trennfix/sw: Single timer version
[eisenbahn.git] / trennfix / sw / hardware.h
1 #ifndef __HARDWARE_H
2 #define __HARDWARE_H
3
4
5 #include "pin_magic.h"
6
7 #define PIN_LED _PIN(PORTB, PORTB2)
8 #define PIN_SENSE _PIN(PORTB, PORTB4)
9 #define PIN_DRIVE _PIN(PORTB, PORTB3)
10 #define PIN_BTN _PIN(PORTB, PB1)
11
12 #define MM_SENSE (!PINVAL(PIN_SENSE))
13 #define BTN_PRESSED (!PINVAL(PIN_BTN))
14
15 #define START_TIMER0 ({TCNT0 = 0; TCCR0B = 2;})
16 #define START_TIMER1 ({TCNT1 = 1; TCCR1 = 7; GTCCR |= 2;})
17 #define STOP_TIMER1 ({TCCR1 = 0; TCNT1 = 1;})
18
19
20 static inline void setup_hw(void)
21 {
22 /* Turn off the 1/8 clock prescaler - now running at 16MHz*/
23 CLKPR = (1 << CLKPCE);
24 CLKPR = 0;
25
26 INPUT_PIN(PIN_SENSE);
27 INPUT_PIN(PIN_BTN);
28 OUTPUT_PIN(PIN_DRIVE);
29 OUTPUT_PIN(PIN_LED);
30 setpin(PIN_BTN, 1); /* Need pullup */
31
32 GIMSK |= _BV(PCIE); /* Enable pin change interrupt for sense port */
33 PCMSK |= _BV(PCINT4); /* PB4, Rail sense input */
34
35 /* Change interrupt for button */
36 PCMSK |= _BV(PCINT1); /* PB1 */
37
38 /* Setup timer 0, used for mm_switch */
39 TCCR0A = 0; /* Normal mode */
40 TCCR0B = 0; /* Timer off */
41 TIMSK |= _BV(OCIE0A); /* Get a match interrupt */
42
43 /* We need 13 + 45,5 us delay, That's 464 clocks @8MHz*/
44 //OCR0A = 91; /* Prescaler 8 is used */
45
46 /* Timer 1 for timeout */
47 /* We set it to 1024us by prescaler 64 and running full 256 */
48 // TCCR1 = 7;
49 // TIMSK |= _BV(TOIE1); /* Overflow interrupt */
50 }
51
52 /* deprecated */
53 #define START_TIMER0 ({TCNT0 = 0; TCCR0B = 2;})
54 #define START_TIMER1 ({TCNT1 = 1; TCCR1 = 7; GTCCR |= 2;})
55 #define STOP_TIMER0 (TCCR0B = 0)
56 #define STOP_TIMER1 ({TCCR1 = 0; TCNT1 = 1;})
57
58 #define TSTART_CLK_TO_SAMPLE_FAST ({TCNT0 = 0; GTCCR |= 1; OCR0A = 110; TCCR0B = 2;})
59 #define TSTART_CLK_TO_SAMPLE_SLOW ({TCNT0 = 0; GTCCR |= 1; OCR0A = 220; TCCR0B = 2;})
60
61 //#define TSTART_CLK_TO_SAMPLE_FAST ({TCNT0 = 0; GTCCR |= 1; OCR0A = 91; TCCR0B = 2;})
62 //#define TSTART_CLK_TO_SAMPLE_SLOW ({TCNT0 = 0; GTCCR |= 1; OCR0A = 182; TCCR0B = 2;})
63
64 #define TSTOP ({TCCR0B = 0;})
65
66
67
68 #endif