[pdp8.git] / sw / f4 / FRTSRC / clock.ra

/
/ VERSION 5A 4/26/77 MH
/
	EXTERN #DISP	/SYSTEM PAGE 0,NEEDED TO
			/PUT CLOCK STATUS ON PG0
			/(CSTAT) FOR USE BY GEN
			/USER CLOCK SERVICE ROUTS
	EXTERN #T812	/RTS CPTYP
	EXTERN ONQI	/INTERRUPT QUEUER
	CLZE=6130	/CLOCK IOTS
	CLSK=6131
	CLLR=6132	/ALSO CLOE
	CLAB=6133
	CLEN=6134
	CLSA=6135
	CSTAT=157	/IDOCLK PUTS CLSA BITS
			/IN HERE
\f	BASE FTMP0
	INDEX FCNWD
	FIELD1 SYNC
	JSA SETUP	/HERE TO READ A STRIG
			/INITIALIZE ARGS
	TRAP4 DOSYNC	/FCNWD (XR) HOLDS STRIG
			/TO READ
	XTA FCNWD	/=ANS=0,1
	FSTA% FTMP1	/GIVE ANS TO CALLER
	JA GOBAK
FTMP0,	F 0.0		/BASE PAGE
FTMP1,	F 0.0
RPTR,	27;ADDR RTBL	/PTR TO RATE TBL, ALSO
			/USED TO FLT OVRCNT (NOTE
			/THAT THE EXPONENT=27)
MINRAT,	F .02		/MIN ALLOWABLE RATE
TOVR,	F 0.0
NAME,	TEXT	+CLOCK +
	ORG	10*3+FTMP0
	FNOP
	JA	NAME+3
	0
GOBAK,	JA	.
RTBL,	F 16.0		/CONSTANT USED TO CHK FOR
			/EXT CLK BIT IN FCNWD
			/THIS CONST MUST BE NE 0
MAXRAT,
F4096,	F 4096.0	/USED TO GET OVRFLO COUNT
	F 100000.0	/FASTEST RATE IN HERTZ
	F 10000.0	/NEXT FASTEST RATE
	F 1000.0
	F 100.0		/SLOWEST RATE
	F 1.0		/USED BY TIME FOR EXT CLK
\f	BASE 0
 
SETUP,	0;0		/HERE TO INIT ALL FPP SUBS
	STARTD
	FLDA 30		/PICK UP RTN TO CALLER
	FSTA GOBAK
	FLDA 0		/GET PTR TO CALLERS ARGS
	SETX FCNWD	/CLOCK XR AND BASE
	SETB FTMP0
	BASE FTMP0
	FSTA FTMP1
	FLDA% FTMP1,P1
	FSTA FTMP0	/PTR TO 1ST ARG
	FLDA% FTMP1,P2
	FSTA FTMP1	/PTR TO 2ND ARG
	FLDA #T812	/TELLS PDP8,PDP12
	ATX CPTYP	/0=8=DK8ES,1=12=KW12A
	STARTF
	FLDA% FTMP0	/=1ST ARG
	ATX FCNWD	/ALWAYS IN FCNWD
	JA SETUP
\f	ENTRY CLOCK
CLOCK,	JSA SETUP	/HERE FOR CLOCK START
	FLDA%	FTMP0
	FSUB RTBL	/FCNWD IS IN FAC,IF GE 16
	JGE ITSEXT	/(RTBL=16.0) THEN USER IS
			/REQUESTING AN EXTERNAL
			/CLOCK I.E. B8 OF FCNWD
			/IS SET.
	FLDA% FTMP1	/=REQUESTED RATE IN HERTZ
	FSUB MINRAT	/.LE. MINUMUM RATE
	JLE GOTR-2	/MEANS STOP CLOCK.
	FADD MINRAT
	FSUB MAXRAT	/CHK FOR TOO FAST
	JGT GOTR-2
	LDX -4,OVRFLO	/THERE ARE 4 BASIC RATES
	LDX 1,RATE	/=INDEX INTO RTBL; UPON
			/TRAP(CLOCK) RATE=(0,
			/2,3,4,5,6) 0=STOP,
			/6=EXTERNAL
			/2-5=PROGRAMMABLE RATES
LOP0,	FLDA% RPTR,RATE+
			/GET NEXT SLOWEST RATE
	FDIV% FTMP1	/=REQUESTED RATE IN HZ.
			/FAC=OVRFLO COUNT;
	FSUB F4096	/MUST BE MODULO 12 BITS.
	JLE GOTR	/FOUND IT
	JXN LOP0,OVRFLO+
	LDX 0,RATE	/RATE IS TOO SLOW, STOP
			/CLOCK.
GOTR,	FADD F4096	/RESTORE
	FSTA TOVR
	ATX OVRFLO	/OVER FLOW COUNT
	TRAP4 SETCLK	/GO START CLOCK
	JA GOBAK		/RTN TO CALLER
ITSEXT,	LDX 6,RATE	/=RATE FOR EXT CLK
	FLDA% FTMP1	/REQUESTED RATE IS
			/INTERPRETED AS OVRFLO
	JA GOTR+1	/WHEN RATE IS EXTERNAL
\f/MAGIC TABLE USED BY SETCLK TO SET CLOCK ENABLE
/BITS. EVEN NUMBERED ENTRIES ARE FOR THE DK8ES;
/ODD NUMBERED ONES ARE FOR THE KW12A.
 
CLKTBL,	0675		/"STANDARD" DK BITS
	300		/STND KW BITS
	1		/DK STRIG1 BIT
	60		/KW STRIG1 BITS
	2		/DK S2
	14		/KW S2
	4		/S3
P3,	3		/S3
	40		/DK ADC ON OVR BIT
	400		/KW ADC ON OVR BIT
 
			/IF NOT NEXT PAGE DO ORG
	IFNEG .-200 < ORG .-SYNC&7600+200+SYNC >
\fSETCLK,	0		/TRAP HERE TO START CLK
			/THIS ROUT HANDLES BOTH
			/DK8ES AND KW12A.
	CLLR		/STOP KW AND SET MODE 0;
			/NOP FOR DK.
	CLEN		/CLR KW12 ENABLE OR
			/READ DK ENABLE.
	CLA
	TAD P7540	/TOGGLE KW MODE 0 TO 1 TO
	CLLR		/CLR CLK COUNTER, OR SET
			/DK ENABLE BITS, RATE FOR
	CLA CMA		/BOTH NOW=7=STOP.
	CLZE		/CLR ALL DK ENABLE BITS,
	CLSA		/CLR STATUS OF BOTH, ALL 
	CLA		/IS NOW CLEAR.
	TAD FCNTBL+1	/SET PTR TO CLKTBL FOR
			/SETTING OF ENABLE REGS.
	TAD CPTYP	/=0 IF PDP8 =1 IF PDP12
	DCA FCNPTR	/TBL ENTRIES ALTERNATE
			/FOR 8 AND 12. CPTYP SETS
			/PTR TO 1ST 8 OR 1ST 12
			/ENTRY
	TAD IDOCLK	/(AC=JMP AROUND). THE
			/FOLLOWING IS ONCE ONLY
			/CODE. THESE LOCS ARE
			/SUBSEQUENTLY USED AS
			/OPERANDS
	DCA .-1
			/THE TAG "ISVBIT" MUST BE
			/IN FRONT OF THE STRIG
			/FLAGS (STFLG) TO COVER
			/THE ILLEGAL CASE OF
			/STRIG 0 IN A FORT CALL
			/TO SYNC.
ISVBIT,	TAD CPTYP	/(AC=0,1) MAKE THE INST
			/RAR CLL (FOR DK) OR THE
			/INST RTR CLL FOR IDOCLK;
STFLG,	RAL CLL		/BECAUSE STATUS BITS FOR
	TAD RARCLL	/STRIGS DIFFER ON DK,KW.
	DCA LOP2+1	/SEE SUB IDOCLK.
			/THE ABOVE 3 LOCS ARE
			/SCHMITT TRIGGER FLAGS.
			/THE ORDER IS S1,S2,S3
			/FOR PDP8 AND S3,S2,S1
			/FOR PDP12. THE MAIN
			/REASON FOR REVERSING
			/THE ORDER IS BECAUSE
			/ENGINEERS NEVER CONSULT
			/PROGRAMMERS WHEN THEY
			/ARE BUILDING NEW 
			/HARDWARE (CHK THE STATUS
			/BITS FOR DK AND KW).
	JMS% KONQI+1	/PUT CLOCK ON THE
ITMP0,	CLSK		/INTERRUPT QUE
			/VIA ONQI.
CLENAB,	ADDR IDOCLK	/THIS LOC WILL HOLD THE
			/ENABLE BITS FOR DK,KW
AROUND,	TAD RATE	/(AC=0,2,3,4,5,6) RATE IS
			/SET BY FPP
	RTR CLL		/START TO POSITION RATE
	RAR		/BITS. B3-B5 FOR DK
			/B0-B2 FOR KW
	TAD CPTYP	/(THIS IS TRICKY) NEED
	RAR		/CPTYP IN LNK BECAUSE
			/POSITION OF RATE BITS
			/DIFFER FOR DK KW.
	TAD% FCNPTR	/AC="STANDARD"
			/ENABLE BITS FOR DK,KW.
	SZL		/IF ITS A KW THE RATE AND
			/AND STND BITS ARE ALREADY
			/POSITIONED AS FOLLOWS:
			/RRR011000000
			/B0-B3 AND B5 WILL GO TO
			/KW CONTROL. B4,B5 WILL
			/GO TO ENABLE. B3 IS ADC
			/ON OVRFLO AND MAY BE SET
			/BELOW. B5 ON CONTROL IS
			/MODE 1. B4 AND B5 ON
			/ENABLE ARE BUFF PRESET TO
			/CLOCK COUNTER AND INTRUPT
			/ON OVRFLO RESPECTIVELY.
	JMP NOBIT-1	/ITS KW GO PUT IN CLENAB.
	RTR		/ITS DK; POSITION RATE TO
	RAR		/B3-B5. NOTE THAT THE LNK
			/(CPTYP=0) IS BEING USED.
	CMA		/NOTE ALSO THAT THE RATE
			/AND STND BITS ARE THE 1S
			/COMP. OF WHAT THEY SHOULD
			/BE, IE CPTYP=LNK=0
			/BECOMES
			/B2=1 OF ENABLE=BUFF
			/PRESET TO CLK CNTR ON
			/OVERFLO. LOOK AT THE RATE
			/BITS IN THE HANDBOOK FOR
			/BOTH DK,KW. R2,R5
			/FOR DK IS 100HZ, 100KHZ
			/RESPECTIVELY. R2,R5 FOR
			/KW IS 100KHZ,100HZ.
			/1S COMP.OF 2=5 ETC.
			/SMARTEN UP STEVE!
			/THE FINAL VALUE OF THE
			/STND DK ENABLE BITS (1ST
			/ENTRY IN CLKTBL) IS LEFT
			/AS AN EXERCISE FOR THE
			/PROGRAMMER.
	JMP NOBIT-1	/GO PUT IN CLENAB
LOP1,	RAR CLL		/ROT 1 FCN BIT INTO LNK.
			/B7=EXT CLK AND IS
			/IGNORED HERE. B8=ADC ON
			/OVRFLO, B9-B11 ARE STRIG3
			/-STRIG1 RESP. BX=1=ENABLE
			/FCN. 0=DISABLE
	DCA FCNWD	/PUT IT BACK (FCNWD IS
			/SET BY FPP)
	SNL		/ENABLE FCN ?
	JMP NOBIT	/NO
	TAD% FCNPTR	/GET BITS FROM THE MAGIC
	TAD CLENAB	/TABLE.
	DCA CLENAB	/UPDATE ENABLE WORD.
NOBIT,	ISZ FCNPTR	/ADV TO NEXT
	ISZ FCNPTR	/TBL ENTRY.
	TAD FCNWD	/WHEN FCNWD GOES TO 0
	AND P17		/WE ARE ALL DONE.
			/THE "AND" IS DONE TO
			/PROTECT AGAINST A BAD
			/ARG FROM THE FORT CALL.
			/IN A FRIENDLY ENIVORN,
			/ITS NOT NECESSARY.
			/NEVER TRUST A FORTRAN
			/"PROGRAMMER".
P7540,	SMA SZA		/SMA IS SUPERFLOUS TO
			/THE ROUT; BUT IT
			/CREATES A NICE CONST.
	JMP LOP1	/MORE TO DO
	DCA STFLG	/CLR THE SCHMITT
	DCA STFLG+1	/TRIGGER FLAGS.
\f	DCA STFLG+2
	TAD OVRFLO	/SET BUFF PRESET
	CIA		/(FPP SET THIS ARG)
	CLAB
	CLA
	TAD CLENAB	/THIS IS FOR KW ONLY.
	AND P377	/AC=3XX. 3= OR BUFF PRE
			/INTO CLK CNTR AND ENAB
			/INT ON OVRFLO.
			/XX ARE THE STRIGS.
	CLEN		/SET KW ENABLE OR
	CLA		/READ DK ENABLE.
	DCA OVRCNT+1	/CLR NUM OF CLK OVRFLOS
	DCA OVRCNT	/SINCE TIME 0.
	TAD CPTYP	/NEED TYPE IN ORDER TO
RARCLL,	RAR CLL		/ISOLATE CONTROL
	TAD CLENAB	/BITS FOR
	SZL		/KW ?
	AND P7540	/YES, B0-B2 IS RATE,
			/B3 IS ADC, B5 IS BUFF
			/PRE TO CLK CNTR ON
			/OVRFLO, B6 IS MOX NIX.
			/IF DK ALL BITS MAY HAVE
			/MEANING
	CLLR		/START THE CLOCK
	CLA
	CIF CDF
	JMP% SETCLK	/RTN TO RTS
\fDOSYNC,	0		/HERE TO DISPOSITION A
			/A SCHMITT TRIGGER.
	TAD CPTYP	/DK AND KW FLAGS ARE IN
	RAR CLL		/REVERSE ORDER. IF DK
			/ARG IS OK; IF KW THEN
			/MUST SET 1=3, 2=2, 3=1
			/TO GET INDEX TO
			/CORRECT FLAG.
	TAD FCNWD	/=REQUESTED STRIG=1,2,3
			/(SET BY FPP)
	SZL		/DK ?
	CIA		/NO KW
	AND P3		/IE 1 GOES TO -1 GOES
			/TO 3 ETC. "AND" ALSO
			/INSURES RANGE IS 0-3.
			/IF ARG IS 0 RESULT IS
			/ALWAYS 0.
	TAD KSTFLG+1	/GET PTR TO FLAG
	DCA SETCLK
	TAD% SETCLK	/FLAG=0 IF TRIG HAS NOT
			/TRIPPED SINCE THE LAST
			/CALL TO SYNC; =1
			/OTHERWISE IE RTN 0=FALSE
	DCA FCNWD	/,1=TRUE (FPP WILL PICK
			/ UP FCNWD)
	DCA% SETCLK	/CLR FLAG ANYWAY
	CIF CDF
	JMP% DOSYNC	/RTN TO RTS
\fIDOCLK,	JMP AROUND	/HERE ON CLOCK INTERRUPT
			/(JMP AROUND IS A ONCE
			/ONLY CONSTANT).
	TAD KSTFLG+1	/SET PTR TO STRIG FLAGS.
	DCA ITMP0
	CLSA		/GET CLOCK BITS.
	DCAZ CSTAT	/SAVE THEM FOR SOME
	TADZ CSTAT	/BODY ELSE.
	SPA		/OVER FLOW ?
	ISZ OVRCNT+1	/YES BUMP LO ORD CNTR
	SKP
	ISZ OVRCNT	/BUMP HI ORD
	JMP DOTRIG	/(HI ORD ISZ SKP IS
			/HARMLESS)
LOP2,	ISZ ITMP0	/ADV STRIG FLAG PTR.
	RAR CLL		/(OR RTR CLL IF KW)
			/IE PUT STRIG BIT IN LNK.
			/IF DK THE ORDER OF
			/INTERROGATION IS S1,S2,S3
			/IF KW THE ORDER IS S3,
			/S2,S1. THE STATUS BITS
			/FOR DK ARE ADJACENT IE
			/ B9(S3),B10(S2),B11(S1)
			/FOR KW ITS EVERY OTHER,
			/B6(S1),B8(S2),B10(S3).
	DCA ISVBIT	/SAVE WHATS LEFT.
	RAL		/COPY LNK INTO FLAG IF=1
	SZA		/IE DONT CLR FLAG WHEN
	DCA% ITMP0	/ITS SET.
	TAD ISVBIT
DOTRIG,	AND P377	/THE "AND" INSURES THAT
			/THE HI ORD BITS ARE
			/CLRED SO THAT ISVBIT
			/GOES TO 0 WHEN ALL
			/STRIGS HAVE BEEN
			/DISPOSITIONED. IE
			/CLR OVRFLO BIT FOR DK,KW
			/AND CLR PRE-EVENT BIT
			/ON KW  IF IT IS SET
	SZA		/DONE ?
	JMP LOP2	/NO
	TAD #CLINT	/CALL USER EXTENDED
	SZA CLA		/CLOCK ROUT ?
	JMS% #CLINT+1	/YES
	JMP% IDOCLK	/RTN TO IHANDL
\fFCNPTR,
OVRCNT,
KONQI,	ADDR ONQI
P17,	17
P377,	377
FCNWD,	0		/FPP XRS
CPTYP,	0
RATE,	0
P1,	1
P2,	2
OVRFLO,
FCNTBL,	ADDR CLKTBL
KSTFLG,	ADDR STFLG-1
	ENTRY #CLINT
#CLINT,	0;0
	ENTRY TIME	/FIGURE WHAT TIME IT IS
TIME,	JSA SETUP
	FLDA RPTR	/=27;X;X IS USED TO FLOAT
	STARTD
	FLDA# OVRCNT	/NUM OF CLK OVRFLOS SINCE
	STARTF		/TIME 0
	FNORM
	FMUL TOVR	/=NUM OF BASIC TICKS PER
			/CLOCK OVER FLOW.
			/FAC=NUM OF TICKS SINCE
			/TIME 0.
	FDIV% RPTR,RATE	/DIV BY BASIC RATE IN HZ
			/OR 1 IF EXTERNAL CLK.
	FSTA% FTMP0	/GIVE ANS TO CALLER, ALSO
			/LEAVE ANS IN FAC IN
			/CASE TIME WAS A FCN
			/CALL. ANS=ELAPSED TIME IN
			/SECONDS SINCE TIME 0 OR
			/NUM OF EXTERNAL UNIT
	JA GOBAK	/TICKS
\f
Commit	Line	Data
7af5ad59 PH	1	/
	2	/ VERSION 5A 4/26/77 MH
	3	/
	4	EXTERN #DISP /SYSTEM PAGE 0,NEEDED TO
	5	/PUT CLOCK STATUS ON PG0
	6	/(CSTAT) FOR USE BY GEN
	7	/USER CLOCK SERVICE ROUTS
	8	EXTERN #T812 /RTS CPTYP
	9	EXTERN ONQI /INTERRUPT QUEUER
	10	CLZE=6130 /CLOCK IOTS
	11	CLSK=6131
	12	CLLR=6132 /ALSO CLOE
	13	CLAB=6133
	14	CLEN=6134
	15	CLSA=6135
	16	CSTAT=157 /IDOCLK PUTS CLSA BITS
	17	/IN HERE
	18	\f BASE FTMP0
	19	INDEX FCNWD
	20	FIELD1 SYNC
	21	JSA SETUP /HERE TO READ A STRIG
	22	/INITIALIZE ARGS
	23	TRAP4 DOSYNC /FCNWD (XR) HOLDS STRIG
	24	/TO READ
	25	XTA FCNWD /=ANS=0,1
	26	FSTA% FTMP1 /GIVE ANS TO CALLER
	27	JA GOBAK
	28	FTMP0, F 0.0 /BASE PAGE
	29	FTMP1, F 0.0
	30	RPTR, 27;ADDR RTBL /PTR TO RATE TBL, ALSO
	31	/USED TO FLT OVRCNT (NOTE
	32	/THAT THE EXPONENT=27)
	33	MINRAT, F .02 /MIN ALLOWABLE RATE
	34	TOVR, F 0.0
	35	NAME, TEXT +CLOCK +
	36	ORG 10*3+FTMP0
	37	FNOP
	38	JA NAME+3
	39	0
	40	GOBAK, JA .
	41	RTBL, F 16.0 /CONSTANT USED TO CHK FOR
	42	/EXT CLK BIT IN FCNWD
	43	/THIS CONST MUST BE NE 0
	44	MAXRAT,
	45	F4096, F 4096.0 /USED TO GET OVRFLO COUNT
	46	F 100000.0 /FASTEST RATE IN HERTZ
	47	F 10000.0 /NEXT FASTEST RATE
	48	F 1000.0
	49	F 100.0 /SLOWEST RATE
	50	F 1.0 /USED BY TIME FOR EXT CLK
	51	\f BASE 0
	52
	53	SETUP, 0;0 /HERE TO INIT ALL FPP SUBS
	54	STARTD
	55	FLDA 30 /PICK UP RTN TO CALLER
	56	FSTA GOBAK
	57	FLDA 0 /GET PTR TO CALLERS ARGS
	58	SETX FCNWD /CLOCK XR AND BASE
	59	SETB FTMP0
	60	BASE FTMP0
	61	FSTA FTMP1
	62	FLDA% FTMP1,P1
	63	FSTA FTMP0 /PTR TO 1ST ARG
	64	FLDA% FTMP1,P2
65	FSTA FTMP1 /PTR TO 2ND ARG
66	FLDA #T812 /TELLS PDP8,PDP12
67	ATX CPTYP /0=8=DK8ES,1=12=KW12A
68	STARTF
69	FLDA% FTMP0 /=1ST ARG
70	ATX FCNWD /ALWAYS IN FCNWD
71	JA SETUP
72	\f ENTRY CLOCK
73	CLOCK, JSA SETUP /HERE FOR CLOCK START
74	FLDA% FTMP0
75	FSUB RTBL /FCNWD IS IN FAC,IF GE 16
76	JGE ITSEXT /(RTBL=16.0) THEN USER IS
77	/REQUESTING AN EXTERNAL
78	/CLOCK I.E. B8 OF FCNWD
79	/IS SET.
80	FLDA% FTMP1 /=REQUESTED RATE IN HERTZ
81	FSUB MINRAT /.LE. MINUMUM RATE
82	JLE GOTR-2 /MEANS STOP CLOCK.
83	FADD MINRAT
84	FSUB MAXRAT /CHK FOR TOO FAST
85	JGT GOTR-2
86	LDX -4,OVRFLO /THERE ARE 4 BASIC RATES
87	LDX 1,RATE /=INDEX INTO RTBL; UPON
88	/TRAP(CLOCK) RATE=(0,
89	/2,3,4,5,6) 0=STOP,
90	/6=EXTERNAL
91	/2-5=PROGRAMMABLE RATES
92	LOP0, FLDA% RPTR,RATE+
93	/GET NEXT SLOWEST RATE
94	FDIV% FTMP1 /=REQUESTED RATE IN HZ.
95	/FAC=OVRFLO COUNT;
96	FSUB F4096 /MUST BE MODULO 12 BITS.
97	JLE GOTR /FOUND IT
98	JXN LOP0,OVRFLO+
99	LDX 0,RATE /RATE IS TOO SLOW, STOP
100	/CLOCK.
101	GOTR, FADD F4096 /RESTORE
102	FSTA TOVR
103	ATX OVRFLO /OVER FLOW COUNT
104	TRAP4 SETCLK /GO START CLOCK
105	JA GOBAK /RTN TO CALLER
106	ITSEXT, LDX 6,RATE /=RATE FOR EXT CLK
107	FLDA% FTMP1 /REQUESTED RATE IS
108	/INTERPRETED AS OVRFLO
109	JA GOTR+1 /WHEN RATE IS EXTERNAL
110	\f/MAGIC TABLE USED BY SETCLK TO SET CLOCK ENABLE
111	/BITS. EVEN NUMBERED ENTRIES ARE FOR THE DK8ES;
112	/ODD NUMBERED ONES ARE FOR THE KW12A.
113
114	CLKTBL, 0675 /"STANDARD" DK BITS
115	300 /STND KW BITS
116	1 /DK STRIG1 BIT
117	60 /KW STRIG1 BITS
118	2 /DK S2
119	14 /KW S2
120	4 /S3
121	P3, 3 /S3
122	40 /DK ADC ON OVR BIT
123	400 /KW ADC ON OVR BIT
124
125	/IF NOT NEXT PAGE DO ORG
126	IFNEG .-200 < ORG .-SYNC&7600+200+SYNC >
127	\fSETCLK, 0 /TRAP HERE TO START CLK
128	/THIS ROUT HANDLES BOTH
129	/DK8ES AND KW12A.
130	CLLR /STOP KW AND SET MODE 0;
131	/NOP FOR DK.
132	CLEN /CLR KW12 ENABLE OR
133	/READ DK ENABLE.
134	CLA
135	TAD P7540 /TOGGLE KW MODE 0 TO 1 TO
136	CLLR /CLR CLK COUNTER, OR SET
137	/DK ENABLE BITS, RATE FOR
138	CLA CMA /BOTH NOW=7=STOP.
139	CLZE /CLR ALL DK ENABLE BITS,
140	CLSA /CLR STATUS OF BOTH, ALL
141	CLA /IS NOW CLEAR.
142	TAD FCNTBL+1 /SET PTR TO CLKTBL FOR
143	/SETTING OF ENABLE REGS.
144	TAD CPTYP /=0 IF PDP8 =1 IF PDP12
145	DCA FCNPTR /TBL ENTRIES ALTERNATE
146	/FOR 8 AND 12. CPTYP SETS
147	/PTR TO 1ST 8 OR 1ST 12
148	/ENTRY
149	TAD IDOCLK /(AC=JMP AROUND). THE
150	/FOLLOWING IS ONCE ONLY
151	/CODE. THESE LOCS ARE
152	/SUBSEQUENTLY USED AS
153	/OPERANDS
154	DCA .-1
155	/THE TAG "ISVBIT" MUST BE
156	/IN FRONT OF THE STRIG
157	/FLAGS (STFLG) TO COVER
158	/THE ILLEGAL CASE OF
159	/STRIG 0 IN A FORT CALL
160	/TO SYNC.
161	ISVBIT, TAD CPTYP /(AC=0,1) MAKE THE INST
162	/RAR CLL (FOR DK) OR THE
163	/INST RTR CLL FOR IDOCLK;
164	STFLG, RAL CLL /BECAUSE STATUS BITS FOR
165	TAD RARCLL /STRIGS DIFFER ON DK,KW.
166	DCA LOP2+1 /SEE SUB IDOCLK.
167	/THE ABOVE 3 LOCS ARE
168	/SCHMITT TRIGGER FLAGS.
169	/THE ORDER IS S1,S2,S3
170	/FOR PDP8 AND S3,S2,S1
171	/FOR PDP12. THE MAIN
172	/REASON FOR REVERSING
173	/THE ORDER IS BECAUSE
174	/ENGINEERS NEVER CONSULT
175	/PROGRAMMERS WHEN THEY
176	/ARE BUILDING NEW
177	/HARDWARE (CHK THE STATUS
178	/BITS FOR DK AND KW).
179	JMS% KONQI+1 /PUT CLOCK ON THE
180	ITMP0, CLSK /INTERRUPT QUE
181	/VIA ONQI.
182	CLENAB, ADDR IDOCLK /THIS LOC WILL HOLD THE
183	/ENABLE BITS FOR DK,KW
184	AROUND, TAD RATE /(AC=0,2,3,4,5,6) RATE IS
185	/SET BY FPP
186	RTR CLL /START TO POSITION RATE
187	RAR /BITS. B3-B5 FOR DK
188	/B0-B2 FOR KW
189	TAD CPTYP /(THIS IS TRICKY) NEED
190	RAR /CPTYP IN LNK BECAUSE
191	/POSITION OF RATE BITS
192	/DIFFER FOR DK KW.
193	TAD% FCNPTR /AC="STANDARD"
194	/ENABLE BITS FOR DK,KW.
195	SZL /IF ITS A KW THE RATE AND
196	/AND STND BITS ARE ALREADY
197	/POSITIONED AS FOLLOWS:
198	/RRR011000000
199	/B0-B3 AND B5 WILL GO TO
200	/KW CONTROL. B4,B5 WILL
201	/GO TO ENABLE. B3 IS ADC
202	/ON OVRFLO AND MAY BE SET
203	/BELOW. B5 ON CONTROL IS
204	/MODE 1. B4 AND B5 ON
205	/ENABLE ARE BUFF PRESET TO
206	/CLOCK COUNTER AND INTRUPT
207	/ON OVRFLO RESPECTIVELY.
208	JMP NOBIT-1 /ITS KW GO PUT IN CLENAB.
209	RTR /ITS DK; POSITION RATE TO
210	RAR /B3-B5. NOTE THAT THE LNK
211	/(CPTYP=0) IS BEING USED.
212	CMA /NOTE ALSO THAT THE RATE
213	/AND STND BITS ARE THE 1S
214	/COMP. OF WHAT THEY SHOULD
215	/BE, IE CPTYP=LNK=0
216	/BECOMES
217	/B2=1 OF ENABLE=BUFF
218	/PRESET TO CLK CNTR ON
219	/OVERFLO. LOOK AT THE RATE
220	/BITS IN THE HANDBOOK FOR
221	/BOTH DK,KW. R2,R5
222	/FOR DK IS 100HZ, 100KHZ
223	/RESPECTIVELY. R2,R5 FOR
224	/KW IS 100KHZ,100HZ.
225	/1S COMP.OF 2=5 ETC.
226	/SMARTEN UP STEVE!
227	/THE FINAL VALUE OF THE
228	/STND DK ENABLE BITS (1ST
229	/ENTRY IN CLKTBL) IS LEFT
230	/AS AN EXERCISE FOR THE
231	/PROGRAMMER.
232	JMP NOBIT-1 /GO PUT IN CLENAB
233	LOP1, RAR CLL /ROT 1 FCN BIT INTO LNK.
234	/B7=EXT CLK AND IS
235	/IGNORED HERE. B8=ADC ON
236	/OVRFLO, B9-B11 ARE STRIG3
237	/-STRIG1 RESP. BX=1=ENABLE
238	/FCN. 0=DISABLE
239	DCA FCNWD /PUT IT BACK (FCNWD IS
240	/SET BY FPP)
241	SNL /ENABLE FCN ?
242	JMP NOBIT /NO
243	TAD% FCNPTR /GET BITS FROM THE MAGIC
244	TAD CLENAB /TABLE.
245	DCA CLENAB /UPDATE ENABLE WORD.
246	NOBIT, ISZ FCNPTR /ADV TO NEXT
247	ISZ FCNPTR /TBL ENTRY.
248	TAD FCNWD /WHEN FCNWD GOES TO 0
249	AND P17 /WE ARE ALL DONE.
250	/THE "AND" IS DONE TO
251	/PROTECT AGAINST A BAD
252	/ARG FROM THE FORT CALL.
253	/IN A FRIENDLY ENIVORN,
254	/ITS NOT NECESSARY.
255	/NEVER TRUST A FORTRAN
256	/"PROGRAMMER".
257	P7540, SMA SZA /SMA IS SUPERFLOUS TO
258	/THE ROUT; BUT IT
259	/CREATES A NICE CONST.
260	JMP LOP1 /MORE TO DO
261	DCA STFLG /CLR THE SCHMITT
262	DCA STFLG+1 /TRIGGER FLAGS.
263	\f DCA STFLG+2
264	TAD OVRFLO /SET BUFF PRESET
265	CIA /(FPP SET THIS ARG)
266	CLAB
267	CLA
268	TAD CLENAB /THIS IS FOR KW ONLY.
269	AND P377 /AC=3XX. 3= OR BUFF PRE
270	/INTO CLK CNTR AND ENAB
271	/INT ON OVRFLO.
272	/XX ARE THE STRIGS.
273	CLEN /SET KW ENABLE OR
274	CLA /READ DK ENABLE.
275	DCA OVRCNT+1 /CLR NUM OF CLK OVRFLOS
276	DCA OVRCNT /SINCE TIME 0.
277	TAD CPTYP /NEED TYPE IN ORDER TO
278	RARCLL, RAR CLL /ISOLATE CONTROL
279	TAD CLENAB /BITS FOR
280	SZL /KW ?
281	AND P7540 /YES, B0-B2 IS RATE,
282	/B3 IS ADC, B5 IS BUFF
283	/PRE TO CLK CNTR ON
284	/OVRFLO, B6 IS MOX NIX.
285	/IF DK ALL BITS MAY HAVE
286	/MEANING
287	CLLR /START THE CLOCK
288	CLA
289	CIF CDF
290	JMP% SETCLK /RTN TO RTS
291	\fDOSYNC, 0 /HERE TO DISPOSITION A
292	/A SCHMITT TRIGGER.
293	TAD CPTYP /DK AND KW FLAGS ARE IN
294	RAR CLL /REVERSE ORDER. IF DK
295	/ARG IS OK; IF KW THEN
296	/MUST SET 1=3, 2=2, 3=1
297	/TO GET INDEX TO
298	/CORRECT FLAG.
299	TAD FCNWD /=REQUESTED STRIG=1,2,3
300	/(SET BY FPP)
301	SZL /DK ?
302	CIA /NO KW
303	AND P3 /IE 1 GOES TO -1 GOES
304	/TO 3 ETC. "AND" ALSO
305	/INSURES RANGE IS 0-3.
306	/IF ARG IS 0 RESULT IS
307	/ALWAYS 0.
308	TAD KSTFLG+1 /GET PTR TO FLAG
309	DCA SETCLK
310	TAD% SETCLK /FLAG=0 IF TRIG HAS NOT
311	/TRIPPED SINCE THE LAST
312	/CALL TO SYNC; =1
313	/OTHERWISE IE RTN 0=FALSE
314	DCA FCNWD /,1=TRUE (FPP WILL PICK
315	/ UP FCNWD)
316	DCA% SETCLK /CLR FLAG ANYWAY
317	CIF CDF
318	JMP% DOSYNC /RTN TO RTS
319	\fIDOCLK, JMP AROUND /HERE ON CLOCK INTERRUPT
320	/(JMP AROUND IS A ONCE
321	/ONLY CONSTANT).
322	TAD KSTFLG+1 /SET PTR TO STRIG FLAGS.
323	DCA ITMP0
324	CLSA /GET CLOCK BITS.
325	DCAZ CSTAT /SAVE THEM FOR SOME
326	TADZ CSTAT /BODY ELSE.
327	SPA /OVER FLOW ?
328	ISZ OVRCNT+1 /YES BUMP LO ORD CNTR
329	SKP
330	ISZ OVRCNT /BUMP HI ORD
331	JMP DOTRIG /(HI ORD ISZ SKP IS
332	/HARMLESS)
333	LOP2, ISZ ITMP0 /ADV STRIG FLAG PTR.
334	RAR CLL /(OR RTR CLL IF KW)
335	/IE PUT STRIG BIT IN LNK.
336	/IF DK THE ORDER OF
337	/INTERROGATION IS S1,S2,S3
338	/IF KW THE ORDER IS S3,
339	/S2,S1. THE STATUS BITS
340	/FOR DK ARE ADJACENT IE
341	/ B9(S3),B10(S2),B11(S1)
342	/FOR KW ITS EVERY OTHER,
343	/B6(S1),B8(S2),B10(S3).
344	DCA ISVBIT /SAVE WHATS LEFT.
345	RAL /COPY LNK INTO FLAG IF=1
346	SZA /IE DONT CLR FLAG WHEN
347	DCA% ITMP0 /ITS SET.
348	TAD ISVBIT
349	DOTRIG, AND P377 /THE "AND" INSURES THAT
350	/THE HI ORD BITS ARE
351	/CLRED SO THAT ISVBIT
352	/GOES TO 0 WHEN ALL
353	/STRIGS HAVE BEEN
354	/DISPOSITIONED. IE
355	/CLR OVRFLO BIT FOR DK,KW
356	/AND CLR PRE-EVENT BIT
357	/ON KW IF IT IS SET
358	SZA /DONE ?
359	JMP LOP2 /NO
360	TAD #CLINT /CALL USER EXTENDED
361	SZA CLA /CLOCK ROUT ?
362	JMS% #CLINT+1 /YES
363	JMP% IDOCLK /RTN TO IHANDL
364	\fFCNPTR,
365	OVRCNT,
366	KONQI, ADDR ONQI
367	P17, 17
368	P377, 377
369	FCNWD, 0 /FPP XRS
370	CPTYP, 0
371	RATE, 0
372	P1, 1
373	P2, 2
374	OVRFLO,
375	FCNTBL, ADDR CLKTBL
376	KSTFLG, ADDR STFLG-1
377	ENTRY #CLINT
378	#CLINT, 0;0
379	ENTRY TIME /FIGURE WHAT TIME IT IS
380	TIME, JSA SETUP
381	FLDA RPTR /=27;X;X IS USED TO FLOAT
382	STARTD
383	FLDA# OVRCNT /NUM OF CLK OVRFLOS SINCE
384	STARTF /TIME 0
385	FNORM
386	FMUL TOVR /=NUM OF BASIC TICKS PER
387	/CLOCK OVER FLOW.
388	/FAC=NUM OF TICKS SINCE
389	/TIME 0.
390	FDIV% RPTR,RATE /DIV BY BASIC RATE IN HZ
391	/OR 1 IF EXTERNAL CLK.
392	FSTA% FTMP0 /GIVE ANS TO CALLER, ALSO
393	/LEAVE ANS IN FAC IN
394	/CASE TIME WAS A FCN
395	/CALL. ANS=ELAPSED TIME IN
396	/SECONDS SINCE TIME 0 OR
397	/NUM OF EXTERNAL UNIT
398	JA GOBAK /TICKS
399	\f