projects / simh.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
First Commit of my working state
[simh.git] / AltairZ80 / insns.h
CommitLineData
196ba1fc
PH		 1/* insns.h header file for insns.c\r
2 * $Id: insns.h,v 1.1 2004/02/11 19:01:38 perrin Exp $\r
3 *\r
4 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and\r
5 * Julian Hall. All rights reserved. The software is\r
6 * redistributable under the licence given in the file "Licence"\r
7 * distributed in the NASM archive.\r
8 */\r
9\r
10#ifndef NASM_INSNS_H\r
11#define NASM_INSNS_H\r
12\r
13/* This file is auto-generated from insns.dat by insns.pl - don't edit it */\r
14\r
15/* This file in included by nasm.h */\r
16\r
17/* Instruction names */\r
18enum {\r
19 I_AAA,\r
20 I_AAD,\r
21 I_AAM,\r
22 I_AAS,\r
23 I_ADC,\r
24 I_ADD,\r
25 I_ADDPD,\r
26 I_ADDPS,\r
27 I_ADDSD,\r
28 I_ADDSS,\r
29 I_ADDSUBPD,\r
30 I_ADDSUBPS,\r
31 I_AND,\r
32 I_ANDNPD,\r
33 I_ANDNPS,\r
34 I_ANDPD,\r
35 I_ANDPS,\r
36 I_ARPL,\r
37 I_BOUND,\r
38 I_BSF,\r
39 I_BSR,\r
40 I_BSWAP,\r
41 I_BT,\r
42 I_BTC,\r
43 I_BTR,\r
44 I_BTS,\r
45 I_CALL,\r
46 I_CBW,\r
47 I_CDQ,\r
48 I_CLC,\r
49 I_CLD,\r
50 I_CLFLUSH,\r
51 I_CLI,\r
52 I_CLTS,\r
53 I_CMC,\r
54 I_CMP,\r
55 I_CMPEQPD,\r
56 I_CMPEQPS,\r
57 I_CMPEQSD,\r
58 I_CMPEQSS,\r
59 I_CMPLEPD,\r
60 I_CMPLEPS,\r
61 I_CMPLESD,\r
62 I_CMPLESS,\r
63 I_CMPLTPD,\r
64 I_CMPLTPS,\r
65 I_CMPLTSD,\r
66 I_CMPLTSS,\r
67 I_CMPNEQPD,\r
68 I_CMPNEQPS,\r
69 I_CMPNEQSD,\r
70 I_CMPNEQSS,\r
71 I_CMPNLEPD,\r
72 I_CMPNLEPS,\r
73 I_CMPNLESD,\r
74 I_CMPNLESS,\r
75 I_CMPNLTPD,\r
76 I_CMPNLTPS,\r
77 I_CMPNLTSD,\r
78 I_CMPNLTSS,\r
79 I_CMPORDPD,\r
80 I_CMPORDPS,\r
81 I_CMPORDSD,\r
82 I_CMPORDSS,\r
83 I_CMPPD,\r
84 I_CMPPS,\r
85 I_CMPSB,\r
86 I_CMPSD,\r
87 I_CMPSS,\r
88 I_CMPSW,\r
89 I_CMPUNORDPD,\r
90 I_CMPUNORDPS,\r
91 I_CMPUNORDSD,\r
92 I_CMPUNORDSS,\r
93 I_CMPXCHG,\r
94 I_CMPXCHG486,\r
95 I_CMPXCHG8B,\r
96 I_COMISD,\r
97 I_COMISS,\r
98 I_CPUID,\r
99 I_CVTDQ2PD,\r
100 I_CVTDQ2PS,\r
101 I_CVTPD2DQ,\r
102 I_CVTPD2PI,\r
103 I_CVTPD2PS,\r
104 I_CVTPI2PD,\r
105 I_CVTPI2PS,\r
106 I_CVTPS2DQ,\r
107 I_CVTPS2PD,\r
108 I_CVTPS2PI,\r
109 I_CVTSD2SI,\r
110 I_CVTSD2SS,\r
111 I_CVTSI2SD,\r
112 I_CVTSI2SS,\r
113 I_CVTSS2SD,\r
114 I_CVTSS2SI,\r
115 I_CVTTPD2DQ,\r
116 I_CVTTPD2PI,\r
117 I_CVTTPS2DQ,\r
118 I_CVTTPS2PI,\r
119 I_CVTTSD2SI,\r
120 I_CVTTSS2SI,\r
121 I_CWD,\r
122 I_CWDE,\r
123 I_DAA,\r
124 I_DAS,\r
125 I_DB,\r
126 I_DD,\r
127 I_DEC,\r
128 I_DIV,\r
129 I_DIVPD,\r
130 I_DIVPS,\r
131 I_DIVSD,\r
132 I_DIVSS,\r
133 I_DQ,\r
134 I_DT,\r
135 I_DW,\r
136 I_EMMS,\r
137 I_ENTER,\r
138 I_EQU,\r
139 I_F2XM1,\r
140 I_FABS,\r
141 I_FADD,\r
142 I_FADDP,\r
143 I_FBLD,\r
144 I_FBSTP,\r
145 I_FCHS,\r
146 I_FCLEX,\r
147 I_FCMOVB,\r
148 I_FCMOVBE,\r
149 I_FCMOVE,\r
150 I_FCMOVNB,\r
151 I_FCMOVNBE,\r
152 I_FCMOVNE,\r
153 I_FCMOVNU,\r
154 I_FCMOVU,\r
155 I_FCOM,\r
156 I_FCOMI,\r
157 I_FCOMIP,\r
158 I_FCOMP,\r
159 I_FCOMPP,\r
160 I_FCOS,\r
161 I_FDECSTP,\r
162 I_FDISI,\r
163 I_FDIV,\r
164 I_FDIVP,\r
165 I_FDIVR,\r
166 I_FDIVRP,\r
167 I_FEMMS,\r
168 I_FENI,\r
169 I_FFREE,\r
170 I_FFREEP,\r
171 I_FIADD,\r
172 I_FICOM,\r
173 I_FICOMP,\r
174 I_FIDIV,\r
175 I_FIDIVR,\r
176 I_FILD,\r
177 I_FIMUL,\r
178 I_FINCSTP,\r
179 I_FINIT,\r
180 I_FIST,\r
181 I_FISTP,\r
182 I_FISTTP,\r
183 I_FISUB,\r
184 I_FISUBR,\r
185 I_FLD,\r
186 I_FLD1,\r
187 I_FLDCW,\r
188 I_FLDENV,\r
189 I_FLDL2E,\r
190 I_FLDL2T,\r
191 I_FLDLG2,\r
192 I_FLDLN2,\r
193 I_FLDPI,\r
194 I_FLDZ,\r
195 I_FMUL,\r
196 I_FMULP,\r
197 I_FNCLEX,\r
198 I_FNDISI,\r
199 I_FNENI,\r
200 I_FNINIT,\r
201 I_FNOP,\r
202 I_FNSAVE,\r
203 I_FNSTCW,\r
204 I_FNSTENV,\r
205 I_FNSTSW,\r
206 I_FPATAN,\r
207 I_FPREM,\r
208 I_FPREM1,\r
209 I_FPTAN,\r
210 I_FRNDINT,\r
211 I_FRSTOR,\r
212 I_FSAVE,\r
213 I_FSCALE,\r
214 I_FSETPM,\r
215 I_FSIN,\r
216 I_FSINCOS,\r
217 I_FSQRT,\r
218 I_FST,\r
219 I_FSTCW,\r
220 I_FSTENV,\r
221 I_FSTP,\r
222 I_FSTSW,\r
223 I_FSUB,\r
224 I_FSUBP,\r
225 I_FSUBR,\r
226 I_FSUBRP,\r
227 I_FTST,\r
228 I_FUCOM,\r
229 I_FUCOMI,\r
230 I_FUCOMIP,\r
231 I_FUCOMP,\r
232 I_FUCOMPP,\r
233 I_FWAIT,\r
234 I_FXAM,\r
235 I_FXCH,\r
236 I_FXRSTOR,\r
237 I_FXSAVE,\r
238 I_FXTRACT,\r
239 I_FYL2X,\r
240 I_FYL2XP1,\r
241 I_HADDPD,\r
242 I_HADDPS,\r
243 I_HLT,\r
244 I_HSUBPD,\r
245 I_HSUBPS,\r
246 I_IBTS,\r
247 I_ICEBP,\r
248 I_IDIV,\r
249 I_IMUL,\r
250 I_IN,\r
251 I_INC,\r
252 I_INCBIN,\r
253 I_INSB,\r
254 I_INSD,\r
255 I_INSW,\r
256 I_INT,\r
257 I_INT01,\r
258 I_INT03,\r
259 I_INT1,\r
260 I_INT3,\r
261 I_INTO,\r
262 I_INVD,\r
263 I_INVLPG,\r
264 I_IRET,\r
265 I_IRETD,\r
266 I_IRETW,\r
267 I_JCXZ,\r
268 I_JECXZ,\r
269 I_JMP,\r
270 I_JMPE,\r
271 I_LAHF,\r
272 I_LAR,\r
273 I_LDDQU,\r
274 I_LDMXCSR,\r
275 I_LDS,\r
276 I_LEA,\r
277 I_LEAVE,\r
278 I_LES,\r
279 I_LFENCE,\r
280 I_LFS,\r
281 I_LGDT,\r
282 I_LGS,\r
283 I_LIDT,\r
284 I_LLDT,\r
285 I_LMSW,\r
286 I_LOADALL,\r
287 I_LOADALL286,\r
288 I_LODSB,\r
289 I_LODSD,\r
290 I_LODSW,\r
291 I_LOOP,\r
292 I_LOOPE,\r
293 I_LOOPNE,\r
294 I_LOOPNZ,\r
295 I_LOOPZ,\r
296 I_LSL,\r
297 I_LSS,\r
298 I_LTR,\r
299 I_MASKMOVDQU,\r
300 I_MASKMOVQ,\r
301 I_MAXPD,\r
302 I_MAXPS,\r
303 I_MAXSD,\r
304 I_MAXSS,\r
305 I_MFENCE,\r
306 I_MINPD,\r
307 I_MINPS,\r
308 I_MINSD,\r
309 I_MINSS,\r
310 I_MONITOR,\r
311 I_MOV,\r
312 I_MOVAPD,\r
313 I_MOVAPS,\r
314 I_MOVD,\r
315 I_MOVDDUP,\r
316 I_MOVDQ2Q,\r
317 I_MOVDQA,\r
318 I_MOVDQU,\r
319 I_MOVHLPS,\r
320 I_MOVHPD,\r
321 I_MOVHPS,\r
322 I_MOVLHPS,\r
323 I_MOVLPD,\r
324 I_MOVLPS,\r
325 I_MOVMSKPD,\r
326 I_MOVMSKPS,\r
327 I_MOVNTDQ,\r
328 I_MOVNTI,\r
329 I_MOVNTPD,\r
330 I_MOVNTPS,\r
331 I_MOVNTQ,\r
332 I_MOVQ,\r
333 I_MOVQ2DQ,\r
334 I_MOVSB,\r
335 I_MOVSD,\r
336 I_MOVSHDUP,\r
337 I_MOVSLDUP,\r
338 I_MOVSS,\r
339 I_MOVSW,\r
340 I_MOVSX,\r
341 I_MOVUPD,\r
342 I_MOVUPS,\r
343 I_MOVZX,\r
344 I_MUL,\r
345 I_MULPD,\r
346 I_MULPS,\r
347 I_MULSD,\r
348 I_MULSS,\r
349 I_MWAIT,\r
350 I_NEG,\r
351 I_NOP,\r
352 I_NOT,\r
353 I_OR,\r
354 I_ORPD,\r
355 I_ORPS,\r
356 I_OUT,\r
357 I_OUTSB,\r
358 I_OUTSD,\r
359 I_OUTSW,\r
360 I_PACKSSDW,\r
361 I_PACKSSWB,\r
362 I_PACKUSWB,\r
363 I_PADDB,\r
364 I_PADDD,\r
365 I_PADDQ,\r
366 I_PADDSB,\r
367 I_PADDSIW,\r
368 I_PADDSW,\r
369 I_PADDUSB,\r
370 I_PADDUSW,\r
371 I_PADDW,\r
372 I_PAND,\r
373 I_PANDN,\r
374 I_PAUSE,\r
375 I_PAVEB,\r
376 I_PAVGB,\r
377 I_PAVGUSB,\r
378 I_PAVGW,\r
379 I_PCMPEQB,\r
380 I_PCMPEQD,\r
381 I_PCMPEQW,\r
382 I_PCMPGTB,\r
383 I_PCMPGTD,\r
384 I_PCMPGTW,\r
385 I_PDISTIB,\r
386 I_PEXTRW,\r
387 I_PF2ID,\r
388 I_PF2IW,\r
389 I_PFACC,\r
390 I_PFADD,\r
391 I_PFCMPEQ,\r
392 I_PFCMPGE,\r
393 I_PFCMPGT,\r
394 I_PFMAX,\r
395 I_PFMIN,\r
396 I_PFMUL,\r
397 I_PFNACC,\r
398 I_PFPNACC,\r
399 I_PFRCP,\r
400 I_PFRCPIT1,\r
401 I_PFRCPIT2,\r
402 I_PFRSQIT1,\r
403 I_PFRSQRT,\r
404 I_PFSUB,\r
405 I_PFSUBR,\r
406 I_PI2FD,\r
407 I_PI2FW,\r
408 I_PINSRW,\r
409 I_PMACHRIW,\r
410 I_PMADDWD,\r
411 I_PMAGW,\r
412 I_PMAXSW,\r
413 I_PMAXUB,\r
414 I_PMINSW,\r
415 I_PMINUB,\r
416 I_PMOVMSKB,\r
417 I_PMULHRIW,\r
418 I_PMULHRWA,\r
419 I_PMULHRWC,\r
420 I_PMULHUW,\r
421 I_PMULHW,\r
422 I_PMULLW,\r
423 I_PMULUDQ,\r
424 I_PMVGEZB,\r
425 I_PMVLZB,\r
426 I_PMVNZB,\r
427 I_PMVZB,\r
428 I_POP,\r
429 I_POPA,\r
430 I_POPAD,\r
431 I_POPAW,\r
432 I_POPF,\r
433 I_POPFD,\r
434 I_POPFW,\r
435 I_POR,\r
436 I_PREFETCH,\r
437 I_PREFETCHNTA,\r
438 I_PREFETCHT0,\r
439 I_PREFETCHT1,\r
440 I_PREFETCHT2,\r
441 I_PREFETCHW,\r
442 I_PSADBW,\r
443 I_PSHUFD,\r
444 I_PSHUFHW,\r
445 I_PSHUFLW,\r
446 I_PSHUFW,\r
447 I_PSLLD,\r
448 I_PSLLDQ,\r
449 I_PSLLQ,\r
450 I_PSLLW,\r
451 I_PSRAD,\r
452 I_PSRAW,\r
453 I_PSRLD,\r
454 I_PSRLDQ,\r
455 I_PSRLQ,\r
456 I_PSRLW,\r
457 I_PSUBB,\r
458 I_PSUBD,\r
459 I_PSUBQ,\r
460 I_PSUBSB,\r
461 I_PSUBSIW,\r
462 I_PSUBSW,\r
463 I_PSUBUSB,\r
464 I_PSUBUSW,\r
465 I_PSUBW,\r
466 I_PSWAPD,\r
467 I_PUNPCKHBW,\r
468 I_PUNPCKHDQ,\r
469 I_PUNPCKHQDQ,\r
470 I_PUNPCKHWD,\r
471 I_PUNPCKLBW,\r
472 I_PUNPCKLDQ,\r
473 I_PUNPCKLQDQ,\r
474 I_PUNPCKLWD,\r
475 I_PUSH,\r
476 I_PUSHA,\r
477 I_PUSHAD,\r
478 I_PUSHAW,\r
479 I_PUSHF,\r
480 I_PUSHFD,\r
481 I_PUSHFW,\r
482 I_PXOR,\r
483 I_RCL,\r
484 I_RCPPS,\r
485 I_RCPSS,\r
486 I_RCR,\r
487 I_RDMSR,\r
488 I_RDPMC,\r
489 I_RDSHR,\r
490 I_RDTSC,\r
491 I_RESB,\r
492 I_RESD,\r
493 I_RESQ,\r
494 I_REST,\r
495 I_RESW,\r
496 I_RET,\r
497 I_RETF,\r
498 I_RETN,\r
499 I_ROL,\r
500 I_ROR,\r
501 I_RSDC,\r
502 I_RSLDT,\r
503 I_RSM,\r
504 I_RSQRTPS,\r
505 I_RSQRTSS,\r
506 I_RSTS,\r
507 I_SAHF,\r
508 I_SAL,\r
509 I_SALC,\r
510 I_SAR,\r
511 I_SBB,\r
512 I_SCASB,\r
513 I_SCASD,\r
514 I_SCASW,\r
515 I_SFENCE,\r
516 I_SGDT,\r
517 I_SHL,\r
518 I_SHLD,\r
519 I_SHR,\r
520 I_SHRD,\r
521 I_SHUFPD,\r
522 I_SHUFPS,\r
523 I_SIDT,\r
524 I_SLDT,\r
525 I_SMI,\r
526 I_SMINT,\r
527 I_SMINTOLD,\r
528 I_SMSW,\r
529 I_SQRTPD,\r
530 I_SQRTPS,\r
531 I_SQRTSD,\r
532 I_SQRTSS,\r
533 I_STC,\r
534 I_STD,\r
535 I_STI,\r
536 I_STMXCSR,\r
537 I_STOSB,\r
538 I_STOSD,\r
539 I_STOSW,\r
540 I_STR,\r
541 I_SUB,\r
542 I_SUBPD,\r
543 I_SUBPS,\r
544 I_SUBSD,\r
545 I_SUBSS,\r
546 I_SVDC,\r
547 I_SVLDT,\r
548 I_SVTS,\r
549 I_SYSCALL,\r
550 I_SYSENTER,\r
551 I_SYSEXIT,\r
552 I_SYSRET,\r
553 I_TEST,\r
554 I_UCOMISD,\r
555 I_UCOMISS,\r
556 I_UD0,\r
557 I_UD1,\r
558 I_UD2,\r
559 I_UMOV,\r
560 I_UNPCKHPD,\r
561 I_UNPCKHPS,\r
562 I_UNPCKLPD,\r
563 I_UNPCKLPS,\r
564 I_VERR,\r
565 I_VERW,\r
566 I_WAIT,\r
567 I_WBINVD,\r
568 I_WRMSR,\r
569 I_WRSHR,\r
570 I_XADD,\r
571 I_XBTS,\r
572 I_XCHG,\r
573 I_XLAT,\r
574 I_XLATB,\r
575 I_XOR,\r
576 I_XORPD,\r
577 I_XORPS,\r
578 I_XSTORE,\r
579 I_CMOVcc,\r
580 I_Jcc,\r
581 I_SETcc\r
582};\r
583\r
584#define MAX_INSLEN 11\r
585\r
586/* max length of any instruction, register name etc. */\r
587#if MAX_INSLEN > 9 /* MAX_INSLEN defined in insnsi.h */\r
588#define MAX_KEYWORD MAX_INSLEN\r
589#else\r
590#define MAX_KEYWORD 9\r
591#endif\r
592\r
593struct itemplate {\r
594 int opcode; /* the token, passed from "parser.c" */\r
595 int operands; /* number of operands */\r
596 long opd[3]; /* bit flags for operand types */\r
597 const char *code; /* the code it assembles to */\r
598 unsigned long flags; /* some flags */\r
599};\r
600\r
601/*\r
602 * this define is used to signify the end of an itemplate\r
603 */\r
604#define ITEMPLATE_END {-1,-1,{-1,-1,-1},NULL,0}\r
605\r
606/*\r
607 * Instruction template flags. These specify which processor\r
608 * targets the instruction is eligible for, whether it is\r
609 * privileged or undocumented, and also specify extra error\r
610 * checking on the matching of the instruction.\r
611 *\r
612 * IF_SM stands for Size Match: any operand whose size is not\r
613 * explicitly specified by the template is `really' intended to be\r
614 * the same size as the first size-specified operand.\r
615 * Non-specification is tolerated in the input instruction, but\r
616 * _wrong_ specification is not.\r
617 *\r
618 * IF_SM2 invokes Size Match on only the first _two_ operands, for\r
619 * three-operand instructions such as SHLD: it implies that the\r
620 * first two operands must match in size, but that the third is\r
621 * required to be _unspecified_.\r
622 *\r
623 * IF_SB invokes Size Byte: operands with unspecified size in the\r
624 * template are really bytes, and so no non-byte specification in\r
625 * the input instruction will be tolerated. IF_SW similarly invokes\r
626 * Size Word, and IF_SD invokes Size Doubleword.\r
627 *\r
628 * (The default state if neither IF_SM nor IF_SM2 is specified is\r
629 * that any operand with unspecified size in the template is\r
630 * required to have unspecified size in the instruction too...)\r
631 */\r
632\r
633#define IF_SM 0x00000001UL /* size match */\r
634#define IF_SM2 0x00000002UL /* size match first two operands */\r
635#define IF_SB 0x00000004UL /* unsized operands can't be non-byte */\r
636#define IF_SW 0x00000008UL /* unsized operands can't be non-word */\r
637#define IF_SD 0x00000010UL /* unsized operands can't be nondword */\r
638#define IF_AR0 0x00000020UL /* SB, SW, SD applies to argument 0 */\r
639#define IF_AR1 0x00000040UL /* SB, SW, SD applies to argument 1 */\r
640#define IF_AR2 0x00000060UL /* SB, SW, SD applies to argument 2 */\r
641#define IF_ARMASK 0x00000060UL /* mask for unsized argument spec */\r
642#define IF_PRIV 0x00000100UL /* it's a privileged instruction */\r
643#define IF_SMM 0x00000200UL /* it's only valid in SMM */\r
644#define IF_PROT 0x00000400UL /* it's protected mode only */\r
645#define IF_UNDOC 0x00001000UL /* it's an undocumented instruction */\r
646#define IF_FPU 0x00002000UL /* it's an FPU instruction */\r
647#define IF_MMX 0x00004000UL /* it's an MMX instruction */\r
648#define IF_3DNOW 0x00008000UL /* it's a 3DNow! instruction */\r
649#define IF_SSE 0x00010000UL /* it's a SSE (KNI, MMX2) instruction */\r
650#define IF_SSE2 0x00020000UL /* it's a SSE2 instruction */\r
651#define IF_SSE3 0x00040000UL /* it's a SSE3 (PNI) instruction */\r
652#define IF_PMASK 0xFF000000UL /* the mask for processor types */\r
653#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */\r
654 /* also the highest possible processor */\r
655#define IF_PFMASK 0xF001FF00UL /* the mask for disassembly "prefer" */\r
656#define IF_8086 0x00000000UL /* 8086 instruction */\r
657#define IF_186 0x01000000UL /* 186+ instruction */\r
658#define IF_286 0x02000000UL /* 286+ instruction */\r
659#define IF_386 0x03000000UL /* 386+ instruction */\r
660#define IF_486 0x04000000UL /* 486+ instruction */\r
661#define IF_PENT 0x05000000UL /* Pentium instruction */\r
662#define IF_P6 0x06000000UL /* P6 instruction */\r
663#define IF_KATMAI 0x07000000UL /* Katmai instructions */\r
664#define IF_WILLAMETTE 0x08000000UL /* Willamette instructions */\r
665#define IF_PRESCOTT 0x09000000UL /* Prescott instructions */\r
666#define IF_IA64 0x0F000000UL /* IA64 instructions */\r
667#define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */\r
668#define IF_AMD 0x20000000UL /* AMD-specific instruction */\r
669\r
670#endif\r
Magically enhanced SIMH