First Commit of my working state

[simh.git] / AltairZ80 / s100_ss1.c

/*************************************************************************\r
 *                                                                       *\r
 * $Id: s100_ss1.c 1773 2008-01-11 05:46:19Z hharte $                    *\r
 *                                                                       *\r
 * Copyright (c) 2007-2008 Howard M. Harte.                              *\r
 * http://www.hartetec.com                                               *\r
 *                                                                       *\r
 * Permission is hereby granted, free of charge, to any person obtaining *\r
 * a copy of this software and associated documentation files (the       *\r
 * "Software"), to deal in the Software without restriction, including   *\r
 * without limitation the rights to use, copy, modify, merge, publish,   *\r
 * distribute, sublicense, and/or sell copies of the Software, and to    *\r
 * permit persons to whom the Software is furnished to do so, subject to *\r
 * the following conditions:                                             *\r
 *                                                                       *\r
 * The above copyright notice and this permission notice shall be        *\r
 * included in all copies or substantial portions of the Software.       *\r
 *                                                                       *\r
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,       *\r
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF    *\r
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND                 *\r
 * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY  *\r
 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,  *\r
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE     *\r
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                *\r
 *                                                                       *\r
 * Except as contained in this notice, the name of Howard M. Harte shall *\r
 * not be used in advertising or otherwise to promote the sale, use or   *\r
 * other dealings in this Software without prior written authorization   *\r
 * Howard M. Harte.                                                      *\r
 *                                                                       *\r
 * SIMH Interface based on altairz80_hdsk.c, by Peter Schorn.            *\r
 *                                                                       *\r
 * Module Description:                                                   *\r
 *     CompuPro System Support 1 module for SIMH.                        *\r
 * Note this does not include the Boot ROM on the System Support 1 Card  *\r
 *                                                                       *\r
 * Environment:                                                          *\r
 *     User mode only                                                    *\r
 *                                                                       *\r
 *************************************************************************/\r
\r
/*#define DBG_MSG */\r
\r
#include "altairz80_defs.h"\r
\r
#if defined (_WIN32)\r
#include <windows.h>\r
#endif\r
\r
#ifdef DBG_MSG\r
#define DBG_PRINT(args) printf args\r
#else\r
#define DBG_PRINT(args)\r
#endif\r
\r
#define TRACE_MSG   0x01\r
#define DMA_MSG     0x02\r
\r
#define SS1_MAX_DRIVES    1\r
\r
#define UNIT_V_SS1_VERBOSE     (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages   */\r
#define UNIT_SS1_VERBOSE       (1 << UNIT_V_SS1_VERBOSE)\r
\r
typedef struct {\r
    PNP_INFO    pnp;    /* Plug and Play */\r
} SS1_INFO;\r
\r
static SS1_INFO ss1_info_data = { { 0x0, 0, 0x50, 12 } };\r
/* static SS1_INFO *ss1_info = &ss1_info_data;*/\r
\r
extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);\r
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);\r
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,\r
        int32 (*routine)(const int32, const int32, const int32), uint8 unmap);\r
extern uint32 PCX;\r
extern REG *sim_PC;\r
\r
/* These are needed for DMA.  PIO Mode has not been implemented yet. */\r
extern void PutBYTEWrapper(const uint32 Addr, const uint32 Value);\r
extern uint8 GetBYTEWrapper(const uint32 Addr);\r
\r
static t_stat ss1_reset(DEVICE *ss1_dev);\r
static uint8 SS1_Read(const uint32 Addr);\r
static uint8 SS1_Write(const uint32 Addr, uint8 cData);\r
\r
\r
static int32 ss1dev(const int32 port, const int32 io, const int32 data);\r
\r
static int32 trace_level    = 0x00;     /* Disable all tracing by default */\r
\r
static UNIT ss1_unit[] = {\r
    { UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }\r
};\r
\r
static REG ss1_reg[] = {\r
    { HRDATA (TRACELEVEL,   trace_level,           16), },\r
    { NULL }\r
};\r
\r
static MTAB ss1_mod[] = {\r
    { MTAB_XTD|MTAB_VDV,    0,              "IOBASE",   "IOBASE",   &set_iobase, &show_iobase, NULL },\r
    /* quiet, no warning messages       */\r
    { UNIT_SS1_VERBOSE, 0,                  "QUIET",    "QUIET",    NULL },\r
    /* verbose, show warning messages   */\r
    { UNIT_SS1_VERBOSE, UNIT_SS1_VERBOSE,   "VERBOSE",  "VERBOSE",  NULL },\r
    { 0 }\r
};\r
\r
DEVICE ss1_dev = {\r
    "SS1", ss1_unit, ss1_reg, ss1_mod,\r
    SS1_MAX_DRIVES, 10, 31, 1, SS1_MAX_DRIVES, SS1_MAX_DRIVES,\r
    NULL, NULL, &ss1_reset,\r
    NULL, NULL, NULL,\r
    &ss1_info_data, (DEV_DISABLE | DEV_DIS), 0,\r
    NULL, NULL, NULL\r
};\r
\r
/* Reset routine */\r
static t_stat ss1_reset(DEVICE *dptr)\r
{\r
    PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;\r
\r
    if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */\r
        sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, TRUE);\r
    } else {\r
        /* Connect SS1 at base address */\r
        if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, FALSE) != 0) {\r
            printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);\r
            return SCPE_ARG;\r
        }\r
    }\r
    return SCPE_OK;\r
}\r
\r
static int32 ss1dev(const int32 port, const int32 io, const int32 data)\r
{\r
    DBG_PRINT(("SS1: IO %s, Port %02x\n", io ? "WR" : "RD", port));\r
    if(io) {\r
        SS1_Write(port, data);\r
        return 0;\r
    } else {\r
        return(SS1_Read(port));\r
    }\r
}\r
\r
#define SS1_M8259_L     0x00\r
#define SS1_M8259_H     0x01\r
#define SS1_S8259_L     0x02\r
#define SS1_S8259_H     0x03\r
#define SS1_8253_TC0    0x04\r
#define SS1_8253_TC1    0x05\r
#define SS1_8253_TC2    0x06\r
#define SS1_8253_CTL    0x07\r
#define SS1_9511A_DATA  0x08\r
#define SS1_9511A_CMD   0x09\r
#define SS1_RTC_CMD     0x0A\r
#define SS1_RTC_DATA    0x0B\r
#define SS1_UART_DATA   0x0C\r
#define SS1_UART_STAT   0x0D\r
#define SS1_UART_MODE   0x0E\r
#define SS1_UART_CMD    0x0F\r
\r
extern int32 sio0d(const int32 port, const int32 io, const int32 data);\r
extern int32 sio0s(const int32 port, const int32 io, const int32 data);\r
\r
static uint8 SS1_Read(const uint32 Addr)\r
{\r
    uint8 cData = 0x00;\r
\r
    switch(Addr & 0x0F) {\r
        case SS1_M8259_L:\r
        case SS1_M8259_H:\r
        case SS1_S8259_L:\r
        case SS1_S8259_H:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Interrupt Controller not Implemented." NLP, PCX));\r
            break;\r
        case SS1_8253_TC0:\r
        case SS1_8253_TC1:\r
        case SS1_8253_TC2:\r
        case SS1_8253_CTL:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Timer not Implemented." NLP, PCX));\r
            break;\r
        case SS1_9511A_DATA:\r
        case SS1_9511A_CMD:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Math Coprocessor not Implemented." NLP, PCX));\r
            break;\r
        case SS1_RTC_CMD:\r
        case SS1_RTC_DATA:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: RTC not Implemented." NLP, PCX));\r
            break;\r
        case SS1_UART_DATA:\r
            cData = sio0d(Addr, 0, 0);\r
            break;\r
        case SS1_UART_STAT:\r
            cData = sio0s(Addr, 0, 0);\r
            break;\r
        case SS1_UART_MODE:\r
        case SS1_UART_CMD:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: UART not Implemented." NLP, PCX));\r
            break;\r
    }\r
\r
    return (cData);\r
\r
}\r
\r
static uint8 SS1_Write(const uint32 Addr, uint8 cData)\r
{\r
\r
    switch(Addr & 0x0F) {\r
        case SS1_M8259_L:\r
        case SS1_M8259_H:\r
        case SS1_S8259_L:\r
        case SS1_S8259_H:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Interrupt Controller not Implemented." NLP, PCX));\r
            break;\r
        case SS1_8253_TC0:\r
        case SS1_8253_TC1:\r
        case SS1_8253_TC2:\r
        case SS1_8253_CTL:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Timer not Implemented." NLP, PCX));\r
            break;\r
        case SS1_9511A_DATA:\r
        case SS1_9511A_CMD:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Math Coprocessor not Implemented." NLP, PCX));\r
            break;\r
        case SS1_RTC_CMD:\r
        case SS1_RTC_DATA:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: RTC not Implemented." NLP, PCX));\r
            break;\r
        case SS1_UART_DATA:\r
            sio0d(Addr, 1, cData);\r
            break;\r
        case SS1_UART_STAT:\r
            sio0s(Addr, 1, cData);\r
            break;\r
        case SS1_UART_MODE:\r
        case SS1_UART_CMD:\r
            TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: UART not Implemented." NLP, PCX));\r
            break;\r
    }\r
\r
    return(0);\r
}\r
\r