First Commit of my working state

[simh.git] / GRI / gri_stddev.c

/* gri_stddev.c: GRI-909 standard devices\r
\r
   Copyright (c) 2001-2008, Robert M Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   tti          S42-001 terminal input\r
   tto          S42-002 terminal output\r
   hsr          S42-004 high speed reader\r
   hsp          S42-006 high speed punch\r
   rtc          real time clock\r
\r
   31-May-08    RMS     Fixed declarations (found by Peter Schorn)\r
   30-Sep-06    RMS     Fixed handling of non-printable characters in KSR mode\r
   22-Nov-05    RMS     Revised for new terminal processing routines\r
   29-Dec-03    RMS     Added support for console backpressure\r
   25-Apr-03    RMS     Revised for extended file support\r
   22-Dec-02    RMS     Added break support\r
   01-Nov-02    RMS     Added 7b/8B support to terminal\r
*/\r
\r
#include "gri_defs.h"\r
#include <ctype.h>\r
\r
uint32 hsr_stopioe = 1, hsp_stopioe = 1;\r
\r
extern uint16 M[];\r
extern uint32 dev_done, ISR;\r
\r
t_stat tti_svc (UNIT *uhsr);\r
t_stat tto_svc (UNIT *uhsr);\r
t_stat tti_reset (DEVICE *dhsr);\r
t_stat tto_reset (DEVICE *dhsr);\r
t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat hsr_svc (UNIT *uhsr);\r
t_stat hsp_svc (UNIT *uhsr);\r
t_stat hsr_reset (DEVICE *dhsr);\r
t_stat hsp_reset (DEVICE *dhsr);\r
t_stat rtc_svc (UNIT *uhsr);\r
t_stat rtc_reset (DEVICE *dhsr);\r
int32 rtc_tps = 1000;\r
\r
/* TTI data structures\r
\r
   tti_dev      TTI device descriptor\r
   tti_unit     TTI unit descriptor\r
   tti_reg      TTI register list\r
   tti_mod      TTI modifiers list\r
*/\r
\r
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_KSR, 0), KBD_POLL_WAIT };\r
\r
REG tti_reg[] = {\r
    { ORDATA (BUF, tti_unit.buf, 8) },\r
    { FLDATA (IRDY, dev_done, INT_V_TTI) },\r
    { FLDATA (IENB, ISR, INT_V_TTI) },\r
    { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },\r
    { DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },\r
    { NULL }\r
    };\r
\r
MTAB tti_mod[] = {\r
    { TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },\r
    { TT_MODE, TT_MODE_7B,  "7b",  "7B",  &tty_set_mode },\r
    { TT_MODE, TT_MODE_8B,  "8b",  "8B",  &tty_set_mode },\r
    { TT_MODE, TT_MODE_7P,  "7b",  NULL,  NULL },\r
    { 0 }\r
    };\r
\r
DEVICE tti_dev = {\r
    "TTI", &tti_unit, tti_reg, tti_mod,\r
    1, 10, 31, 1, 8, 8,\r
    NULL, NULL, &tti_reset,\r
    NULL, NULL, NULL\r
    };\r
\r
/* TTO data structures\r
\r
   tto_dev      TTO device descriptor\r
   tto_unit     TTO unit descriptor\r
   tto_reg      TTO register list\r
*/\r
\r
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_KSR, 0), SERIAL_OUT_WAIT };\r
\r
REG tto_reg[] = {\r
    { ORDATA (BUF, tto_unit.buf, 8) },\r
    { FLDATA (ORDY, dev_done, INT_V_TTO) },\r
    { FLDATA (IENB, ISR, INT_V_TTO) },\r
    { DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },\r
    { DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },\r
    { NULL }\r
    };\r
\r
MTAB tto_mod[] = {\r
    { TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },\r
    { TT_MODE, TT_MODE_7B,  "7b",  "7B",  &tty_set_mode },\r
    { TT_MODE, TT_MODE_8B,  "8b",  "8B",  &tty_set_mode },\r
    { TT_MODE, TT_MODE_7P,  "7p",  "7P",  &tty_set_mode },\r
    { 0 }\r
    };\r
\r
DEVICE tto_dev = {\r
    "TTO", &tto_unit, tto_reg, tto_mod,\r
    1, 10, 31, 1, 8, 8,\r
    NULL, NULL, &tto_reset, \r
    NULL, NULL, NULL\r
    };\r
\r
/* HSR data structures\r
\r
   hsr_dev      HSR device descriptor\r
   hsr_unit     HSR unit descriptor\r
   hsr_reg      HSR register list\r
   hsr_mod      HSR modifiers list\r
*/\r
\r
UNIT hsr_unit = {\r
    UDATA (&hsr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), SERIAL_IN_WAIT\r
    };\r
\r
REG hsr_reg[] = {\r
    { ORDATA (BUF, hsr_unit.buf, 8) },\r
    { FLDATA (IRDY, dev_done, INT_V_HSR) },\r
    { FLDATA (IENB, ISR, INT_V_HSR) },\r
    { DRDATA (POS, hsr_unit.pos, T_ADDR_W), PV_LEFT },\r
    { DRDATA (TIME, hsr_unit.wait, 24), REG_NZ + PV_LEFT },\r
    { FLDATA (STOP_IOE, hsr_stopioe, 0) },\r
    { NULL }\r
    };\r
\r
DEVICE hsr_dev = {\r
    "HSR", &hsr_unit, hsr_reg, NULL,\r
    1, 10, 31, 1, 8, 8,\r
    NULL, NULL, &hsr_reset,\r
    NULL, NULL, NULL\r
    };\r
\r
/* HSP data structures\r
\r
   hsp_dev      HSP device descriptor\r
   hsp_unit     HSP unit descriptor\r
   hsp_reg      HSP register list\r
*/\r
\r
UNIT hsp_unit = {\r
    UDATA (&hsp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT\r
    };\r
\r
REG hsp_reg[] = {\r
    { ORDATA (BUF, hsp_unit.buf, 8) },\r
    { FLDATA (ORDY, dev_done, INT_V_HSP) },\r
    { FLDATA (IENB, ISR, INT_V_HSP) },\r
    { DRDATA (POS, hsp_unit.pos, T_ADDR_W), PV_LEFT },\r
    { DRDATA (TIME, hsp_unit.wait, 24), PV_LEFT },\r
    { FLDATA (STOP_IOE, hsp_stopioe, 0) },\r
    { NULL }\r
    };\r
\r
DEVICE hsp_dev = {\r
    "HSP", &hsp_unit, hsp_reg, NULL,\r
    1, 10, 31, 1, 8, 8,\r
    NULL, NULL, &hsp_reset,\r
    NULL, NULL, NULL\r
    };\r
\r
/* RTC data structures\r
\r
   rtc_dev      RTC device descriptor\r
   rtc_unit     RTC unit descriptor\r
   rtc_reg      RTC register list\r
*/\r
\r
UNIT rtc_unit = { UDATA (&rtc_svc, 0, 0), 16000 };\r
\r
REG rtc_reg[] = {\r
    { FLDATA (RDY, dev_done, INT_V_RTC) },\r
    { FLDATA (IENB, ISR, INT_V_RTC) },\r
    { DRDATA (TIME, rtc_unit.wait, 24), REG_NZ + PV_LEFT },\r
    { DRDATA (TPS, rtc_tps, 8), REG_NZ + PV_LEFT + REG_HIDDEN },\r
    { NULL }\r
    };\r
\r
DEVICE rtc_dev = {\r
    "RTC", &rtc_unit, rtc_reg, NULL,\r
    1, 0, 0, 0, 0, 0,\r
    NULL, NULL, &rtc_reset,\r
    NULL, NULL, NULL\r
    };\r
\r
/* Console terminal function processors */\r
\r
uint32 tty_rd (int32 src, int32 ea)\r
{\r
return tti_unit.buf;                                    /* return data */\r
}\r
\r
t_stat tty_wr (uint32 dst, uint32 val)\r
{\r
tto_unit.buf = val & 0377;                              /* save char */\r
dev_done = dev_done & ~INT_TTO;                         /* clear ready */\r
sim_activate (&tto_unit, tto_unit.wait);                /* activate unit */\r
return SCPE_OK;\r
}\r
\r
t_stat tty_fo (uint32 op)\r
{\r
if (op & TTY_IRDY) dev_done = dev_done & ~INT_TTI;\r
if (op & TTY_ORDY) dev_done = dev_done & ~INT_TTO;\r
return SCPE_OK;\r
}\r
\r
uint32 tty_sf (uint32 op)\r
{\r
if (((op & TTY_IRDY) && (dev_done & INT_TTI)) ||\r
    ((op & TTY_ORDY) && (dev_done & INT_TTO))) return 1;\r
return 0;\r
}\r
\r
/* Service routines */\r
\r
t_stat tti_svc (UNIT *uptr)\r
{\r
int32 c;\r
\r
sim_activate (uptr, uptr->wait);                        /* continue poll */\r
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c;       /* no char or error? */\r
if (c & SCPE_BREAK) uptr->buf = 0;                      /* break? */\r
else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags) | TTUF_KSR);\r
dev_done = dev_done | INT_TTI;                          /* set ready */\r
uptr->pos = uptr->pos + 1;\r
return SCPE_OK;\r
}\r
\r
t_stat tto_svc (UNIT *uptr)\r
{\r
int32 c;\r
t_stat r;\r
\r
c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags) | TTUF_KSR);\r
if (c >= 0) {\r
    if ((r = sim_putchar_s (c)) != SCPE_OK) {           /* output; error? */\r
        sim_activate (uptr, uptr->wait);                /* try again */\r
        return ((r == SCPE_STALL)? SCPE_OK: r);         /* !stall? report */\r
        }\r
    }\r
dev_done = dev_done | INT_TTO;                          /* set ready */\r
uptr->pos = uptr->pos + 1;\r
return SCPE_OK;\r
}\r
\r
/* Reset routines */\r
\r
t_stat tti_reset (DEVICE *dptr)\r
{\r
tti_unit.buf = 0;                                       /* clear buffer */\r
dev_done = dev_done & ~INT_TTI;                         /* clear ready */\r
sim_activate (&tti_unit, tti_unit.wait);                /* activate unit */\r
return SCPE_OK;\r
}\r
\r
t_stat tto_reset (DEVICE *dptr)\r
{\r
tto_unit.buf = 0;                                       /* clear buffer */\r
dev_done = dev_done | INT_TTO;                          /* set ready */\r
sim_cancel (&tto_unit);                                 /* deactivate unit */\r
return SCPE_OK;\r
}\r
\r
t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
tti_unit.flags = (tti_unit.flags & ~TT_MODE) | val;\r
tto_unit.flags = (tto_unit.flags & ~TT_MODE) | val;\r
return SCPE_OK;\r
}\r
\r
/* High speed paper tape function processors */\r
\r
uint32 hsrp_rd (int32 src, int32 ea)\r
{\r
return hsr_unit.buf;                                    /* return data */\r
}\r
\r
t_stat hsrp_wr (uint32 dst, uint32 val)\r
{\r
hsp_unit.buf = val & 0377;                              /* save char */\r
dev_done = dev_done & ~INT_HSP;                         /* clear ready */\r
sim_activate (&hsp_unit, hsp_unit.wait);                /* activate unit */\r
return SCPE_OK;\r
}\r
\r
t_stat hsrp_fo (uint32 op)\r
{\r
if (op & PT_IRDY) dev_done = dev_done & ~INT_HSR;\r
if (op & PT_ORDY) dev_done = dev_done & ~INT_HSP;\r
if (op & PT_STRT) sim_activate (&hsr_unit, hsr_unit.wait);\r
return SCPE_OK;\r
}\r
\r
uint32 hsrp_sf (uint32 op)\r
{\r
if (((op & PT_IRDY) && (dev_done & INT_HSR)) ||\r
    ((op & PT_ORDY) && (dev_done & INT_HSP))) return 1;\r
return 0;\r
}\r
\r
t_stat hsr_svc (UNIT *uptr)\r
{\r
int32 temp;\r
\r
if ((hsr_unit.flags & UNIT_ATT) == 0)                   /* attached? */\r
    return IORETURN (hsr_stopioe, SCPE_UNATT);\r
if ((temp = getc (hsr_unit.fileref)) == EOF) {          /* read char */\r
    if (feof (hsr_unit.fileref)) {                      /* err or eof? */\r
        if (hsr_stopioe) printf ("HSR end of file\n");\r
        else return SCPE_OK;\r
        }\r
    else perror ("HSR I/O error");\r
    clearerr (hsr_unit.fileref);\r
    return SCPE_IOERR;\r
    }\r
dev_done = dev_done | INT_HSR;                          /* set ready */\r
hsr_unit.buf = temp & 0377;                             /* save char */\r
hsr_unit.pos = hsr_unit.pos + 1;\r
return SCPE_OK;\r
}\r
\r
t_stat hsp_svc (UNIT *uptr)\r
{\r
dev_done = dev_done | INT_HSP;                          /* set ready */\r
if ((hsp_unit.flags & UNIT_ATT) == 0)                   /* attached? */\r
    return IORETURN (hsp_stopioe, SCPE_UNATT);\r
if (putc (hsp_unit.buf, hsp_unit.fileref) == EOF) {     /* write char */\r
    perror ("HSP I/O error");                           /* error? */\r
    clearerr (hsp_unit.fileref);\r
    return SCPE_IOERR;\r
    }\r
hsp_unit.pos = hsp_unit.pos + 1;\r
return SCPE_OK;\r
}\r
\r
/* Reset routines */\r
\r
t_stat hsr_reset (DEVICE *dptr)\r
{\r
hsr_unit.buf = 0;                                       /* clear buffer */\r
dev_done = dev_done & ~INT_HSR;                         /* clear ready */\r
sim_cancel (&hsr_unit);                                 /* deactivate unit */\r
return SCPE_OK;\r
}\r
\r
t_stat hsp_reset (DEVICE *dptr)\r
{\r
hsp_unit.buf = 0;                                       /* clear buffer */\r
dev_done = dev_done | INT_HSP;                          /* set ready */\r
sim_cancel (&hsp_unit);                                 /* deactivate unit */\r
return SCPE_OK;\r
}\r
\r
/* Clock function processors */\r
\r
t_stat rtc_fo (int32 op)\r
{\r
if (op & RTC_OFF) sim_cancel (&rtc_unit);               /* clock off? */\r
if ((op & RTC_ON) && !sim_is_active (&rtc_unit))        /* clock on? */\r
    sim_activate (&rtc_unit, sim_rtc_init (rtc_unit.wait));\r
if (op & RTC_OV) dev_done = dev_done & ~INT_RTC;        /* clr ovflo? */\r
return SCPE_OK;\r
}\r
\r
uint32 rtc_sf (int32 op)\r
{\r
if ((op & RTC_OV) && (dev_done & INT_RTC)) return 1;\r
return 0;\r
}\r
\r
t_stat rtc_svc (UNIT *uptr)\r
{\r
M[RTC_CTR] = (M[RTC_CTR] + 1) & DMASK;                  /* incr counter */\r
if (M[RTC_CTR] == 0) dev_done = dev_done | INT_RTC;     /* ovflo? set ready */\r
sim_activate (&rtc_unit, sim_rtc_calb (rtc_tps));       /* reactivate */\r
return SCPE_OK;\r
}\r
\r
t_stat rtc_reset (DEVICE *dptr)\r
{\r
dev_done = dev_done & ~INT_RTC;                         /* clear ready */\r
sim_cancel (&rtc_unit);                                 /* stop clock */\r
return SCPE_OK;\r
}\r