First Commit of my working state

[simh.git] / H316 / h316_fhd.c

/* h316_fhd.c: H316/516 fixed head simulator\r
\r
   Copyright (c) 2003-2006, Robert M. Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   fhd          516-4400 fixed head disk\r
\r
   15-May-06    RMS     Fixed bug in autosize attach (reported by David Gesswein)\r
   04-Jan-04    RMS     Changed sim_fsize calling sequence\r
\r
   These head-per-track devices are buffered in memory, to minimize overhead.\r
*/\r
\r
#include "h316_defs.h"\r
#include <math.h>\r
\r
/* Constants */\r
\r
#define FH_NUMWD        1536                            /* words/track */\r
#define FH_NUMTK        64                              /* tracks/surface */\r
#define FH_WDPSF        (FH_NUMWD * FH_NUMTK)           /* words/surface */             \r
#define FH_NUMSF        16                              /* surfaces/ctlr */\r
#define UNIT_V_AUTO     (UNIT_V_UF + 0)                 /* autosize */\r
#define UNIT_V_SF       (UNIT_V_UF + 1)                 /* #surfaces - 1 */\r
#define UNIT_M_SF       017\r
#define UNIT_AUTO       (1 << UNIT_V_AUTO)\r
#define UNIT_SF         (UNIT_M_SF << UNIT_V_SF)\r
#define UNIT_GETSF(x)   ((((x) >> UNIT_V_SF) & UNIT_M_SF) + 1)\r
\r
/* Command word 1 */\r
\r
#define CW1_RW          0100000                         /* read vs write */\r
#define CW1_V_SF        10                              /* surface */\r
#define CW1_M_SF        017\r
#define CW1_GETSF(x)    (((x) >> CW1_V_SF) & CW1_M_SF)\r
#define CW1_V_TK        4                               /* track */\r
#define CW1_M_TK        077\r
#define CW1_GETTK(x)    (((x) >> CW1_V_TK) & CW1_M_TK)\r
\r
/* Command word 2 */\r
\r
#define CW2_V_CA        0                               /* character addr */\r
#define CW2_M_CA        07777\r
#define CW2_GETCA(x)    (((x) >> CW2_V_CA) & CW2_M_CA)\r
\r
#define GET_POS(x)      ((int) fmod (sim_gtime() / ((double) (x)), \\r
                        ((double) FH_NUMWD)))\r
\r
/* OTA states */\r
\r
#define OTA_NOP         0                               /* normal */\r
#define OTA_CW1         1                               /* expecting CW1 */\r
#define OTA_CW2         2                               /* expecting CW2 */\r
\r
extern int32 dev_int, dev_enb, chan_req;\r
extern int32 stop_inst;\r
extern uint32 dma_ad[DMA_MAX];\r
\r
uint32 fhd_cw1 = 0;                                     /* cmd word 1 */\r
uint32 fhd_cw2 = 0;                                     /* cmd word 2 */\r
uint32 fhd_buf = 0;                                     /* buffer */\r
uint32 fhd_otas = 0;                                    /* state */\r
uint32 fhd_busy = 0;                                    /* busy */\r
uint32 fhd_rdy = 0;                                     /* word ready */\r
uint32 fhd_dte = 0;                                     /* data err */\r
uint32 fhd_ace = 0;                                     /* access error */\r
uint32 fhd_dma = 0;                                     /* DMA/DMC */\r
uint32 fhd_eor = 0;                                     /* end of range */\r
uint32 fhd_csum = 0;                                    /* parity checksum */\r
uint32 fhd_stopioe = 1;                                 /* stop on error */\r
int32 fhd_time = 10;                                    /* time per word */\r
\r
int32 fhdio (int32 inst, int32 fnc, int32 dat, int32 dev);\r
t_stat fhd_svc (UNIT *uptr);\r
t_stat fhd_reset (DEVICE *dptr);\r
t_stat fhd_attach (UNIT *uptr, char *cptr);\r
t_stat fhd_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);\r
void fhd_go (uint32 dma);\r
void fhd_go1 (uint32 dat);\r
void fhd_go2 (uint32 dat);\r
t_bool fhd_getc (UNIT *uptr, uint32 *ch);\r
t_bool fhd_putc (UNIT *uptr, uint32 ch);\r
t_bool fhd_bad_wa (uint32 wa);\r
uint32 fhd_csword (uint32 cs, uint32 ch);\r
\r
/* FHD data structures\r
\r
   fhd_dev      device descriptor\r
   fhd_unit     unit descriptor\r
   fhd_mod      unit modifiers\r
   fhd_reg      register list\r
*/\r
\r
DIB fhd_dib = { FHD, IOBUS, 1, &fhdio };\r
\r
UNIT fhd_unit = { \r
    UDATA (&fhd_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,\r
           FH_WDPSF)\r
    };\r
\r
REG fhd_reg[] = {\r
    { ORDATA (CW1, fhd_cw1, 16) },\r
    { ORDATA (CW2, fhd_cw2, 16) },\r
    { ORDATA (BUF, fhd_buf, 16) },\r
    { FLDATA (BUSY, fhd_busy, 0) },\r
    { FLDATA (RDY, fhd_rdy, 0) },\r
    { FLDATA (DTE, fhd_dte, 0) },\r
    { FLDATA (ACE, fhd_ace, 0) },\r
    { FLDATA (EOR, fhd_eor, 0) },\r
    { FLDATA (DMA, fhd_dma, 0) },\r
    { FLDATA (CSUM, fhd_csum, 7) },\r
    { FLDATA (INTREQ, dev_int, INT_V_MT) },\r
    { FLDATA (ENABLE, dev_enb, INT_V_MT) },\r
    { DRDATA (TIME, fhd_time, 31), REG_NZ + PV_LEFT },\r
    { ORDATA (OTAS, fhd_otas, 2), REG_HRO },\r
    { ORDATA (CHAN, fhd_dib.chan, 5), REG_HRO },\r
    { FLDATA (STOP_IOE, fhd_stopioe, 0) },\r
    { NULL }\r
    };\r
\r
MTAB fhd_mod[] = {\r
    { UNIT_SF, (0 << UNIT_V_SF), NULL, "1S", &fhd_set_size },\r
    { UNIT_SF, (1 << UNIT_V_SF), NULL, "2S", &fhd_set_size },\r
    { UNIT_SF, (2 << UNIT_V_SF), NULL, "3S", &fhd_set_size },\r
    { UNIT_SF, (3 << UNIT_V_SF), NULL, "4S", &fhd_set_size },\r
    { UNIT_SF, (4 << UNIT_V_SF), NULL, "5S", &fhd_set_size },\r
    { UNIT_SF, (5 << UNIT_V_SF), NULL, "6S", &fhd_set_size },\r
    { UNIT_SF, (6 << UNIT_V_SF), NULL, "7S", &fhd_set_size },\r
    { UNIT_SF, (7 << UNIT_V_SF), NULL, "8S", &fhd_set_size },\r
    { UNIT_SF, (8 << UNIT_V_SF), NULL, "9S", &fhd_set_size },\r
    { UNIT_SF, (9 << UNIT_V_SF), NULL, "10S", &fhd_set_size },\r
    { UNIT_SF, (10 << UNIT_V_SF), NULL, "11S", &fhd_set_size },\r
    { UNIT_SF, (11 << UNIT_V_SF), NULL, "12S", &fhd_set_size },\r
    { UNIT_SF, (12 << UNIT_V_SF), NULL, "13S", &fhd_set_size },\r
    { UNIT_SF, (13 << UNIT_V_SF), NULL, "14S", &fhd_set_size },\r
    { UNIT_SF, (14 << UNIT_V_SF), NULL, "15S", &fhd_set_size },\r
    { UNIT_SF, (15 << UNIT_V_SF), NULL, "16S", &fhd_set_size },\r
    { UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, NULL, "IOBUS",\r
      &io_set_iobus, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, NULL, "DMC",\r
      &io_set_dmc, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, NULL, "DMA",\r
      &io_set_dma, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "CHANNEL", NULL,\r
      NULL, &io_show_chan, NULL },\r
    { 0 }\r
    };\r
\r
DEVICE fhd_dev = {\r
    "FHD", &fhd_unit, fhd_reg, fhd_mod,\r
    1, 8, 22, 1, 8, 16,\r
    NULL, NULL, &fhd_reset,\r
    NULL, &fhd_attach, NULL,\r
    &fhd_dib, DEV_DISABLE\r
    };\r
\r
/* IO routines */\r
\r
int32 fhdio (int32 inst, int32 fnc, int32 dat, int32 dev)\r
{\r
switch (inst) {                                         /* case on opcode */\r
\r
    case ioOCP:                                         /* control */\r
        if (fnc == 04) {                                /* terminate output? */\r
            fhd_eor = 1;                                /* stop */\r
            CLR_INT (INT_FHD);                          /* clear int req */\r
            }\r
        else if (fnc == 003) fhd_go (1);                /* start, DMA */\r
        else if (fnc == 007) fhd_go (0);                /* start, IO bus */\r
        else return IOBADFNC (dat);\r
        break;\r
\r
    case ioOTA:                                         /* output */\r
        if (fnc) return IOBADFNC (dat);                 /* only fnc 0 */\r
        if (fhd_rdy) {                                  /* ready? */\r
            fhd_buf = dat;                              /* store data */\r
            if (fhd_otas == OTA_CW1) fhd_go1 (dat);     /* expecting CW1? */\r
            else if (fhd_otas == OTA_CW2) fhd_go2 (dat);/* expecting CW2? */\r
            else fhd_rdy = 0;                           /* normal, clr ready */\r
            return IOSKIP (dat);\r
            }\r
        break;\r
\r
    case ioINA:                                         /* input */\r
        if (fnc) return IOBADFNC (dat);                 /* only fnc 0 */\r
        if (fhd_rdy) {                                  /* ready? */\r
            fhd_rdy = 0;                                /* clear ready */\r
            return IOSKIP (dat | fhd_buf);              /* return data */\r
            }\r
        break;\r
\r
    case ioSKS:                                         /* sense */\r
        if (((fnc == 000) && fhd_rdy) ||                /* 0 = skip if ready */\r
            ((fnc == 001) && !fhd_busy) ||              /* 1 = skip if !busy */\r
            ((fnc == 002) && !fhd_dte) ||               /* 2 = skip if !data err */\r
            ((fnc == 003) && !fhd_ace) ||               /* 3 = skip if !access err */\r
            ((fnc == 004) && !TST_INTREQ (INT_FHD)))    /* 4 = skip if !interrupt */\r
            return IOSKIP (dat);\r
            break;\r
\r
    case ioEND:\r
        fhd_eor = 1;\r
        break;\r
        }\r
\r
return dat;\r
}\r
\r
/* Start new operation */\r
\r
void fhd_go (uint32 dma)\r
{\r
int32 ch = fhd_dib.chan - 1;                            /* DMA/DMC chan */\r
\r
if (fhd_busy) return;                                   /* ignore if busy */\r
fhd_busy = 1;                                           /* ctlr is busy */\r
fhd_eor = 0;                                            /* transfer not done */\r
fhd_csum = 0;                                           /* init checksum */\r
fhd_dte = 0;                                            /* clear errors */\r
fhd_ace = 0;\r
if (ch >= 0) fhd_dma = dma;                             /* DMA allowed? */\r
else fhd_dma = 0;                                       /* no, force IO bus */\r
fhd_otas = OTA_CW1;                                     /* expect CW1 */\r
fhd_rdy = 1;                                            /* set ready */\r
if (fhd_dma && Q_DMA (ch)) {                            /* DMA and DMA channel? */\r
    SET_CH_REQ (ch);                                    /* set channel request */\r
    dma_ad[ch] = dma_ad[ch] & ~DMA_IN;                  /* force output */\r
    }\r
return;\r
}\r
\r
/* Process command word 1 */\r
\r
void fhd_go1 (uint32 dat)\r
{\r
int32 ch = fhd_dib.chan - 1;                            /* DMA/DMC chan */\r
\r
fhd_cw1 = dat;                                          /* store CW1 */\r
fhd_otas = OTA_CW2;                                     /* expect CW2 */\r
fhd_rdy = 1;                                            /* set ready */\r
if (fhd_dma && Q_DMA (ch)) SET_CH_REQ (ch);             /* DMA? set chan request */\r
return;\r
}\r
\r
/* Process command word 2 - initiate seek */\r
\r
void fhd_go2 (uint32 dat)\r
{\r
int32 ch = fhd_dib.chan - 1;                            /* DMA/DMC chan */\r
uint32 sf = CW1_GETSF (fhd_cw1);                        /* surface */\r
int32 t, wa;\r
\r
fhd_cw2 = dat;                                          /* store CW2 */\r
fhd_otas = OTA_NOP;                                     /* next state */\r
wa = CW2_GETCA (fhd_cw2) >> 1;                          /* word addr */\r
if ((wa >= FH_NUMWD) ||                                 /* if bad char addr */\r
    ((fhd_unit.flags & UNIT_ATT) == 0) ||               /* or unattached */\r
    (sf >= UNIT_GETSF (fhd_unit.flags))) {              /* or bad surface */\r
    fhd_ace = 1;                                        /* access error */\r
    fhd_busy = 0;                                       /* abort operation */\r
    SET_INT (INT_FHD);\r
    return;\r
    }\r
if (fhd_cw1 & CW1_RW) {                                 /* write? */\r
    fhd_rdy = 1;                                        /* set ready */\r
    if (fhd_dma) SET_CH_REQ (ch);                       /* if DMA/DMC, req chan */\r
    }\r
else {\r
    fhd_rdy = 0;                                        /* read, clear ready */\r
    if (fhd_dma && (ch < DMC_V_DMC1))                   /* read and DMA chan? */\r
        dma_ad[ch] = dma_ad[ch] | DMA_IN;               /* force input */\r
    }\r
t = wa - GET_POS (fhd_time);                            /* delta to new loc */\r
if (t < 0) t = t + FH_NUMWD;                            /* wrap around? */\r
sim_activate (&fhd_unit, t * fhd_time);                 /* schedule op */\r
return;\r
}\r
\r
/* Unit service */\r
\r
t_stat fhd_svc (UNIT *uptr)\r
{\r
int32 ch = fhd_dib.chan - 1;                            /* DMA/DMC chan (-1 if IO bus) */\r
uint32 c1, c2;\r
\r
if ((uptr->flags & UNIT_ATT) == 0) {                    /* unattached? */\r
    fhd_ace = 1;                                        /* access error */\r
    fhd_busy = 0;                                       /* abort operation */\r
    SET_INT (INT_FHD);\r
    return IORETURN (fhd_stopioe, SCPE_UNATT);\r
    }\r
\r
if (fhd_eor || fhd_rdy) {                               /* done or ready set? */\r
    if (fhd_rdy) fhd_dte = 1;                           /* if ready set, data err */\r
    if (fhd_cw1 & CW1_RW) {                             /* write? */\r
        if (!fhd_rdy) {                                 /* buffer full? */\r
            fhd_putc (uptr, fhd_buf >> 8);              /* store last word */\r
            fhd_putc (uptr, fhd_buf);\r
            }\r
        fhd_putc (uptr, fhd_csum);                      /* store csum */\r
        }\r
    else {                                              /* read */\r
        fhd_getc (uptr, &c1);                           /* get csum */\r
        if (fhd_csum) fhd_dte = 1;                      /* if csum != 0, err */\r
        }\r
    fhd_busy = 0;                                       /* operation complete */\r
    SET_INT (INT_FHD);\r
    return SCPE_OK;\r
    }\r
\r
if (fhd_cw1 & CW1_RW) {                                 /* write? */\r
    if (fhd_putc (uptr, fhd_buf >> 8)) return SCPE_OK;\r
    if (fhd_putc (uptr, fhd_buf)) return SCPE_OK;\r
    }\r
else {\r
    if (fhd_getc (uptr, &c1)) return SCPE_OK;           /* read */\r
    if (fhd_getc (uptr, &c2)) return SCPE_OK;\r
    fhd_buf = (c1 << 8) | c2;\r
    }\r
sim_activate (uptr, fhd_time);                          /* next word */\r
fhd_rdy = 1;                                            /* set ready */\r
if (fhd_dma) SET_CH_REQ (ch);                           /* if DMA/DMC, req chan */\r
return SCPE_OK;\r
}\r
\r
/* Read character from disk */\r
\r
t_bool fhd_getc (UNIT *uptr, uint32 *ch)\r
{\r
uint32 sf = CW1_GETSF (fhd_cw1);                        /* surface */\r
uint32 tk = CW1_GETTK (fhd_cw1);                        /* track */\r
uint32 ca = CW2_GETCA (fhd_cw2);                        /* char addr */\r
uint32 wa = ca >> 1;                                    /* word addr */\r
uint32 ba = (((sf * FH_NUMTK) + tk) * FH_NUMWD) + wa;   /* buffer offset */\r
uint16 *fbuf = uptr->filebuf;                           /* buffer base */\r
uint32 wd;\r
\r
if (fhd_bad_wa (wa)) return TRUE;                       /* addr bad? */\r
fhd_cw2 = fhd_cw2 + 1;                                  /* incr char addr */\r
if (ca & 1) wd = fbuf[ba] & 0377;                       /* select char */\r
else wd = (fbuf[ba] >> 8) & 0377;\r
fhd_csum = fhd_csword (fhd_csum, wd);                   /* put in csum */\r
*ch = wd;                                               /* return */\r
return FALSE;\r
}\r
\r
/* Write character to disk */\r
\r
t_bool fhd_putc (UNIT *uptr, uint32 ch)\r
{\r
uint32 sf = CW1_GETSF (fhd_cw1);                        /* surface */\r
uint32 tk = CW1_GETTK (fhd_cw1);                        /* track */\r
uint32 ca = CW2_GETCA (fhd_cw2);                        /* char addr */\r
uint32 wa = ca >> 1;                                    /* word addr */\r
uint32 ba = (((sf * FH_NUMTK) + tk) * FH_NUMWD) + wa;   /* buffer offset */\r
uint16 *fbuf = uptr->filebuf;                           /* buffer base */\r
\r
ch = ch & 0377;                                         /* mask char */\r
if (fhd_bad_wa (wa)) return TRUE;                       /* addr bad? */\r
fhd_cw2 = fhd_cw2 + 1;                                  /* incr char addr */\r
if (ca & 1) fbuf[ba] = (fbuf[ba] & ~0377) | ch;         /* odd? low char */\r
else fbuf[ba] = (fbuf[ba] & 0377) | (ch << 8);          /* even, hi char */\r
fhd_csum = fhd_csword (fhd_csum, ch);                   /* put in csum */\r
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;          /* update hwmark */\r
return FALSE;\r
}\r
\r
/* Check word address */\r
\r
t_bool fhd_bad_wa (uint32 wa)\r
{\r
if (wa >= FH_NUMWD) {                                   /* bad address? */\r
    fhd_ace = 1;                                        /* access error */\r
    fhd_busy = 0;                                       /* abort operation */\r
    SET_INT (INT_FHD);\r
    return TRUE;\r
    }\r
return FALSE;\r
}\r
\r
/* Add character to checksum (parity) */\r
\r
uint32 fhd_csword (uint32 cs, uint32 ch)\r
{\r
while (ch) {                                            /* count bits */\r
    ch = ch & ~(ch & (-(int32) ch));\r
    cs = cs ^ 0200;                                     /* invert cs for each 1 */\r
    }\r
return cs;\r
}\r
\r
/* Reset routine */\r
\r
t_stat fhd_reset (DEVICE *dptr)\r
{\r
fhd_busy = 0;                                           /* reset state */\r
fhd_rdy = 0;\r
fhd_ace = 0;\r
fhd_dte = 0;\r
fhd_eor = 0;\r
fhd_otas = OTA_NOP;\r
fhd_cw1 = fhd_cw2 = fhd_buf = 0;\r
CLR_INT (INT_FHD);                                      /* clear int, enb */\r
CLR_ENB (INT_FHD);\r
sim_cancel (&fhd_unit);                                 /* cancel operation */\r
return SCPE_OK;\r
}\r
\r
/* Attach routine */\r
\r
t_stat fhd_attach (UNIT *uptr, char *cptr)\r
{\r
uint32 sz, sf;\r
uint32 ds_bytes = FH_WDPSF * sizeof (int16);\r
\r
if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {\r
    sf = (sz + ds_bytes - 1) / ds_bytes;\r
    if (sf >= FH_NUMSF) sf = FH_NUMSF - 1;\r
    uptr->flags = (uptr->flags & ~UNIT_SF) |\r
        (sf << UNIT_V_SF);\r
    }\r
uptr->capac = UNIT_GETSF (uptr->flags) * FH_WDPSF;\r
return attach_unit (uptr, cptr);\r
}\r
\r
/* Set size routine */\r
\r
t_stat fhd_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (val < 0) return SCPE_IERR;\r
if (uptr->flags & UNIT_ATT) return SCPE_ALATT;\r
uptr->capac = UNIT_GETSF (val) * FH_WDPSF;\r
return SCPE_OK;\r
}\r