[simh.git] / HP2100 / hp2100_ipl.c

/* hp2100_ipl.c: HP 2000 interprocessor link simulator\r
\r
   Copyright (c) 2002-2007, Robert M Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   ipli, iplo   12875A interprocessor link\r
\r
   01-Mar-07    JDB     IPLI EDT delays DMA completion interrupt for TSB\r
                        Added debug printouts\r
   28-Dec-06    JDB     Added ioCRS state to I/O decoders\r
   16-Aug-05    RMS     Fixed C++ declaration and cast problems\r
   07-Oct-04    JDB     Fixed enable/disable from either device\r
   26-Apr-04    RMS     Fixed SFS x,C and SFC x,C\r
                        Implemented DMA SRQ (follows FLG)\r
   21-Dec-03    RMS     Adjusted ipl_ptime for TSB (from Mike Gemeny)\r
   09-May-03    RMS     Added network device flag\r
   31-Jan-03    RMS     Links are full duplex (found by Mike Gemeny)\r
\r
   The 12875A Processor Interconnect Kit consists four 12566A Microcircuit\r
   Interface cards.  Two are used in each processor.  One card in each system is\r
   used to initiate transmissions to the other, and the second card is used to\r
   receive transmissions from the other.  Each pair of cards forms a\r
   bidirectional link, as the sixteen data lines are cross-connected, so that\r
   data sent and status returned are supported.  In each processor, data is sent\r
   on the lower priority card and received on the higher priority card.  Two\r
   sets of cards are used to support simultaneous transmission in both\r
   directions.\r
\r
   Reference:\r
   - 12875A Processor Interconnect Kit Operating and Service Manual\r
            (12875-90002, Jan-1974)\r
*/\r
\r
#include "hp2100_defs.h"\r
#include "sim_sock.h"\r
#include "sim_tmxr.h"\r
\r
#define UNIT_V_DIAG     (UNIT_V_UF + 0)                 /* diagnostic mode */\r
#define UNIT_V_ACTV     (UNIT_V_UF + 1)                 /* making connection */\r
#define UNIT_V_ESTB     (UNIT_V_UF + 2)                 /* connection established */\r
#define UNIT_V_HOLD     (UNIT_V_UF + 3)                 /* character holding */\r
#define UNIT_DIAG       (1 << UNIT_V_DIAG)\r
#define UNIT_ACTV       (1 << UNIT_V_ACTV)\r
#define UNIT_ESTB       (1 << UNIT_V_ESTB)\r
#define UNIT_HOLD       (1 << UNIT_V_HOLD)\r
#define IBUF            buf                             /* input buffer */\r
#define OBUF            wait                            /* output buffer */\r
#define DSOCKET         u3                              /* data socket */\r
#define LSOCKET         u4                              /* listening socket */\r
\r
/* Debug flags */\r
\r
#define DEB_CMDS        (1 << 0)                        /* Command initiation and completion */\r
#define DEB_CPU         (1 << 1)                        /* CPU I/O */\r
#define DEB_XFER        (1 << 2)                        /* Socket receive and transmit */\r
\r
extern uint32 PC;\r
extern uint32 dev_cmd[2], dev_ctl[2], dev_flg[2], dev_fbf[2], dev_srq[2];\r
extern FILE *sim_log;\r
extern FILE *sim_deb;\r
int32 ipl_edtdelay = 1;                                 /* EDT delay (msec) */\r
int32 ipl_ptime = 31;                                   /* polling interval */\r
int32 ipl_stopioe = 0;                                  /* stop on error */\r
int32 ipl_hold[2] = { 0 };                              /* holding character */\r
\r
DEVICE ipli_dev, iplo_dev;\r
int32 ipliio (int32 inst, int32 IR, int32 dat);\r
int32 iploio (int32 inst, int32 IR, int32 dat);\r
int32 iplio (UNIT *uptr, int32 inst, int32 IR, int32 dat);\r
t_stat ipl_svc (UNIT *uptr);\r
t_stat ipl_reset (DEVICE *dptr);\r
t_stat ipl_attach (UNIT *uptr, char *cptr);\r
t_stat ipl_detach (UNIT *uptr);\r
t_stat ipl_boot (int32 unitno, DEVICE *dptr);\r
t_stat ipl_dscln (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat ipl_setdiag (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_bool ipl_check_conn (UNIT *uptr);\r
\r
/* Debug flags table */\r
\r
DEBTAB ipl_deb[] = {\r
    { "CMDS", DEB_CMDS },\r
    { "CPU",  DEB_CPU },\r
    { "XFER", DEB_XFER },\r
    { NULL, 0 }  };\r
\r
/* IPLI data structures\r
\r
   ipli_dev     IPLI device descriptor\r
   ipli_unit    IPLI unit descriptor\r
   ipli_reg     IPLI register list\r
*/\r
\r
DIB ipl_dib[] = {\r
    { IPLI, 0, 0, 0, 0, 0, &ipliio },\r
    { IPLO, 0, 0, 0, 0, 0, &iploio }\r
    };\r
\r
#define ipli_dib ipl_dib[0]\r
#define iplo_dib ipl_dib[1]\r
\r
UNIT ipl_unit[] = {\r
    { UDATA (&ipl_svc, UNIT_ATTABLE, 0) },\r
    { UDATA (&ipl_svc, UNIT_ATTABLE, 0) }\r
    };\r
\r
#define ipli_unit ipl_unit[0]\r
#define iplo_unit ipl_unit[1]\r
\r
REG ipli_reg[] = {\r
    { ORDATA (IBUF, ipli_unit.IBUF, 16) },\r
    { ORDATA (OBUF, ipli_unit.OBUF, 16) },\r
    { FLDATA (CMD, ipli_dib.cmd, 0) },\r
    { FLDATA (CTL, ipli_dib.ctl, 0) },\r
    { FLDATA (FLG, ipli_dib.flg, 0) },\r
    { FLDATA (FBF, ipli_dib.fbf, 0) },\r
    { FLDATA (SRQ, ipli_dib.srq, 0) },\r
    { ORDATA (HOLD, ipl_hold[0], 8) },\r
    { DRDATA (TIME, ipl_ptime, 24), PV_LEFT },\r
    { FLDATA (STOP_IOE, ipl_stopioe, 0) },\r
    { ORDATA (DEVNO, ipli_dib.devno, 6), REG_HRO },\r
    { NULL }\r
    };\r
\r
MTAB ipl_mod[] = {\r
    { UNIT_DIAG, UNIT_DIAG, "diagnostic mode", "DIAG", &ipl_setdiag },\r
    { UNIT_DIAG, 0, "link mode", "LINK", &ipl_setdiag },\r
    { MTAB_XTD | MTAB_VDV, 0, NULL, "DISCONNECT",\r
      &ipl_dscln, NULL, NULL },\r
    { MTAB_XTD | MTAB_VDV, 1, "DEVNO", "DEVNO",\r
      &hp_setdev, &hp_showdev, &ipli_dev },\r
    { 0 }\r
    };\r
\r
DEVICE ipli_dev = {\r
    "IPLI", &ipli_unit, ipli_reg, ipl_mod,\r
    1, 10, 31, 1, 16, 16,\r
    &tmxr_ex, &tmxr_dep, &ipl_reset,\r
    &ipl_boot, &ipl_attach, &ipl_detach,\r
    &ipli_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG,\r
    0, ipl_deb, NULL, NULL\r
    };\r
\r
/* IPLO data structures\r
\r
   iplo_dev     IPLO device descriptor\r
   iplo_unit    IPLO unit descriptor\r
   iplo_reg     IPLO register list\r
*/\r
\r
REG iplo_reg[] = {\r
    { ORDATA (IBUF, iplo_unit.IBUF, 16) },\r
    { ORDATA (OBUF, iplo_unit.OBUF, 16) },\r
    { FLDATA (CMD, iplo_dib.cmd, 0) },\r
    { FLDATA (CTL, iplo_dib.ctl, 0) },\r
    { FLDATA (FLG, iplo_dib.flg, 0) },\r
    { FLDATA (FBF, iplo_dib.fbf, 0) },\r
    { FLDATA (SRQ, iplo_dib.srq, 0) },\r
    { ORDATA (HOLD, ipl_hold[1], 8) },\r
    { DRDATA (TIME, ipl_ptime, 24), PV_LEFT },\r
    { ORDATA (DEVNO, iplo_dib.devno, 6), REG_HRO },\r
    { NULL }\r
    };\r
\r
DEVICE iplo_dev = {\r
    "IPLO", &iplo_unit, iplo_reg, ipl_mod,\r
    1, 10, 31, 1, 16, 16,\r
    &tmxr_ex, &tmxr_dep, &ipl_reset,\r
    &ipl_boot, &ipl_attach, &ipl_detach,\r
    &iplo_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG,\r
    0, ipl_deb, NULL, NULL\r
    };\r
\r
/* I/O instructions */\r
\r
int32 ipliio (int32 inst, int32 IR, int32 dat)\r
{\r
return iplio (&ipli_unit, inst, IR, dat);\r
}\r
\r
int32 iploio (int32 inst, int32 IR, int32 dat)\r
{\r
return iplio (&iplo_unit, inst, IR, dat);\r
}\r
\r
/* I/O handler for the IPLI and IPLO devices.\r
\r
   Implementation note: 2000 Access has a race condition that manifests itself\r
   by an apparently normal boot and operational system console but no PLEASE LOG\r
   IN response to terminals connected to the multiplexer.  The frequency of\r
   occurrence is higher on multiprocessor host systems, where the SP and IOP\r
   instances may execute concurrently.\r
\r
   The cause is this code in the SP disc loader source (2883.asm, 7900.asm,\r
   790X.asm, 79X3.asm, and 79XX.asm):\r
\r
         LDA SDVTR     REQUEST\r
         JSB IOPMA,I     DEVICE TABLE\r
         [...]\r
         STC DMAHS,C   TURN ON DMA\r
         SFS DMAHS     WAIT FOR\r
         JMP *-1         DEVICE TABLE\r
         STC CH2,C     SET CORRECT\r
         CLC CH2         FLAG DIRECTION\r
\r
   The STC/CLC normally would cause a second "request device table" command to\r
   be recognized by the IOP, except that the IOP DMA setup routine "DMAXF" (in\r
   D61.asm) has specified an end-of-block CLC that holds off the IPL interrupt,\r
   and the completion interrupt routine "DMACP" ends with a STC,C that clears\r
   the IPL flag.\r
\r
   In hardware, the two CPUs are essentially interlocked by the DMA transfer,\r
   and DMA completion interrupts occur almost simultaneously.  Therefore, the\r
   STC/CLC in the SP is guaranteed to occur before the STC,C in the IOP.  Under\r
   simulation, and especially on multiprocessor hosts, that guarantee does not\r
   hold.  If the STC/CLC occurs after the STC,C, then the IOP starts a second\r
   device table DMA transfer, which the SP is not expecting.  The IOP never\r
   processes the subsequent "start timesharing" command, and the muxtiplexer is\r
   non-reponsive.\r
\r
   We employ a workaround that decreases the incidence of the problem: DMA\r
   output completion interrupts are delayed to allow the other SIMH instance a\r
   chance to process its own DMA completion.  We do this by processing the EDT\r
   (End Data Transfer) I/O backplane signal and "sleep"ing for a short time if\r
   the transfer was an output transfer ("dat" contains the DMA channel number\r
   and direction flag for EDT signals).\r
*/\r
\r
int32 iplio (UNIT *uptr, int32 inst, int32 IR, int32 dat)\r
{\r
uint32 u, dev, odev;\r
int32 sta;\r
char msg[2], uc;\r
DEVICE *dbdev;                                          /* device ptr for debug */\r
static const char *iotype[] = { "Status", "Command" };\r
\r
uc = (uptr == &ipli_unit) ? 'I' : 'O';                  /* identify unit for debug */\r
dbdev = (uptr == &ipli_unit) ? &ipli_dev : &iplo_dev;   /* identify device for debug */\r
\r
u = (uptr - ipl_unit);                                  /* get unit number */\r
dev = IR & I_DEVMASK;                                   /* get device no */\r
switch (inst) {                                         /* case on opcode */\r
\r
    case ioFLG:                                         /* flag clear/set */\r
        if ((IR & I_HC) == 0) { setFSR (dev); }         /* STF */\r
        break;\r
\r
    case ioSFC:                                         /* skip flag clear */\r
        if (FLG (dev) == 0) PC = (PC + 1) & VAMASK;\r
        break;\r
\r
    case ioSFS:                                         /* skip flag set */\r
        if (FLG (dev) != 0) PC = (PC + 1) & VAMASK;\r
        break;\r
\r
    case ioOTX:                                         /* output */\r
        uptr->OBUF = dat;\r
\r
        if (DEBUG_PRJ (dbdev, DEB_CPU))\r
            fprintf (sim_deb, ">>IPL%c OTx: %s = %06o\n", uc, iotype[u], dat);\r
        break;\r
\r
    case ioLIX:                                         /* load */\r
        dat = 0;\r
\r
    case ioMIX:                                         /* merge */\r
        dat = dat | uptr->IBUF;                         /* get return data */\r
\r
        if (DEBUG_PRJ (dbdev, DEB_CPU))\r
            fprintf (sim_deb, ">>IPL%c LIx: %s = %06o\n", uc, iotype[u ^ 1], dat);\r
        break;\r
\r
    case ioCRS:                                         /* control reset */\r
        clrCMD (dev);                                   /* clear ctl, cmd */\r
        clrCTL (dev);\r
        break;\r
\r
    case ioCTL:                                         /* control clear/set */\r
        if (IR & I_CTL) {                               /* CLC */\r
            clrCMD (dev);                               /* clear ctl, cmd */\r
            clrCTL (dev);\r
\r
            if (DEBUG_PRJ (dbdev, DEB_CMDS))\r
                fprintf (sim_deb, ">>IPL%c CLC: Command cleared\n", uc);\r
            }\r
\r
        else {                                          /* STC */\r
            setCMD (dev);                               /* set ctl, cmd */\r
            setCTL (dev);\r
\r
            if (DEBUG_PRJ (dbdev, DEB_CMDS))\r
                fprintf (sim_deb, ">>IPL%c STC: Command set\n", uc);\r
\r
            if (uptr->flags & UNIT_ATT) {               /* attached? */\r
                if ((uptr->flags & UNIT_ESTB) == 0) {   /* established? */\r
                    if (!ipl_check_conn (uptr))         /* not established? */\r
                        return STOP_NOCONN;             /* lose */\r
                    uptr->flags = uptr->flags | UNIT_ESTB;\r
                    }\r
                msg[0] = (uptr->OBUF >> 8) & 0377;\r
                msg[1] = uptr->OBUF & 0377;\r
                sta = sim_write_sock (uptr->DSOCKET, msg, 2);\r
\r
                if (DEBUG_PRJ (dbdev, DEB_XFER))\r
                    fprintf (sim_deb,\r
                        ">>IPL%c STC: Socket write = %06o, status = %d\n",\r
                        uc, uptr->OBUF, sta);\r
\r
                if (sta == SOCKET_ERROR) {\r
                    printf ("IPL: socket write error\n");\r
                    return SCPE_IOERR;\r
                    }\r
                sim_os_sleep (0);\r
                }\r
            else if (uptr->flags & UNIT_DIAG) {         /* diagnostic mode? */\r
                u = (uptr - ipl_unit) ^ 1;              /* find other device */\r
                ipl_unit[u].IBUF = uptr->OBUF;          /* output to other */\r
                odev = ipl_dib[u].devno;                /* other device no */\r
                setFSR (odev);                          /* set other flag */\r
                }\r
            else return SCPE_UNATT;                     /* lose */\r
            }\r
        break;\r
\r
    case ioEDT:                                         /* End of DMA data transfer */\r
        if ((dat & DMA2_OI) == 0) {                     /* output transfer? */\r
            if (DEBUG_PRJ (dbdev, DEB_CMDS))\r
                fprintf (sim_deb,\r
                    ">>IPL%c EDT: Delaying DMA completion interrupt for %d msec\n",\r
                    uc, ipl_edtdelay);\r
            sim_os_ms_sleep (ipl_edtdelay);             /* delay completion */\r
            }\r
        break;\r
\r
    default:\r
        break;\r
        }\r
\r
if (IR & I_HC) { clrFSR (dev); }                        /* H/C option */\r
return dat;\r
}\r
\r
/* Unit service - poll for input */\r
\r
t_stat ipl_svc (UNIT *uptr)\r
{\r
int32 u, nb, dev;\r
char msg[2], uc;\r
DEVICE *dbdev;                                          /* device ptr for debug */\r
\r
u = uptr - ipl_unit;                                    /* get link number */\r
if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK;      /* not attached? */\r
sim_activate (uptr, ipl_ptime);                         /* reactivate */\r
if ((uptr->flags & UNIT_ESTB) == 0) {                   /* not established? */\r
    if (!ipl_check_conn (uptr)) return SCPE_OK;         /* check for conn */\r
    uptr->flags = uptr->flags | UNIT_ESTB;\r
    }\r
nb = sim_read_sock (uptr->DSOCKET, msg, ((uptr->flags & UNIT_HOLD)? 1: 2));\r
if (nb < 0) {                                           /* connection closed? */\r
    printf ("IPL: socket read error\n");\r
    return SCPE_IOERR;\r
    }\r
if (nb == 0) return SCPE_OK;                            /* no data? */\r
if (uptr->flags & UNIT_HOLD) {                          /* holdover byte? */\r
    uptr->IBUF = (ipl_hold[u] << 8) | (((int32) msg[0]) & 0377);\r
    uptr->flags = uptr->flags & ~UNIT_HOLD;\r
    }\r
else if (nb == 1) {\r
    ipl_hold[u] = ((int32) msg[0]) & 0377;\r
    uptr->flags = uptr->flags | UNIT_HOLD;\r
    }\r
else uptr->IBUF = ((((int32) msg[0]) & 0377) << 8) |\r
    (((int32) msg[1]) & 0377);\r
dev = ipl_dib[u].devno;                                 /* get device number */\r
clrCMD (dev);                                           /* clr cmd, set flag */\r
setFSR (dev);\r
\r
uc = (uptr == &ipli_unit) ? 'I' : 'O';                  /* identify unit for debug */\r
dbdev = (uptr == &ipli_unit) ? &ipli_dev : &iplo_dev;   /* identify device for debug */\r
\r
if (DEBUG_PRJ (dbdev, DEB_XFER))\r
    fprintf (sim_deb, ">>IPL%c svc: Socket read = %06o, status = %d\n",\r
        uc, uptr->IBUF, nb);\r
\r
return SCPE_OK;\r
}\r
\r
t_bool ipl_check_conn (UNIT *uptr)\r
{\r
SOCKET sock;\r
\r
if (uptr->flags & UNIT_ESTB) return TRUE;               /* established? */\r
if (uptr->flags & UNIT_ACTV) {                          /* active connect? */\r
    if (sim_check_conn (uptr->DSOCKET, 0) <= 0) return FALSE;\r
    }\r
else {\r
    sock = sim_accept_conn (uptr->LSOCKET, NULL);       /* poll connect */\r
    if (sock == INVALID_SOCKET) return FALSE;           /* got a live one? */\r
    uptr->DSOCKET = sock;                               /* save data socket */\r
    }\r
uptr->flags = uptr->flags | UNIT_ESTB;                  /* conn established */\r
return TRUE;\r
}\r
\r
/* Reset routine */\r
\r
t_stat ipl_reset (DEVICE *dptr)\r
{\r
DIB *dibp = (DIB *) dptr->ctxt;\r
UNIT *uptr = dptr->units;\r
\r
hp_enbdis_pair (dptr,                                   /* make pair cons */\r
    (dptr == &ipli_dev)? &iplo_dev: &ipli_dev);\r
dibp->cmd = dibp->ctl = 0;                              /* clear cmd, ctl */\r
dibp->flg = dibp->fbf = dibp->srq = 1;                  /* set flg, fbf, srq */\r
uptr->IBUF = uptr->OBUF = 0;                            /* clr buffers */\r
if (uptr->flags & UNIT_ATT) sim_activate (uptr, ipl_ptime);\r
else sim_cancel (uptr);                                 /* deactivate unit */\r
uptr->flags = uptr->flags & ~UNIT_HOLD;\r
return SCPE_OK;\r
}\r
\r
/* Attach routine\r
\r
   attach -l - listen for connection on port\r
   attach -c - connect to ip address and port\r
*/\r
\r
t_stat ipl_attach (UNIT *uptr, char *cptr)\r
{\r
extern int32 sim_switches;\r
SOCKET newsock;\r
uint32 i, t, ipa, ipp, oldf;\r
char *tptr;\r
t_stat r;\r
\r
r = get_ipaddr (cptr, &ipa, &ipp);\r
if ((r != SCPE_OK) || (ipp == 0)) return SCPE_ARG;\r
oldf = uptr->flags;\r
if (oldf & UNIT_ATT) ipl_detach (uptr);\r
if ((sim_switches & SWMASK ('C')) ||\r
    ((sim_switches & SIM_SW_REST) && (oldf & UNIT_ACTV))) {\r
        if (ipa == 0) ipa = 0x7F000001;\r
        newsock = sim_connect_sock (ipa, ipp);\r
        if (newsock == INVALID_SOCKET) return SCPE_IOERR;\r
        printf ("Connecting to IP address %d.%d.%d.%d, port %d\n",\r
            (ipa >> 24) & 0xff, (ipa >> 16) & 0xff,\r
            (ipa >> 8) & 0xff, ipa & 0xff, ipp);\r
        if (sim_log) fprintf (sim_log,\r
            "Connecting to IP address %d.%d.%d.%d, port %d\n",\r
            (ipa >> 24) & 0xff, (ipa >> 16) & 0xff,\r
            (ipa >> 8) & 0xff, ipa & 0xff, ipp);\r
        uptr->flags = uptr->flags | UNIT_ACTV;\r
        uptr->LSOCKET = 0;\r
        uptr->DSOCKET = newsock;\r
        }\r
else {\r
    if (ipa != 0) return SCPE_ARG;\r
    newsock = sim_master_sock (ipp);\r
    if (newsock == INVALID_SOCKET) return SCPE_IOERR;\r
    printf ("Listening on port %d\n", ipp);\r
    if (sim_log) fprintf (sim_log, "Listening on port %d\n", ipp);\r
    uptr->flags = uptr->flags & ~UNIT_ACTV;\r
    uptr->LSOCKET = newsock;\r
    uptr->DSOCKET = 0;\r
    }\r
uptr->IBUF = uptr->OBUF = 0;\r
uptr->flags = (uptr->flags | UNIT_ATT) & ~(UNIT_ESTB | UNIT_HOLD);\r
tptr = (char *) malloc (strlen (cptr) + 1);             /* get string buf */\r
if (tptr == NULL) {                                     /* no memory? */\r
    ipl_detach (uptr);                                  /* close sockets */\r
    return SCPE_MEM;\r
    }\r
strcpy (tptr, cptr);                                    /* copy ipaddr:port */\r
uptr->filename = tptr;                                  /* save */\r
sim_activate (uptr, ipl_ptime);                         /* activate poll */\r
if (sim_switches & SWMASK ('W')) {                      /* wait? */\r
    for (i = 0; i < 30; i++) {                          /* check for 30 sec */\r
        if (t = ipl_check_conn (uptr)) break;           /* established? */\r
        if ((i % 10) == 0)                              /* status every 10 sec */\r
            printf ("Waiting for connnection\n");\r
        sim_os_sleep (1);                               /* sleep 1 sec */\r
        }\r
    if (t) printf ("Connection established\n");\r
    }\r
return SCPE_OK;\r
}\r
\r
/* Detach routine */\r
\r
t_stat ipl_detach (UNIT *uptr)\r
{\r
if (!(uptr->flags & UNIT_ATT)) return SCPE_OK;          /* attached? */\r
if (uptr->flags & UNIT_ACTV) sim_close_sock (uptr->DSOCKET, 1);\r
else {\r
    if (uptr->flags & UNIT_ESTB)                        /* if established, */\r
        sim_close_sock (uptr->DSOCKET, 0);              /* close data socket */\r
    sim_close_sock (uptr->LSOCKET, 1);                  /* closen listen socket */\r
    }\r
free (uptr->filename);                                  /* free string */\r
uptr->filename = NULL;\r
uptr->LSOCKET = 0;\r
uptr->DSOCKET = 0;\r
uptr->flags = uptr->flags & ~(UNIT_ATT | UNIT_ACTV | UNIT_ESTB);\r
sim_cancel (uptr);                                      /* don't poll */\r
return SCPE_OK;\r
}\r
\r
/* Disconnect routine */\r
\r
t_stat ipl_dscln (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (cptr) return SCPE_ARG;\r
if (((uptr->flags & UNIT_ATT) == 0) || (uptr->flags & UNIT_ACTV) ||\r
    ((uptr->flags & UNIT_ESTB) == 0)) return SCPE_NOFNC;\r
sim_close_sock (uptr->DSOCKET, 0);\r
uptr->DSOCKET = 0;\r
uptr->flags = uptr->flags & ~UNIT_ESTB;\r
return SCPE_OK;\r
}\r
\r
/* Diagnostic/normal mode routine */\r
\r
t_stat ipl_setdiag (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (val) {\r
    ipli_unit.flags = ipli_unit.flags | UNIT_DIAG;\r
    iplo_unit.flags = iplo_unit.flags | UNIT_DIAG;\r
    }\r
else {\r
    ipli_unit.flags = ipli_unit.flags & ~UNIT_DIAG;\r
    iplo_unit.flags = iplo_unit.flags & ~UNIT_DIAG;\r
    }\r
return SCPE_OK;\r
}\r
\r
/* Interprocessor link bootstrap routine (HP Access Manual) */\r
\r
#define MAX_BASE        073\r
#define IPL_PNTR        074\r
#define PTR_PNTR        075\r
#define IPL_DEVA        076\r
#define PTR_DEVA        077\r
\r
static const uint32 pboot[IBL_LNT] = {\r
    0163774,                    /*BBL LDA ICK,I         ; IPL sel code */\r
    0027751,                    /*    JMP CFG           ; go configure */\r
    0107700,                    /*ST  CLC 0,C           ; intr off */\r
    0002702,                    /*    CLA,CCE,SZA       ; skip in */\r
    0063772,                    /*CN  LDA M26           ; feed frame */\r
    0002307,                    /*EOC CCE,INA,SZA,RSS   ; end of file? */\r
    0027760,                    /*    JMP EOT           ; yes */\r
    0017736,                    /*    JSB READ          ; get #char */\r
    0007307,                    /*    CMB,CCE,INB,SZB,RSS ; 2's comp; null? */\r
    0027705,                    /*    JMP EOC           ; read next */\r
    0077770,                    /*    STB WC            ; word in rec */\r
    0017736,                    /*    JSB READ          ; get feed frame */\r
    0017736,                    /*    JSB READ          ; get address */\r
    0074000,                    /*    STB 0             ; init csum */\r
    0077771,                    /*    STB AD            ; save addr */\r
    0067771,                    /*CK  LDB AD            ; check addr */\r
    0047773,                    /*    ADB MAXAD         ; below loader */\r
    0002040,                    /*    SEZ               ; E =0 => OK */\r
    0102055,                    /*    HLT 55 */\r
    0017736,                    /*    JSB READ          ; get word */\r
    0040001,                    /*    ADA 1             ; cont checksum */\r
    0177771,                    /*    STB AD,I          ; store word */\r
    0037771,                    /*    ISZ AD */\r
    0000040,                    /*    CLE               ; force wd read */\r
    0037770,                    /*    ISZ WC            ; block done? */\r
    0027717,                    /*    JMP CK            ; no */\r
    0017736,                    /*    JSB READ          ; get checksum */\r
    0054000,                    /*    CPB 0             ; ok? */\r
    0027704,                    /*    JMP CN            ; next block */\r
    0102011,                    /*    HLT 11            ; bad csum */\r
    0000000,                    /*RD  0 */\r
    0006600,                    /*    CLB,CME           ; E reg byte ptr */\r
    0103700,                    /*IO1 STC RDR,C         ; start reader */\r
    0102300,                    /*IO2 SFS RDR           ; wait */\r
    0027741,                    /*    JMP *-1 */\r
    0106400,                    /*IO3 MIB RDR           ; get byte */\r
    0002041,                    /*    SEZ,RSS           ; E set? */\r
    0127736,                    /*    JMP RD,I          ; no, done */\r
    0005767,                    /*    BLF,CLE,BLF       ; shift byte */\r
    0027740,                    /*    JMP IO1           ; again */\r
    0163775,                    /*    LDA PTR,I         ; get ptr code */\r
    0043765,                    /*CFG ADA SFS           ; config IO */\r
    0073741,                    /*    STA IO2 */\r
    0043766,                    /*    ADA STC */\r
    0073740,                    /*    STA IO1 */\r
    0043767,                    /*    ADA MIB */\r
    0073743,                    /*    STA IO3 */\r
    0027702,                    /*    JMP ST */\r
    0063777,                    /*EOT LDA PSC           ; put select codes */\r
    0067776,                    /*    LDB ISC           ; where xloader wants */\r
    0102077,                    /*    HLT 77 */\r
    0027702,                    /*    JMP ST */\r
    0000000,                    /*    NOP */\r
    0102300,                    /*SFS SFS 0 */\r
    0001400,                    /*STC 1400 */\r
    0002500,                    /*MIB 2500 */\r
    0000000,                    /*WC  0 */\r
    0000000,                    /*AD  0 */\r
    0177746,                    /*M26 -26 */\r
    0000000,                    /*MAX -BBL */\r
    0007776,                    /*ICK ISC */\r
    0007777,                    /*PTR IPT */\r
    0000000,                    /*ISC 0 */\r
    0000000                     /*IPT 0 */\r
    };\r
\r
t_stat ipl_boot (int32 unitno, DEVICE *dptr)\r
{\r
int32 i, devi, devp;\r
extern DIB ptr_dib;\r
extern UNIT cpu_unit;\r
extern uint32 SR;\r
extern uint16 *M;\r
\r
devi = ipli_dib.devno;                                  /* get device no */\r
devp = ptr_dib.devno;\r
PC = ((MEMSIZE - 1) & ~IBL_MASK) & VAMASK;              /* start at mem top */\r
SR = (devi << IBL_V_DEV) | devp;                        /* set SR */\r
for (i = 0; i < IBL_LNT; i++) M[PC + i] = pboot[i];     /* copy bootstrap */\r
M[PC + MAX_BASE] = (~PC + 1) & DMASK;                   /* fix ups */\r
M[PC + IPL_PNTR] = M[PC + IPL_PNTR] | PC;\r
M[PC + PTR_PNTR] = M[PC + PTR_PNTR] | PC;\r
M[PC + IPL_DEVA] = devi;\r
M[PC + PTR_DEVA] = devp;\r
return SCPE_OK;\r
}\r