First Commit of my working state

[simh.git] / I7094 / i7094_bug_history.txt

Bugs Found and Fixed During Simulator Debug\r
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1. CPU: MPY tested sign of AC instead of sign of MQ.\r
2. CPU: VLM, VDP, VDH need alternate opcode decode points for large counts.\r
3. CPU: STL not in decode table.\r
4. CPU: Partial stores lacked initial read in decode table.\r
5. CPU: PXD, PCD needed (t_uint64) cast.\r
6. CPU: SXD, SCD needed (t_uint64) cast.\r
7. CPU: SBM at wrong case offset.\r
8. CPU: All transfers used IR<21:35> instead of calculated effective address.\r
9. CPU: HPR, TRA need alternate negative opcodes.\r
10. CPU: STT missing final write to memory.\r
11. IO: Channel output process model incorrect, extensive revision required.\r
12. IO: Channel connect test should not test channel state, only connection.\r
13. IO: Channel opcode with nostore doesn't increment channel address.\r
14. CDR: Card reader missing activate at end of state 2.\r
15. SYS: Zero operand instructions printed with trailing space.\r
16. CPU: Convert class count bit field start definition incorrect.\r
17. CPU: CAQ cut and paste error from CVR.\r
18. CPU: Shift count is 8b wide, not 9b.\r
19. SYS: Mnemonic is LDQ not LMQ.\r
20. SYS: RQL opcode incorrect in symbolic decode table.\r
21. CPU: Multi-tag mode stores OR'd value of tags on any index read except\r
    normal effective address.\r
22. CPU: Floating point trap does not write location 0 if trap suppressed.\r
23. SYS: TRA instructions should have symbolic class MXN not MXR.\r
24. CPU: Floating add instructions test for zero result only if normalization enabled.\r
25. CPU: Floating add with unlike signs and equal magnitudes, result sign is sign\r
    of SR rather than sign of AC.\r
26. CPU: Floating multiply does not test spill prior to normalization step.\r
27. CPU: Channel activity proceeds under HALT.\r
28. MT: Any read error should stop the channel and the tape controller.\r
29. MT: EOR write flag cleared before testing.\r
39. IO: EOR write flag set after data sent to device.\r
40. IO: EOR write flag incorrect set on IOCP, IOCT, IOSP, IOST.\r
41. MT: End of file errors not masked on backspace operations.\r
42. CPU: LCHx, RCHx miscoded in decode table.\r
43. IO: Only 7607 error completions (IOxT without new command) set trap.\r
44. CPU: 7067 channel trap flags misdefined with extraneous decrement shift.\r
45. CPU: pcq array misdeclared as uint32 instead of uint16.\r
46. IO: SDC and SCD tested chan_flags instead of chan_dev.flags.\r
47. SYS: 7907 opcodes defined incorrectly.\r
48. SYS: TCH not decoding bit<19>.\r
49. IO: CTL not clearing EOR after device end.\r
50. DSK: Format code not incrementing track in writing all tracks in cylinder.\r
51. DSK: THA mode overwrites record structure of first record.\r
52. DSK: Write doesn't set channel request for initial word.\r
53. DSK: Saved record number was command digits 3..8 instead of 5..10.\r
54. CLK: Compute 60th's from location 5, so Chrono clock is in sync with interval clock.\r
55. CPU: Enable Chronolog clock if CTSS.\r
56. CPU: Read/write protection error not setting protection trap.\r
57. CPU: SCHx not setting protection trap in user mode.\r
58: CPU: Protection trap overwriting wrong location.\r
59. CPU: Stop message reporting physical, not virtual, PC.\r
60. IO: Test for "request another cycle" in channel processor was inverted.\r
61. IO: Valid bit handling incorrect across multiple transfers.\r
62. IO: BSR doesn't set EOF indicator.\r
63. IO: 7607 channel modeled incorrectly, could stall.\r
64. IO: All 7607 "effective NOP" conditions must be tested when a new command is\r
    decoded (wc == 0 for IOCx and IOSx, EOR set for IOSx and IORx).\r
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