First Commit of my working state

[simh.git] / I7094 / i7094_clk.c

/* i7094_clk.c: IBM 7094 clock\r
\r
   Copyright (c) 2003-2006, Robert M. Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   clk          RPQ F89349 interval timer\r
                Chronolog calendar clock\r
*/\r
\r
#include "i7094_defs.h"\r
#include <time.h>\r
\r
uint32 chtr_clk = 0;\r
extern t_uint64 *M;\r
\r
t_stat clk_svc (UNIT *uptr);\r
t_stat clk_reset (DEVICE *dptr);\r
uint8 bcd_2d (uint32 n, uint8 *b2);\r
\r
/* CLK data structures\r
\r
   clk_dev      CLK device descriptor\r
   clk_unit     CLK unit\r
   clk_reg      CLK register list\r
*/\r
\r
UNIT clk_unit = { UDATA (&clk_svc, 0, 0), 16000 };\r
\r
REG clk_reg[] = {\r
    { FLDATA (TRAP, chtr_clk, 0) },\r
    { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },\r
    { NULL }\r
    };\r
\r
DEVICE clk_dev = {\r
    "CLK", &clk_unit, clk_reg, NULL,\r
    1, 0, 0, 0, 0, 0,\r
    NULL, NULL, &clk_reset,\r
    NULL, NULL, NULL,\r
    NULL, DEV_DISABLE+DEV_DIS\r
    };\r
\r
/* Clock unit service */\r
\r
t_stat clk_svc (UNIT *uptr)\r
{\r
t_uint64 ctr;\r
\r
if ((clk_dev.flags & DEV_DIS) == 0) {                   /* clock enabled? */\r
    ctr = ReadP (CLK_CTR);\r
    ctr = (ctr + 1) & DMASK;                            /* increment */\r
    WriteP (CLK_CTR, ctr);\r
    if ((ctr & MMASK) == 0) chtr_clk = 1;               /* overflow? req trap */\r
    sim_activate (uptr, sim_rtcn_calb (CLK_TPS, TMR_CLK)); /* reactivate unit */\r
    }\r
return SCPE_OK;\r
}\r
\r
/* Chronolog clock */\r
\r
uint32 chrono_rd (uint8 *buf, uint32 bufsiz)\r
{\r
time_t curtim;\r
t_uint64 ctr;\r
struct tm *tptr;\r
\r
if (bufsiz < 12) return 0;\r
curtim = time (NULL);                                   /* get time */\r
tptr = localtime (&curtim);                             /* decompose */\r
if (tptr == NULL) return 0;                             /* error? */\r
\r
buf[0] = bcd_2d (tptr->tm_mon + 1, buf + 1);\r
buf[2] = bcd_2d (tptr->tm_mday, buf + 3);\r
buf[4] = bcd_2d (tptr->tm_hour, buf + 5);\r
buf[6] = bcd_2d (tptr->tm_min, buf + 7);\r
buf[8] = bcd_2d (tptr->tm_sec, buf + 9);\r
ctr = ReadP (CLK_CTR);\r
buf[10] = bcd_2d ((uint32) (ctr % 60), buf + 11);\r
return 12;\r
}\r
\r
/* Convert number (0-99) to BCD */\r
\r
uint8 bcd_2d (uint32 n, uint8 *b2)\r
{\r
uint8 d1, d2;\r
\r
d1 = n / 10;\r
d2 = n % 10;\r
if (d1 == 0) d1 = BCD_ZERO;\r
if (d2 == 0) d2 = BCD_ZERO;\r
if (b2 != NULL) *b2 = d2;\r
return d1;\r
}\r
\r
/* Reset routine */\r
\r
t_stat clk_reset (DEVICE *dptr)\r
{\r
chtr_clk = 0;\r
if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit);\r
else sim_activate (&clk_unit, sim_rtcn_init (clk_unit.wait, TMR_CLK));\r
return SCPE_OK;\r
}\r