First Commit of my working state

[simh.git] / I7094 / i7094_drm.c

/* i7094_drm.c: 7289/7320A drum simulator\r
\r
   Copyright (c) 2005-2006, Robert M Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   drm          7289/7320A "fast" drum\r
\r
   Very little is known about this device; the behavior simulated here is\r
   what is used by CTSS.\r
\r
   - The drum channel/controller behaves like a hybrid of the 7607 and the 7909.\r
     It responds to SCD (like the 7909), gets its address from the channel\r
     program (like the 7909), but responds to IOCD/IOCP (like the 7607) and\r
     sets channel flags (like the 7607).\r
   - The drum channel supports at least 2 drums.  The maximum is 8 or less.\r
     Physical drums are numbered from 0.\r
   - Each drum has a capacity of 192K 36b words.  This is divided into 6\r
     "logical" drum of 32KW each.  Each "logical" drum has 16 2048W "sectors".\r
     Logical drums are numbered from 1.\r
   - The drum's behavior if a sector boundary is crossed in mid-transfer is\r
     unknown.  CTSS never does this.\r
   - The drum's behavior with record operations is unknown.  CTSS only uses\r
     IOCD and IOCP.\r
   - The drum's error indicators are unknown.  CTSS regards bits <0:2,13> of\r
     the returned SCD data as errors, as well as the normal 7607 trap flags.\r
   - The drum's rotational speed is unknown.\r
\r
   Assumptions in this simulator:\r
\r
   - Transfers may not cross a sector boundary.  An attempt to do so sets\r
     the EOF flag and causes an immediate disconnect.\r
   - The hardware never sets end of record.\r
\r
   For speed, the entire drum is buffered in memory.\r
*/\r
\r
#include "i7094_defs.h"\r
#include <math.h>\r
\r
#define DRM_NUMDR       8                               /* drums/controller */\r
\r
/* Drum geometry */\r
\r
#define DRM_NUMWDS      2048                            /* words/sector */\r
#define DRM_SCMASK      (DRM_NUMWDS - 1)                /* sector mask */\r
#define DRM_NUMSC       16                              /* sectors/log drum */\r
#define DRM_NUMWDL      (DRM_NUMWDS * DRM_NUMSC)        /* words/log drum */\r
#define DRM_NUMLD       6                               /* log drums/phys drum */\r
#define DRM_SIZE        (DRM_NUMLD * DRM_NUMWDL)        /* words/phys drum */\r
#define GET_POS(x)      ((int) fmod (sim_gtime() / ((double) (x)), \\r
                        ((double) DRM_NUMWDS)))\r
\r
/* Drum address from channel */\r
\r
#define DRM_V_PHY       30                              /* physical drum sel */\r
#define DRM_M_PHY       07\r
#define DRM_V_LOG       18                              /* logical drum sel */\r
#define DRM_M_LOG       07\r
#define DRM_V_WDA       0                               /* word address */\r
#define DRM_M_WDA       (DRM_NUMWDL - 1)\r
#define DRM_GETPHY(x)   (((uint32) ((x) >> DRM_V_PHY)) & DRM_M_PHY)\r
#define DRM_GETLOG(x)   ((((uint32) (x)) >> DRM_V_LOG) & DRM_M_LOG)\r
#define DRM_GETWDA(x)   ((((uint32) (x)) >> DRM_V_WDA) & DRM_M_WDA)\r
#define DRM_GETDA(x)    (((DRM_GETLOG(x) - 1) * DRM_NUMWDL) + DRM_GETWDA(x))\r
\r
/* Drum controller states */\r
\r
#define DRM_IDLE        0\r
#define DRM_1ST         1\r
#define DRM_DATA        2\r
#define DRM_EOS         3\r
\r
uint32 drm_ch = CH_G;                                   /* drum channel */\r
uint32 drm_da = 0;                                      /* drum address */\r
uint32 drm_sta = 0;                                     /* state */\r
uint32 drm_op = 0;                                      /* operation */\r
t_uint64 drm_chob = 0;                                  /* output buf */\r
uint32 drm_chob_v = 0;                                  /* valid */\r
int32 drm_time = 10;                                    /* inter-word time */\r
\r
extern uint32 ind_ioc;\r
\r
t_stat drm_svc (UNIT *uptr);\r
t_stat drm_reset (DEVICE *dptr);\r
t_stat drm_chsel (uint32 ch, uint32 sel, uint32 unit);\r
t_stat drm_chwr (uint32 ch, t_uint64 val, uint32 flags);\r
t_bool drm_da_incr (void);\r
\r
/* DRM data structures\r
\r
   drm_dev      DRM device descriptor\r
   drm_unit     DRM unit descriptor\r
   drm_reg      DRM register list\r
*/\r
\r
DIB drm_dib = { &drm_chsel, &drm_chwr };\r
\r
UNIT drm_unit[] = {\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE, DRM_SIZE) },\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE, DRM_SIZE) },\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) },\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) },\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) },\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) },\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) },\r
    { UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+\r
             UNIT_MUSTBUF+UNIT_DISABLE+UNIT_DIS, DRM_SIZE) }\r
    };\r
\r
REG drm_reg[] = {\r
    { ORDATA (STATE, drm_sta, 2) },\r
    { ORDATA (DA, drm_da, 18) },\r
    { FLDATA (OP, drm_op, 0) },\r
    { ORDATA (CHOB, drm_chob, 36) },\r
    { FLDATA (CHOBV, drm_chob_v, 0) },\r
    { DRDATA (TIME, drm_time, 24), REG_NZ + PV_LEFT },\r
    { DRDATA (CHAN, drm_ch, 3), REG_HRO },\r
    { NULL }\r
    };\r
\r
MTAB drm_mtab[] = {\r
    { MTAB_XTD|MTAB_VDV, 0, "CHANNEL", NULL, NULL, &ch_show_chan },\r
    { 0 }\r
    };\r
\r
DEVICE drm_dev = {\r
    "DRM", drm_unit, drm_reg, drm_mtab,\r
    DRM_NUMDR, 8, 18, 1, 8, 36,\r
    NULL, NULL, &drm_reset,\r
    NULL, NULL, NULL,\r
    &drm_dib, DEV_DIS\r
    };\r
\r
/* Channel select routine */\r
\r
t_stat drm_chsel (uint32 ch, uint32 sel, uint32 unit)\r
{\r
drm_ch = ch;                                            /* save channel */\r
if (sel & CHSL_NDS) return ch6_end_nds (ch);            /* nds? nop */\r
\r
switch (sel) {                                          /* case on cmd */\r
\r
    case CHSL_RDS:                                      /* read */\r
    case CHSL_WRS:                                      /* write */\r
        if (drm_sta != DRM_IDLE) return ERR_STALL;      /* busy? */\r
        drm_sta = DRM_1ST;                              /* initial state */\r
        if (sel == CHSL_WRS) drm_op = 1;                /* set read/write */\r
        else drm_op = 0;                                /* LCHx sends addr */\r
        break;                                          /* wait for addr */\r
\r
    default:                                            /* other */\r
        return STOP_ILLIOP;\r
        }\r
return SCPE_OK;\r
}\r
\r
/* Channel write routine */\r
\r
t_stat drm_chwr (uint32 ch, t_uint64 val, uint32 flags)\r
{\r
uint32 u, l;\r
int32 cp, dp;\r
\r
if (drm_sta == DRM_1ST) {\r
    u = DRM_GETPHY (val);                               /* get unit */\r
    l = DRM_GETLOG (val);                               /* get logical address */\r
    if ((u >= DRM_NUMDR) ||                             /* invalid unit? */\r
        (drm_unit[u].flags & UNIT_DIS) ||               /* disabled unit? */\r
        (l == 0) || (l > DRM_NUMLD)) {                  /* invalid log drum? */\r
        ch6_err_disc (ch, U_DRM, CHF_TRC);              /* disconnect */\r
        drm_sta = DRM_IDLE;\r
        return SCPE_OK;\r
        }\r
    drm_da = DRM_GETDA (val);                           /* get drum addr */\r
    cp = GET_POS (drm_time);                            /* current pos in sec */\r
    dp = (drm_da & DRM_SCMASK) - cp;                    /* delta to desired pos */\r
    if (dp <= 0) dp = dp + DRM_NUMWDS;                  /* if neg, add rev */\r
    sim_activate (&drm_unit[u], dp * drm_time);         /* schedule */\r
    if (drm_op) ch6_req_wr (ch, U_DRM);                 /* if write, get word */\r
    drm_sta = DRM_DATA;\r
    drm_chob = 0;                                       /* clr, inval buffer */\r
    drm_chob_v = 0;\r
    }\r
else {\r
    drm_chob = val & DMASK;\r
    drm_chob_v = 1;\r
    }\r
return SCPE_OK;\r
}\r
\r
/* Unit service - this code assumes the entire drum is buffered */\r
\r
t_stat drm_svc (UNIT *uptr)\r
{\r
t_uint64 *fbuf = (t_uint64 *) uptr->filebuf;\r
\r
if ((uptr->flags & UNIT_BUF) == 0) {                    /* not buf? */\r
    ch6_err_disc (drm_ch, U_DRM, CHF_TRC);              /* set TRC, disc */\r
    drm_sta = DRM_IDLE;                                 /* drum is idle */\r
    return SCPE_UNATT;\r
    }\r
if (drm_da >= DRM_SIZE) {                               /* nx logical drum? */\r
    ch6_err_disc (drm_ch, U_DRM, CHF_EOF);              /* set EOF, disc */\r
    drm_sta = DRM_IDLE;                                 /* drum is idle */\r
    return SCPE_OK;\r
    }\r
\r
switch (drm_sta) {                                      /* case on state */\r
\r
    case DRM_DATA:                                      /* data */\r
        if (drm_op) {                                   /* write? */\r
            if (drm_chob_v) drm_chob_v = 0;             /* valid? clear */\r
            else if (ch6_qconn (drm_ch, U_DRM))         /* no, chan conn? */\r
                ind_ioc = 1;                            /* io check */\r
            fbuf[drm_da] = drm_chob;                    /* get data */\r
            if (drm_da >= uptr->hwmark) uptr->hwmark = drm_da + 1;\r
            if (!drm_da_incr ()) ch6_req_wr (drm_ch, U_DRM);\r
            }\r
        else{                                           /* read */\r
            ch6_req_rd (drm_ch, U_DRM, fbuf[drm_da], 0); /* send word to channel */\r
            drm_da_incr ();\r
            }\r
        sim_activate (uptr, drm_time);                  /* next word */\r
        break;\r
\r
    case DRM_EOS:                                       /* end sector */\r
        if (ch6_qconn (drm_ch, U_DRM))                  /* drum still conn? */\r
            ch6_err_disc (drm_ch, U_DRM, CHF_EOF);      /* set EOF, disc */\r
        drm_sta = DRM_IDLE;                             /* drum is idle */\r
        break;\r
        }                                               /* end case */\r
\r
return SCPE_OK;\r
}\r
\r
/* Increment drum address - return true, set new state if end of sector */\r
\r
t_bool drm_da_incr (void)\r
{\r
drm_da = drm_da + 1;\r
if (drm_da & DRM_SCMASK) return FALSE;\r
drm_sta = DRM_EOS;\r
return TRUE;\r
}\r
\r
/* Reset routine */\r
\r
t_stat drm_reset (DEVICE *dptr)\r
{\r
uint32 i;\r
\r
drm_da = 0;\r
drm_op = 0;\r
drm_sta = DRM_IDLE;\r
drm_chob = 0;\r
drm_chob_v = 0;\r
for (i = 0; i < dptr->numunits; i++) sim_cancel (dptr->units + i);\r
return SCPE_OK;\r
}\r