First Commit of my working state

[simh.git] / NOVA / nova_clk.c

/* nova_clk.c: NOVA real-time clock simulator\r
\r
   Copyright (c) 1993-2008, Robert M. Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   clk          real-time clock\r
\r
   04-Jul-07    BKR     DEV_SET/CLR macros now used,\r
                        changed CLK name to RTC for DG compatiblity,\r
                        device may now bw DISABLED\r
   01-Mar-03    RMS     Added SET/SHOW CLK FREQ support\r
   03-Oct-02    RMS     Added DIB\r
   17-Sep-01    RMS     Added terminal multiplexor support\r
   17-Mar-01    RMS     Moved function prototype\r
   05-Mar-01    RMS     Added clock calibration\r
   24-Sep-97    RMS     Fixed bug in unit service (found by Charles Owen)\r
*/\r
\r
#include "nova_defs.h"\r
\r
extern int32 int_req, dev_busy, dev_done, dev_disable ;\r
\r
int32 clk_sel = 0;                                      /* selected freq */\r
int32 clk_time[4] = { 16000, 100000, 10000, 1000 };     /* freq table */\r
int32 clk_tps[4] = { 60, 10, 100, 1000 };               /* ticks per sec */\r
int32 clk_adj[4] = { 1, -5, 2, 20 };                    /* tmxr adjust */\r
int32 tmxr_poll = 16000;                                /* tmxr poll */\r
\r
int32  clk (int32 pulse, int32 code, int32 AC);\r
t_stat clk_svc (UNIT *uptr);\r
t_stat clk_reset (DEVICE *dptr);\r
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);\r
\r
/* CLK data structures\r
\r
   clk_dev      CLK device descriptor\r
   clk_unit     CLK unit descriptor\r
   clk_reg      CLK register list\r
*/\r
\r
DIB clk_dib = { DEV_CLK, INT_CLK, PI_CLK, &clk };\r
\r
UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };\r
\r
REG clk_reg[] = {\r
    { ORDATA (SELECT, clk_sel, 2) },\r
    { FLDATA (BUSY, dev_busy, INT_V_CLK) },\r
    { FLDATA (DONE, dev_done, INT_V_CLK) },\r
    { FLDATA (DISABLE, dev_disable, INT_V_CLK) },\r
    { FLDATA (INT, int_req, INT_V_CLK) },\r
    { DRDATA (TIME0, clk_time[0], 24), REG_NZ + PV_LEFT },\r
    { DRDATA (TIME1, clk_time[1], 24), REG_NZ + PV_LEFT },\r
    { DRDATA (TIME2, clk_time[2], 24), REG_NZ + PV_LEFT },\r
    { DRDATA (TIME3, clk_time[3], 24), REG_NZ + PV_LEFT },\r
    { DRDATA (TPS0, clk_tps[0], 6), PV_LEFT + REG_HRO },\r
    { NULL }\r
    };\r
\r
MTAB clk_mod[] = {\r
    { MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",\r
      &clk_set_freq, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",\r
      &clk_set_freq, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "LINE", NULL,\r
      NULL, &clk_show_freq, NULL },\r
    { 0 }\r
    };\r
\r
DEVICE clk_dev = {\r
    "RTC", &clk_unit, clk_reg, clk_mod,\r
    1, 0, 0, 0, 0, 0,\r
    NULL, NULL, &clk_reset,\r
    NULL, NULL, NULL,\r
    &clk_dib, DEV_DISABLE\r
    };\r
\r
\r
/* IOT routine */\r
\r
int32 clk (int32 pulse, int32 code, int32 AC)\r
{\r
if (code == ioDOA) {                                    /* DOA */\r
    clk_sel = AC & 3;                                   /* save select */\r
    sim_rtc_init (clk_time[clk_sel]);                   /* init calibr */\r
    }\r
\r
switch (pulse) {                                        /* decode IR<8:9> */\r
\r
  case iopS:                                            /* start */\r
    DEV_SET_BUSY( INT_CLK ) ;\r
    DEV_CLR_DONE( INT_CLK ) ;\r
    DEV_UPDATE_INTR ;\r
    if (!sim_is_active (&clk_unit))                     /* not running? */\r
        sim_activate (&clk_unit,                        /* activate */\r
            sim_rtc_init (clk_time[clk_sel]));          /* init calibr */\r
    break;\r
\r
  case iopC:                                            /* clear */\r
    DEV_CLR_BUSY( INT_CLK ) ;\r
    DEV_CLR_DONE( INT_CLK ) ;\r
    DEV_UPDATE_INTR ;\r
    sim_cancel (&clk_unit);                             /* deactivate unit */\r
    break;\r
    }                                                   /* end switch */\r
\r
return 0;\r
}\r
\r
/* Unit service */\r
\r
t_stat clk_svc (UNIT *uptr)\r
{\r
int32 t;\r
\r
if ( DEV_IS_BUSY(INT_CLK) )\r
    {\r
    DEV_CLR_BUSY( INT_CLK ) ;\r
    DEV_SET_DONE( INT_CLK ) ;\r
    DEV_UPDATE_INTR ;\r
    }\r
t = sim_rtc_calb (clk_tps[clk_sel]);                    /* calibrate delay */\r
sim_activate (&clk_unit, t);                            /* reactivate unit */\r
if (clk_adj[clk_sel] > 0)                               /* clk >= 60Hz? */\r
    tmxr_poll = t * clk_adj[clk_sel];                   /* poll is longer */\r
else\r
    tmxr_poll = t / (-clk_adj[clk_sel]);                /* poll is shorter */\r
\r
return SCPE_OK;\r
}\r
\r
/* Reset routine */\r
\r
t_stat clk_reset (DEVICE *dptr)\r
{\r
clk_sel = 0;\r
DEV_CLR_BUSY( INT_CLK ) ;\r
DEV_CLR_DONE( INT_CLK ) ;\r
DEV_UPDATE_INTR ;\r
\r
sim_cancel (&clk_unit);                                 /* deactivate unit */\r
tmxr_poll = clk_time[0];                                /* poll is default */\r
return SCPE_OK;\r
}\r
\r
/* Set line frequency */\r
\r
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (cptr) return SCPE_ARG;\r
if ((val != 50) && (val != 60)) return SCPE_IERR;\r
clk_tps[0] = val;\r
return SCPE_OK;\r
}\r
\r
/* Show line frequency */\r
\r
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)\r
{\r
fprintf (st, (clk_tps[0] == 50)? "50Hz": "60Hz");\r
return SCPE_OK;\r
}\r