First Commit of my working state

[simh.git] / PDP1 / pdp1_clk.c

/* pdp1_clk.c: PDP-1D clock simulator\r
\r
   Copyright (c) 2006, Robert M. Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   bused in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   clk          PDP-1D clock\r
\r
   Note that the clock is run at 1/8 of real speed (125Hz instead of 1Khz), to\r
   provide for eventual implementation of idling.\r
*/\r
\r
#include "pdp1_defs.h"\r
\r
#define CLK_HWRE_TPS    1000                            /* hardware freq */\r
#define CLK_TPS         125                             /* sim freq */\r
#define CLK_CNTS        (CLK_HWRE_TPS / CLK_TPS)        /* counts per tick */\r
#define CLK_C1MIN       (1000 * 60)                     /* counts per min */\r
#define CLK_C32MS       32                              /* counts per 32ms */\r
\r
int32 clk32ms_sbs = 0;                                  /* 32ms SBS level */\r
int32 clk1min_sbs = 0;                                  /* 1min SBS level */\r
int32 clk_cntr = 0;\r
int32 tmxr_poll = 5000;\r
\r
extern int32 stop_inst;\r
\r
t_stat clk_svc (UNIT *uptr);\r
t_stat clk_reset (DEVICE *dptr);\r
\r
/* CLK data structures\r
\r
   clk_dev      CLK device descriptor\r
   clk_unit     CLK unit\r
   clk_reg      CLK register list\r
*/\r
\r
UNIT clk_unit = {\r
    UDATA (&clk_svc, 0, 0), 5000\r
    };\r
\r
REG clk_reg[] = {\r
    { ORDATA (CNTR, clk_cntr, 16) },\r
    { DRDATA (SBS32LVL, clk32ms_sbs, 4), REG_HRO },\r
    { DRDATA (SBS1MLVL, clk1min_sbs, 4), REG_HRO },\r
    { NULL }\r
    };\r
\r
MTAB clk_mod[] = {\r
    { MTAB_XTD|MTAB_VDV, 0, "SBS32MSLVL", "SBS32MSLVL",\r
      &dev_set_sbs, &dev_show_sbs, (void *) &clk32ms_sbs },\r
    { MTAB_XTD|MTAB_VDV, 0, "SBS1MINLVL", "SBS1MINLVL",\r
      &dev_set_sbs, &dev_show_sbs, (void *) &clk1min_sbs },\r
    { 0 }\r
    };\r
\r
DEVICE clk_dev = {\r
    "CLK", &clk_unit, clk_reg, clk_mod,\r
    1, 10, 31, 1, 8, 8,\r
    NULL, NULL, &clk_reset,\r
    NULL, NULL, NULL,\r
    NULL, DEV_DISABLE | DEV_DIS\r
    };\r
\r
/* Clock IOT routine */\r
\r
int32 clk (int32 inst, int32 dev, int32 dat)\r
{\r
int32 used, incr;\r
\r
if (clk_dev.flags & DEV_DIS)                            /* disabled? */\r
    return (stop_inst << IOT_V_REASON) | dat;           /* illegal inst */\r
used = tmxr_poll - (sim_is_active (&clk_unit) - 1);\r
incr = (used * CLK_CNTS) / tmxr_poll;\r
return clk_cntr + incr;\r
}\r
\r
/* Unit service, generate appropriate interrupts */\r
\r
t_stat clk_svc (UNIT *uptr)\r
{\r
if (clk_dev.flags & DEV_DIS) return SCPE_OK;            /* disabled? */\r
tmxr_poll = sim_rtcn_calb (CLK_TPS, TMR_CLK);           /* calibrate clock */\r
sim_activate (&clk_unit, tmxr_poll);                    /* reactivate unit */\r
clk_cntr = clk_cntr + CLK_CNTS;                         /* incr counter */\r
if ((clk_cntr % CLK_C32MS) == 0)                        /* 32ms interval? */\r
    dev_req_int (clk32ms_sbs);                          /* req intr */\r
if (clk_cntr >= CLK_C1MIN) {                            /* 1min interval? */\r
    dev_req_int (clk1min_sbs);                          /* req intr */\r
    clk_cntr = 0;                                       /* reset counter */\r
    }\r
return SCPE_OK;\r
}\r
\r
/* Reset routine */\r
\r
t_stat clk_reset (DEVICE *dptr)\r
{\r
if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit);    /* disabled? */\r
else {\r
    tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK);\r
    sim_activate_abs (&clk_unit, tmxr_poll);            /* activate unit */\r
    }\r
clk_cntr = 0;                                           /* clear counter */\r
return SCPE_OK;\r
}\r