[simh.git] / PDP1 / pdp1_defs.h

/* pdp1_defs.h: 18b PDP simulator definitions\r
\r
   Copyright (c) 1993-2006, Robert M. Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   21-Dec-06    RMS     Added 16-channel sequence break support\r
   22-Jul-05    RMS     Fixed definition of CPLS_DPY\r
   08-Feb-04    PLB     Added support for display\r
   08-Dec-03    RMS     Added support for parallel drum\r
   18-Oct-03    RMS     Added DECtape off reel message\r
   22-Jul-03    RMS     Updated for "hardware" RIM loader\r
                        Revised to detect I/O wait hang\r
   05-Dec-02    RMS     Added IOT skip support (required by drum)\r
   14-Apr-99    RMS     Changed t_addr to unsigned\r
\r
   The PDP-1 was Digital's first computer.  The system design evolved during\r
   its life, and as a result, specifications are sketchy or contradictory.\r
   This simulator is based on the 1962 maintenance manual.\r
\r
   This simulator implements the following options:\r
\r
   Automatic multiply/divide    Type 10\r
   Memory extension control     Type 15\r
   Parallel drum                Type 23\r
   Serial drum                  Type 24\r
   Graphic display              Type 30\r
   Line printer control         Type 62\r
   Microtape (DECtape) control  Type 550\r
*/\r
\r
#ifndef _PDP1_DEFS_H_\r
#define _PDP1_DEFS_H_   0\r
\r
#include "sim_defs.h"\r
\r
/* Simulator stop codes */\r
\r
#define STOP_RSRV       1                               /* must be 1 */\r
#define STOP_HALT       2                               /* HALT */\r
#define STOP_IBKPT      3                               /* breakpoint */\r
#define STOP_XCT        4                               /* nested XCT's */\r
#define STOP_IND        5                               /* nested indirects */\r
#define STOP_WAIT       6                               /* IO wait hang */\r
#define STOP_DTOFF      7                               /* DECtape off reel */\r
#define ERR_RMV         10                              /* restrict mode viol */\r
\r
/* Memory */\r
\r
#define ASIZE           16                              /* address bits */\r
#define MAXMEMSIZE      (1u << ASIZE)                   /* max mem size */\r
#define AMASK           (MAXMEMSIZE - 1)                /* address mask */\r
#define MEMSIZE         (cpu_unit.capac)                /* actual memory size */\r
#define MEM_ADDR_OK(x)  (((uint32) (x)) < MEMSIZE)\r
\r
/* Architectural constants */\r
\r
#define SIGN            0400000                         /* sign */\r
#define DMASK           0777777                         /* data mask */\r
#define DAMASK          0007777                         /* direct addr */\r
#define EPCMASK         (AMASK & ~DAMASK)               /* extended addr */\r
#define IA              0010000                         /* indirect flag */\r
#define IO_WAIT         0010000                         /* I/O sync wait */\r
#define IO_CPLS         0004000                         /* completion pulse */\r
#define OP_DAC          0240000                         /* DAC */\r
#define OP_DIO          0320000                         /* DIO */\r
#define OP_JMP          0600000                         /* JMP */\r
#define GEN_CPLS(x)     (((x) ^ ((x) << 1)) & IO_WAIT)  /* completion pulse? */\r
\r
/* Program flags/sense switches */\r
\r
#define PF_V_L          7\r
#define PF_V_RNG        6\r
#define PF_L            (1u << PF_V_L)\r
#define PF_RNG          (1u << PF_V_RNG)\r
#define PF_SS_1         0040\r
#define PF_SS_2         0020\r
#define PF_SS_3         0010\r
#define PF_SS_4         0004\r
#define PF_SS_5         0002\r
#define PF_SS_6         0001\r
#define PF_VR_ALL       0377\r
#define PF_SS_ALL       0077\r
\r
/* Restict mode */\r
\r
#define RTB_IOT         0400000\r
#define RTB_ILL         0200000\r
#define RTB_HLT         0100000\r
#define RTB_DBK         0040000\r
#define RTB_CHR         0020000\r
#define RTB_MB_MASK     0017777\r
\r
#define RM45_V_BNK      14\r
#define RM45_M_BNK      003\r
#define RM48_V_BNK      12\r
#define RM48_M_BNK      017\r
\r
#define RN45_SIZE       4\r
\r
/* IOT subroutine return codes */\r
\r
#define IOT_V_SKP       18                              /* skip */\r
#define IOT_SKP         (1 << IOT_V_SKP)\r
#define IOT_V_REASON    (IOT_V_SKP + 1)                 /* reason */\r
#define IOT_REASON      (1 << IOT_V_REASON)\r
#define IORETURN(f,v)   ((f)? (v): SCPE_OK)             /* stop on error */\r
\r
/* I/O status flags */\r
\r
#define IOS_V_LPN       17                              /* light pen */\r
#define IOS_V_PTR       16                              /* paper tape reader */\r
#define IOS_V_TTO       15                              /* typewriter out */\r
#define IOS_V_TTI       14                              /* typewriter in */\r
#define IOS_V_PTP       13                              /* paper tape punch */\r
#define IOS_V_DRM       12                              /* drum */\r
#define IOS_V_SQB       11                              /* sequence break */\r
#define IOS_V_PNT       3                               /* print done */\r
#define IOS_V_SPC       2                               /* space done */\r
#define IOS_V_DCS       1                               /* data comm sys */\r
#define IOS_V_DRP       0                               /* parallel drum busy */\r
\r
#define IOS_LPN         (1 << IOS_V_LPN)\r
#define IOS_PTR         (1 << IOS_V_PTR)\r
#define IOS_TTO         (1 << IOS_V_TTO)\r
#define IOS_TTI         (1 << IOS_V_TTI)\r
#define IOS_PTP         (1 << IOS_V_PTP)\r
#define IOS_DRM         (1 << IOS_V_DRM)\r
#define IOS_SQB         (1 << IOS_V_SQB)\r
#define IOS_PNT         (1 << IOS_V_PNT)\r
#define IOS_SPC         (1 << IOS_V_SPC)\r
#define IOS_DCS         (1 << IOS_V_DCS)\r
#define IOS_DRP         (1 << IOS_V_DRP)\r
\r
/* Completion pulses */\r
\r
#define CPLS_V_PTR      5\r
#define CPLS_V_PTP      4\r
#define CPLS_V_TTO      3\r
#define CPLS_V_LPT      2\r
#define CPLS_V_DPY      1\r
#define CPLS_PTR        (1 << CPLS_V_PTR)\r
#define CPLS_PTP        (1 << CPLS_V_PTP)\r
#define CPLS_TTO        (1 << CPLS_V_TTO)\r
#define CPLS_LPT        (1 << CPLS_V_LPT)\r
#define CPLS_DPY        (1 << CPLS_V_DPY)\r
\r
/* One channel sequence break */\r
\r
#define SB_V_IP         0                               /* in progress */\r
#define SB_V_RQ         1                               /* request */\r
#define SB_V_ON         2                               /* enabled */\r
\r
#define SB_IP           (1 << SB_V_IP)\r
#define SB_RQ           (1 << SB_V_RQ)\r
#define SB_ON           (1 << SB_V_ON)\r
\r
/* 16 channel sequence break */\r
\r
#define SBS_LVLS        16                              /* num levels */\r
#define SBS_LVL_MASK    (SBS_LVLS - 1)\r
#define SBS_LVL_RMV     14                              /* restrict level */\r
#define SBS_MASK(x)     (1u << (SBS_LVLS - 1 - (x)))    /* level to mask */\r
\r
/* Timers */\r
\r
#define TMR_CLK         0\r
\r
/* Device routines */\r
\r
t_stat dev_req_int (int32 lvl);\r
t_stat dev_set_sbs (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat dev_show_sbs (FILE *st, UNIT *uptr, int32 val, void *desc);\r
\r
#endif\r
Commit	Line	Data
196ba1fc PH	1	/* pdp1_defs.h: 18b PDP simulator definitions\r
	2	\r
	3	Copyright (c) 1993-2006, Robert M. Supnik\r
	4	\r
	5	Permission is hereby granted, free of charge, to any person obtaining a\r
	6	copy of this software and associated documentation files (the "Software"),\r
	7	to deal in the Software without restriction, including without limitation\r
	8	the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
	9	and/or sell copies of the Software, and to permit persons to whom the\r
	10	Software is furnished to do so, subject to the following conditions:\r
	11	\r
	12	The above copyright notice and this permission notice shall be included in\r
	13	all copies or substantial portions of the Software.\r
	14	\r
	15	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
	16	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
	17	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r
	18	ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
	19	IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
	20	CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
	21	\r
	22	Except as contained in this notice, the name of Robert M Supnik shall not be\r
	23	used in advertising or otherwise to promote the sale, use or other dealings\r
	24	in this Software without prior written authorization from Robert M Supnik.\r
	25	\r
	26	21-Dec-06 RMS Added 16-channel sequence break support\r
	27	22-Jul-05 RMS Fixed definition of CPLS_DPY\r
	28	08-Feb-04 PLB Added support for display\r
	29	08-Dec-03 RMS Added support for parallel drum\r
	30	18-Oct-03 RMS Added DECtape off reel message\r
	31	22-Jul-03 RMS Updated for "hardware" RIM loader\r
	32	Revised to detect I/O wait hang\r
	33	05-Dec-02 RMS Added IOT skip support (required by drum)\r
	34	14-Apr-99 RMS Changed t_addr to unsigned\r
	35	\r
	36	The PDP-1 was Digital's first computer. The system design evolved during\r
	37	its life, and as a result, specifications are sketchy or contradictory.\r
	38	This simulator is based on the 1962 maintenance manual.\r
	39	\r
	40	This simulator implements the following options:\r
	41	\r
	42	Automatic multiply/divide Type 10\r
	43	Memory extension control Type 15\r
	44	Parallel drum Type 23\r
	45	Serial drum Type 24\r
	46	Graphic display Type 30\r
	47	Line printer control Type 62\r
	48	Microtape (DECtape) control Type 550\r
	49	*/\r
	50	\r
	51	#ifndef _PDP1_DEFS_H_\r
	52	#define _PDP1_DEFS_H_ 0\r
	53	\r
	54	#include "sim_defs.h"\r
	55	\r
	56	/* Simulator stop codes */\r
	57	\r
	58	#define STOP_RSRV 1 /* must be 1 */\r
	59	#define STOP_HALT 2 /* HALT */\r
	60	#define STOP_IBKPT 3 /* breakpoint */\r
	61	#define STOP_XCT 4 /* nested XCT's */\r
	62	#define STOP_IND 5 /* nested indirects */\r
	63	#define STOP_WAIT 6 /* IO wait hang */\r
	64	#define STOP_DTOFF 7 /* DECtape off reel */\r
65	#define ERR_RMV 10 /* restrict mode viol */\r
66	\r
67	/* Memory */\r
68	\r
69	#define ASIZE 16 /* address bits */\r
70	#define MAXMEMSIZE (1u << ASIZE) /* max mem size */\r
71	#define AMASK (MAXMEMSIZE - 1) /* address mask */\r
72	#define MEMSIZE (cpu_unit.capac) /* actual memory size */\r
73	#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)\r
74	\r
75	/* Architectural constants */\r
76	\r
77	#define SIGN 0400000 /* sign */\r
78	#define DMASK 0777777 /* data mask */\r
79	#define DAMASK 0007777 /* direct addr */\r
80	#define EPCMASK (AMASK & ~DAMASK) /* extended addr */\r
81	#define IA 0010000 /* indirect flag */\r
82	#define IO_WAIT 0010000 /* I/O sync wait */\r
83	#define IO_CPLS 0004000 /* completion pulse */\r
84	#define OP_DAC 0240000 /* DAC */\r
85	#define OP_DIO 0320000 /* DIO */\r
86	#define OP_JMP 0600000 /* JMP */\r
87	#define GEN_CPLS(x) (((x) ^ ((x) << 1)) & IO_WAIT) /* completion pulse? */\r
88	\r
89	/* Program flags/sense switches */\r
90	\r
91	#define PF_V_L 7\r
92	#define PF_V_RNG 6\r
93	#define PF_L (1u << PF_V_L)\r
94	#define PF_RNG (1u << PF_V_RNG)\r
95	#define PF_SS_1 0040\r
96	#define PF_SS_2 0020\r
97	#define PF_SS_3 0010\r
98	#define PF_SS_4 0004\r
99	#define PF_SS_5 0002\r
100	#define PF_SS_6 0001\r
101	#define PF_VR_ALL 0377\r
102	#define PF_SS_ALL 0077\r
103	\r
104	/* Restict mode */\r
105	\r
106	#define RTB_IOT 0400000\r
107	#define RTB_ILL 0200000\r
108	#define RTB_HLT 0100000\r
109	#define RTB_DBK 0040000\r
110	#define RTB_CHR 0020000\r
111	#define RTB_MB_MASK 0017777\r
112	\r
113	#define RM45_V_BNK 14\r
114	#define RM45_M_BNK 003\r
115	#define RM48_V_BNK 12\r
116	#define RM48_M_BNK 017\r
117	\r
118	#define RN45_SIZE 4\r
119	\r
120	/* IOT subroutine return codes */\r
121	\r
122	#define IOT_V_SKP 18 /* skip */\r
123	#define IOT_SKP (1 << IOT_V_SKP)\r
124	#define IOT_V_REASON (IOT_V_SKP + 1) /* reason */\r
125	#define IOT_REASON (1 << IOT_V_REASON)\r
126	#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */\r
127	\r
128	/* I/O status flags */\r
129	\r
130	#define IOS_V_LPN 17 /* light pen */\r
131	#define IOS_V_PTR 16 /* paper tape reader */\r
132	#define IOS_V_TTO 15 /* typewriter out */\r
133	#define IOS_V_TTI 14 /* typewriter in */\r
134	#define IOS_V_PTP 13 /* paper tape punch */\r
135	#define IOS_V_DRM 12 /* drum */\r
136	#define IOS_V_SQB 11 /* sequence break */\r
137	#define IOS_V_PNT 3 /* print done */\r
138	#define IOS_V_SPC 2 /* space done */\r
139	#define IOS_V_DCS 1 /* data comm sys */\r
140	#define IOS_V_DRP 0 /* parallel drum busy */\r
141	\r
142	#define IOS_LPN (1 << IOS_V_LPN)\r
143	#define IOS_PTR (1 << IOS_V_PTR)\r
144	#define IOS_TTO (1 << IOS_V_TTO)\r
145	#define IOS_TTI (1 << IOS_V_TTI)\r
146	#define IOS_PTP (1 << IOS_V_PTP)\r
147	#define IOS_DRM (1 << IOS_V_DRM)\r
148	#define IOS_SQB (1 << IOS_V_SQB)\r
149	#define IOS_PNT (1 << IOS_V_PNT)\r
150	#define IOS_SPC (1 << IOS_V_SPC)\r
151	#define IOS_DCS (1 << IOS_V_DCS)\r
152	#define IOS_DRP (1 << IOS_V_DRP)\r
153	\r
154	/* Completion pulses */\r
155	\r
156	#define CPLS_V_PTR 5\r
157	#define CPLS_V_PTP 4\r
158	#define CPLS_V_TTO 3\r
159	#define CPLS_V_LPT 2\r
160	#define CPLS_V_DPY 1\r
161	#define CPLS_PTR (1 << CPLS_V_PTR)\r
162	#define CPLS_PTP (1 << CPLS_V_PTP)\r
163	#define CPLS_TTO (1 << CPLS_V_TTO)\r
164	#define CPLS_LPT (1 << CPLS_V_LPT)\r
165	#define CPLS_DPY (1 << CPLS_V_DPY)\r
166	\r
167	/* One channel sequence break */\r
168	\r
169	#define SB_V_IP 0 /* in progress */\r
170	#define SB_V_RQ 1 /* request */\r
171	#define SB_V_ON 2 /* enabled */\r
172	\r
173	#define SB_IP (1 << SB_V_IP)\r
174	#define SB_RQ (1 << SB_V_RQ)\r
175	#define SB_ON (1 << SB_V_ON)\r
176	\r
177	/* 16 channel sequence break */\r
178	\r
179	#define SBS_LVLS 16 /* num levels */\r
180	#define SBS_LVL_MASK (SBS_LVLS - 1)\r
181	#define SBS_LVL_RMV 14 /* restrict level */\r
182	#define SBS_MASK(x) (1u << (SBS_LVLS - 1 - (x))) /* level to mask */\r
183	\r
184	/* Timers */\r
185	\r
186	#define TMR_CLK 0\r
187	\r
188	/* Device routines */\r
189	\r
190	t_stat dev_req_int (int32 lvl);\r
191	t_stat dev_set_sbs (UNIT uptr, int32 val, char cptr, void *desc);\r
192	t_stat dev_show_sbs (FILE st, UNIT uptr, int32 val, void *desc);\r
193	\r
194	#endif\r