projects / simh.git / blame
| Commit | Line | Data |
|---|---|---|
| 196ba1fc PH |
1 | Bugs Found and Fixed During Simulator Debug\r |
| 2 | \r | |
| 3 | 1. pushj cleared T2 after setting it\r | |
| 4 | 2. if timer autoadjust is enabled, timer diagnostic may fail,\r | |
| 5 | depending on host CPU speed\r | |
| 6 | 3. DFAD/DFSB should use FP_ONES instead of ONES\r | |
| 7 | 4. TLB physical address max = 1MW, tested in diagnostic\r | |
| 8 | 5. DPB does read/write, not read-modify/write\r | |
| 9 | 6. Fetch error takes priority over traps, due to prefetching\r | |
| 10 | of next instruction\r | |
| 11 | 7. HSB is 36b, was 32b\r | |
| 12 | 8. CPU and PAG devices had mismatched types\r | |
| 13 | 9. non-zero sections in Tops-20 paging section indirect may\r | |
| 14 | cause non-existent memory error, due to microcode "error"\r | |
| 15 | 10. PXCT test for user mode was backward\r | |
| 16 | 11. Timer interrupts were not implemented in Tops-20 indirect\r | |
| 17 | chains\r | |
| 18 | 12. epta/upta hit known bug in VC++ implementation of 64b\r | |
| 19 | data types\r | |
| 20 | 13. final W calculation in Tops-20 paging was incorrect\r | |
| 21 | 14. Timer representation lost sub msec values\r | |
| 22 | 15. UBA initialization reset the UBA itself\r | |
| 23 | 16. RHCS1: writing IE cannot trigger an interrupt\r | |
| 24 | 17. Tape bootstrap was set to 800bpi instead of 1600bpi\r | |
| 25 | 18. FIXR off by 1 in testing for lower limit to process\r |