[simh.git] / PDP11 / pdp11_pclk.c

/* pdp11_pclk.c: KW11P programmable clock simulator\r
\r
   Copyright (c) 1993-2008, Robert M Supnik\r
   Written by John Dundas, used with his gracious permission\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   pclk         KW11P line frequency clock\r
\r
   20-May-08    RMS     Standardized clock delay at 1mips\r
   18-Jun-07    RMS     Added UNIT_IDLE flag\r
   07-Jul-05    RMS     Removed extraneous externs\r
\r
   KW11-P Programmable Clock\r
\r
   I/O Page Registers:\r
\r
        CSR     17 772 540\r
        CSB     17 772 542\r
        CNT     17 772 544\r
\r
   Vector:      0104\r
\r
   Priority:    BR6\r
\r
   ** Theory of Operation **\r
\r
   A real KW11-P is built around the following major components:\r
   - 16-bit up/down counter\r
   - 16-bit count set buffer\r
   - 9-bit control and status register\r
   - clocks: crystal controlled (1) 100 kHz and (2) 10 kHz clocks,\r
     (3) a 50/60 Hz line frequency clock, and (4) an analog signal\r
     input trigger\r
   This software emulator for SIMH implements all of the above with\r
   the exception of the external input trigger, which is arbitrarily\r
   wired to 10Hz.\r
\r
   Operation of this emulator is rather simplistic as compared to the\r
   actual device.  The register read and write routines are responsible\r
   for copying internal state from the simulated device to the operating\r
   program.  Clock state variables are altered in the write routine\r
   as well as the desired clock ticking rate.  Possible rates are\r
   given in the table below.\r
\r
    Rate                Bit 2   Bit 1\r
   100 kHz                0       0\r
   10 kHz                 0       1\r
   Line frequency         1       0\r
   External               1       1\r
\r
   I think SIMH would have a hard time actually keeping up with a 100\r
   kHz ticking rate.  I haven't tried this to verify, though.\r
\r
   The clock service routine (pclk_svc) is responsible for ticking\r
   the clock.  The routine does implement up/down, repeat vs.\r
   single-interrupt, and single clocking (maintenance).  The routine\r
   updates the internal state according to the options selected and\r
   signals interrupts when appropriate.\r
\r
   For a complete description of the device, please see DEC-11-HPWB-D\r
   KW11-P Programmable Real-Time Clock Manual.\r
\r
   ** Notes **\r
\r
   1. The device is disabled by default.\r
\r
   2. Use XXDP V2.5 test program ZKWBJ1.BIC; loads at 1000, starts at\r
      1100?  Seems to execute the first few tests correctly then waits\r
      for input from the console.  I don't have a description of how this\r
      diagnostic works and thus don't know how to proceed from that point.\r
\r
   3. The read and write routines don't do anything with odd address\r
      accesses.  The manual says that byte writes don't work.\r
\r
   4. RSTS can use this clock in place of the standard KW11-L line\r
      frequency clock.  In order to do this, use the DEFAULT response in\r
      the OPTION: dialog.  To the Preferred clock prompt answer "P".\r
      Then you have the option of line frequency "L" or some multiple of\r
      50 between 50 and 1000 to use the programmable portion of the clock.\r
\r
   5. This is really a Unibus peripheral and thus doesn't actually make\r
      sense within a J-11 system as there never was a Qbus version of\r
      this to the best of my knowledge.  However the OSs I have tried\r
      don't appear to exhibit any dissonance between this option and the\r
      processor/bus emulation.  I think the options that would make\r
      somewhat more sense in a Qbus environment the KWV11-C and/or KWV11-S.\r
      I don't know if any of the -11 OSs contained support for using\r
      these as the system clock, though.\r
*/\r
\r
#include "pdp11_defs.h"\r
\r
#define PCLKCSR_RDMASK  0100377                         /* readable */\r
#define PCLKCSR_WRMASK  0000137                         /* writeable */\r
\r
#define UNIT_V_LINE50HZ (UNIT_V_UF + 0)\r
#define UNIT_LINE50HZ   (1 << UNIT_V_LINE50HZ)\r
\r
/* CSR - 17772540 */\r
\r
#define CSR_V_FIX       5                               /* single tick */\r
#define CSR_V_UPDN      4                               /* down/up */\r
#define CSR_V_MODE      3                               /* single/repeat */\r
#define CSR_FIX         (1u << CSR_V_FIX)\r
#define CSR_UPDN        (1u << CSR_V_UPDN)\r
#define CSR_MODE        (1u << CSR_V_MODE)\r
#define CSR_V_RATE      1                               /* rate */\r
#define CSR_M_RATE      03\r
#define CSR_GETRATE(x)  (((x) >> CSR_V_RATE) & CSR_M_RATE)\r
\r
extern int32 int_req[IPL_HLVL];\r
\r
uint32 pclk_csr = 0;                                    /* control/status */\r
uint32 pclk_csb = 0;                                    /* count set buffer */\r
uint32 pclk_ctr = 0;                                    /* counter */\r
static uint32 rate[4] = { 100000, 10000, 60, 10 };      /* ticks per second */\r
static uint32 xtim[4] = { 10, 100, 16667, 100000 };     /* nominal time delay */\r
\r
DEVICE pclk_dev;\r
t_stat pclk_rd (int32 *data, int32 PA, int32 access);\r
t_stat pclk_wr (int32 data, int32 PA, int32 access);\r
t_stat pclk_svc (UNIT *uptr);\r
t_stat pclk_reset (DEVICE *dptr);\r
t_stat pclk_set_line (UNIT *uptr, int32 val, char *cptr, void *desc);\r
void pclk_tick (void);\r
\r
/* PCLK data structures\r
\r
   pclk_dev     PCLK device descriptor\r
   pclk_unit    PCLK unit descriptor\r
   pclk_reg     PCLK register list\r
*/\r
\r
DIB pclk_dib = {\r
    IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr,\r
    1, IVCL (PCLK), VEC_PCLK, { NULL }\r
    };\r
\r
UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) };\r
\r
REG pclk_reg[] = {\r
    { ORDATA (CSR, pclk_csr, 16) },\r
    { ORDATA (CSB, pclk_csb, 16) },\r
    { ORDATA (CNT, pclk_ctr, 16) },\r
    { FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },\r
    { FLDATA (OVFL, pclk_csr, CSR_V_ERR) },\r
    { FLDATA (DONE, pclk_csr, CSR_V_DONE) },\r
    { FLDATA (IE, pclk_csr, CSR_V_IE) },\r
    { FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },\r
    { FLDATA (MODE, pclk_csr, CSR_V_MODE) },\r
    { FLDATA (RUN, pclk_csr, CSR_V_GO) },\r
    { BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },\r
    { BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },\r
    { DRDATA (CURTIM, pclk_unit.wait, 32), REG_HRO },\r
    { ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },\r
    { ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },\r
    { NULL }\r
    };\r
\r
MTAB pclk_mod[] = {\r
    { UNIT_LINE50HZ, UNIT_LINE50HZ, "50 Hz", "50HZ", &pclk_set_line },\r
    { UNIT_LINE50HZ,             0, "60 Hz", "60HZ", &pclk_set_line },\r
    { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,\r
      NULL, &show_addr, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",\r
      &set_vec, &show_vec, NULL },\r
    { 0 }\r
    };\r
\r
DEVICE pclk_dev = {\r
    "PCLK", &pclk_unit, pclk_reg, pclk_mod,\r
    1, 0, 0, 0, 0, 0,\r
    NULL, NULL, &pclk_reset,\r
    NULL, NULL, NULL,\r
    &pclk_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS\r
    };\r
\r
/* Clock I/O address routines */\r
\r
t_stat pclk_rd (int32 *data, int32 PA, int32 access)\r
{\r
switch ((PA >> 1) & 03) {\r
\r
    case 00:                                            /* CSR */\r
        *data = pclk_csr & PCLKCSR_RDMASK;              /* return CSR */\r
        pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE);    /* clr err, done */\r
        CLR_INT (PCLK);                                 /* clr intr */\r
        break;\r
\r
    case 01:                                            /* buffer */\r
        *data = 0;                                      /* read only */\r
        break;\r
\r
    case 02:                                            /* counter */\r
        *data = pclk_ctr & DMASK;                       /* return counter */\r
        break;\r
        }\r
\r
return SCPE_OK;\r
}\r
\r
t_stat pclk_wr (int32 data, int32 PA, int32 access)\r
{\r
int32 old_csr = pclk_csr;\r
int32 rv;\r
\r
switch ((PA >> 1) & 03) {\r
\r
    case 00:                                            /* CSR */\r
        pclk_csr = data & PCLKCSR_WRMASK;               /* clear and write */\r
        CLR_INT (PCLK);                                 /* clr intr */\r
        rv = CSR_GETRATE (pclk_csr);                    /* new rate */\r
        pclk_unit.wait = xtim[rv];                      /* new delay */\r
        if ((pclk_csr & CSR_GO) == 0) {                 /* stopped? */\r
            sim_cancel (&pclk_unit);                    /* cancel */\r
            if (data & CSR_FIX) pclk_tick ();           /* fix? tick */\r
             }\r
        else if (((old_csr & CSR_GO) == 0) ||           /* run 0 -> 1? */\r
                 (rv != CSR_GETRATE (old_csr))) {       /* rate change? */\r
            sim_cancel (&pclk_unit);                    /* cancel */\r
            sim_activate (&pclk_unit,                   /* start clock */\r
                sim_rtcn_init (pclk_unit.wait, TMR_PCLK));\r
            }\r
        break;\r
\r
    case 01:                                            /* buffer */\r
        pclk_csb = pclk_ctr = data;                     /* store ctr */\r
        pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE);    /* clr err, done */\r
        CLR_INT (PCLK);                                 /* clr intr */\r
        break;\r
\r
    case 02:                                            /* counter */\r
        break;                                          /* read only */\r
        }\r
\r
return SCPE_OK;\r
}\r
\r
/* Clock tick (automatic or manual) */\r
\r
void pclk_tick (void)\r
{\r
if (pclk_csr & CSR_UPDN)                                /* up or down? */\r
    pclk_ctr = (pclk_ctr + 1) & DMASK;                  /* 1 = up */\r
else pclk_ctr = (pclk_ctr - 1) & DMASK;                 /* 0 = down */\r
if (pclk_ctr == 0) {                                    /* reached zero? */\r
    if (pclk_csr & CSR_DONE)                            /* done already set? */\r
        pclk_csr = pclk_csr | CSR_ERR;                  /* set error */\r
    else pclk_csr = pclk_csr | CSR_DONE;                /* else set done */\r
    if (pclk_csr & CSR_IE) SET_INT (PCLK);              /* if IE, set int */\r
    if (pclk_csr & CSR_MODE) pclk_ctr = pclk_csb;       /* if rpt, reload */\r
    else {\r
        pclk_csb = 0;                                   /* else clr ctr */\r
        pclk_csr = pclk_csr & ~CSR_GO;                  /* and clr go */\r
        }\r
    }\r
return;\r
}\r
\r
/* Clock service */\r
\r
t_stat pclk_svc (UNIT *uptr)\r
{\r
int32 rv;\r
\r
pclk_tick ();                                           /* tick clock */\r
if ((pclk_csr & CSR_GO) == 0) return SCPE_OK;           /* done? */\r
rv = CSR_GETRATE (pclk_csr);                            /* get rate */\r
sim_activate (&pclk_unit, sim_rtcn_calb (rate[rv], TMR_PCLK));\r
return SCPE_OK;\r
}\r
\r
/* Clock reset */\r
\r
t_stat pclk_reset (DEVICE *dptr)\r
{\r
pclk_csr = 0;                                           /* clear reg */\r
pclk_csb = 0;\r
pclk_ctr = 0;\r
CLR_INT (PCLK);                                         /* clear int */\r
sim_cancel (&pclk_unit);                                /* cancel */\r
pclk_unit.wait = xtim[0];                               /* reset delay */\r
return SCPE_OK;\r
}\r
\r
/* Set line frequency */\r
\r
t_stat pclk_set_line (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (val == UNIT_LINE50HZ) rate[2] = 50;\r
else rate[2] = 60;\r
return SCPE_OK;\r
}\r
Commit	Line	Data
196ba1fc PH	1	/* pdp11_pclk.c: KW11P programmable clock simulator\r
	2	\r
	3	Copyright (c) 1993-2008, Robert M Supnik\r
	4	Written by John Dundas, used with his gracious permission\r
	5	\r
	6	Permission is hereby granted, free of charge, to any person obtaining a\r
	7	copy of this software and associated documentation files (the "Software"),\r
	8	to deal in the Software without restriction, including without limitation\r
	9	the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
	10	and/or sell copies of the Software, and to permit persons to whom the\r
	11	Software is furnished to do so, subject to the following conditions:\r
	12	\r
	13	The above copyright notice and this permission notice shall be included in\r
	14	all copies or substantial portions of the Software.\r
	15	\r
	16	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
	17	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
	18	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r
	19	ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
	20	IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
	21	CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
	22	\r
	23	Except as contained in this notice, the name of Robert M Supnik shall not be\r
	24	used in advertising or otherwise to promote the sale, use or other dealings\r
	25	in this Software without prior written authorization from Robert M Supnik.\r
	26	\r
	27	pclk KW11P line frequency clock\r
	28	\r
	29	20-May-08 RMS Standardized clock delay at 1mips\r
	30	18-Jun-07 RMS Added UNIT_IDLE flag\r
	31	07-Jul-05 RMS Removed extraneous externs\r
	32	\r
	33	KW11-P Programmable Clock\r
	34	\r
	35	I/O Page Registers:\r
	36	\r
	37	CSR 17 772 540\r
	38	CSB 17 772 542\r
	39	CNT 17 772 544\r
	40	\r
	41	Vector: 0104\r
	42	\r
	43	Priority: BR6\r
	44	\r
	45	Theory of Operation \r
	46	\r
	47	A real KW11-P is built around the following major components:\r
	48	- 16-bit up/down counter\r
	49	- 16-bit count set buffer\r
	50	- 9-bit control and status register\r
	51	- clocks: crystal controlled (1) 100 kHz and (2) 10 kHz clocks,\r
	52	(3) a 50/60 Hz line frequency clock, and (4) an analog signal\r
	53	input trigger\r
	54	This software emulator for SIMH implements all of the above with\r
	55	the exception of the external input trigger, which is arbitrarily\r
	56	wired to 10Hz.\r
	57	\r
	58	Operation of this emulator is rather simplistic as compared to the\r
	59	actual device. The register read and write routines are responsible\r
	60	for copying internal state from the simulated device to the operating\r
	61	program. Clock state variables are altered in the write routine\r
	62	as well as the desired clock ticking rate. Possible rates are\r
	63	given in the table below.\r
	64	\r
65	Rate Bit 2 Bit 1\r
66	100 kHz 0 0\r
67	10 kHz 0 1\r
68	Line frequency 1 0\r
69	External 1 1\r
70	\r
71	I think SIMH would have a hard time actually keeping up with a 100\r
72	kHz ticking rate. I haven't tried this to verify, though.\r
73	\r
74	The clock service routine (pclk_svc) is responsible for ticking\r
75	the clock. The routine does implement up/down, repeat vs.\r
76	single-interrupt, and single clocking (maintenance). The routine\r
77	updates the internal state according to the options selected and\r
78	signals interrupts when appropriate.\r
79	\r
80	For a complete description of the device, please see DEC-11-HPWB-D\r
81	KW11-P Programmable Real-Time Clock Manual.\r
82	\r
83	Notes \r
84	\r
85	1. The device is disabled by default.\r
86	\r
87	2. Use XXDP V2.5 test program ZKWBJ1.BIC; loads at 1000, starts at\r
88	1100? Seems to execute the first few tests correctly then waits\r
89	for input from the console. I don't have a description of how this\r
90	diagnostic works and thus don't know how to proceed from that point.\r
91	\r
92	3. The read and write routines don't do anything with odd address\r
93	accesses. The manual says that byte writes don't work.\r
94	\r
95	4. RSTS can use this clock in place of the standard KW11-L line\r
96	frequency clock. In order to do this, use the DEFAULT response in\r
97	the OPTION: dialog. To the Preferred clock prompt answer "P".\r
98	Then you have the option of line frequency "L" or some multiple of\r
99	50 between 50 and 1000 to use the programmable portion of the clock.\r
100	\r
101	5. This is really a Unibus peripheral and thus doesn't actually make\r
102	sense within a J-11 system as there never was a Qbus version of\r
103	this to the best of my knowledge. However the OSs I have tried\r
104	don't appear to exhibit any dissonance between this option and the\r
105	processor/bus emulation. I think the options that would make\r
106	somewhat more sense in a Qbus environment the KWV11-C and/or KWV11-S.\r
107	I don't know if any of the -11 OSs contained support for using\r
108	these as the system clock, though.\r
109	*/\r
110	\r
111	#include "pdp11_defs.h"\r
112	\r
113	#define PCLKCSR_RDMASK 0100377 /* readable */\r
114	#define PCLKCSR_WRMASK 0000137 /* writeable */\r
115	\r
116	#define UNIT_V_LINE50HZ (UNIT_V_UF + 0)\r
117	#define UNIT_LINE50HZ (1 << UNIT_V_LINE50HZ)\r
118	\r
119	/* CSR - 17772540 */\r
120	\r
121	#define CSR_V_FIX 5 /* single tick */\r
122	#define CSR_V_UPDN 4 /* down/up */\r
123	#define CSR_V_MODE 3 /* single/repeat */\r
124	#define CSR_FIX (1u << CSR_V_FIX)\r
125	#define CSR_UPDN (1u << CSR_V_UPDN)\r
126	#define CSR_MODE (1u << CSR_V_MODE)\r
127	#define CSR_V_RATE 1 /* rate */\r
128	#define CSR_M_RATE 03\r
129	#define CSR_GETRATE(x) (((x) >> CSR_V_RATE) & CSR_M_RATE)\r
130	\r
131	extern int32 int_req[IPL_HLVL];\r
132	\r
133	uint32 pclk_csr = 0; /* control/status */\r
134	uint32 pclk_csb = 0; /* count set buffer */\r
135	uint32 pclk_ctr = 0; /* counter */\r
136	static uint32 rate[4] = { 100000, 10000, 60, 10 }; /* ticks per second */\r
137	static uint32 xtim[4] = { 10, 100, 16667, 100000 }; /* nominal time delay */\r
138	\r
139	DEVICE pclk_dev;\r
140	t_stat pclk_rd (int32 *data, int32 PA, int32 access);\r
141	t_stat pclk_wr (int32 data, int32 PA, int32 access);\r
142	t_stat pclk_svc (UNIT *uptr);\r
143	t_stat pclk_reset (DEVICE *dptr);\r
144	t_stat pclk_set_line (UNIT uptr, int32 val, char cptr, void *desc);\r
145	void pclk_tick (void);\r
146	\r
147	/* PCLK data structures\r
148	\r
149	pclk_dev PCLK device descriptor\r
150	pclk_unit PCLK unit descriptor\r
151	pclk_reg PCLK register list\r
152	*/\r
153	\r
154	DIB pclk_dib = {\r
155	IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr,\r
156	1, IVCL (PCLK), VEC_PCLK, { NULL }\r
157	};\r
158	\r
159	UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) };\r
160	\r
161	REG pclk_reg[] = {\r
162	{ ORDATA (CSR, pclk_csr, 16) },\r
163	{ ORDATA (CSB, pclk_csb, 16) },\r
164	{ ORDATA (CNT, pclk_ctr, 16) },\r
165	{ FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },\r
166	{ FLDATA (OVFL, pclk_csr, CSR_V_ERR) },\r
167	{ FLDATA (DONE, pclk_csr, CSR_V_DONE) },\r
168	{ FLDATA (IE, pclk_csr, CSR_V_IE) },\r
169	{ FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },\r
170	{ FLDATA (MODE, pclk_csr, CSR_V_MODE) },\r
171	{ FLDATA (RUN, pclk_csr, CSR_V_GO) },\r
172	{ BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },\r
173	{ BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },\r
174	{ DRDATA (CURTIM, pclk_unit.wait, 32), REG_HRO },\r
175	{ ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },\r
176	{ ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },\r
177	{ NULL }\r
178	};\r
179	\r
180	MTAB pclk_mod[] = {\r
181	{ UNIT_LINE50HZ, UNIT_LINE50HZ, "50 Hz", "50HZ", &pclk_set_line },\r
182	{ UNIT_LINE50HZ, 0, "60 Hz", "60HZ", &pclk_set_line },\r
183	{ MTAB_XTD\|MTAB_VDV, 0, "ADDRESS", NULL,\r
184	NULL, &show_addr, NULL },\r
185	{ MTAB_XTD\|MTAB_VDV, 0, "VECTOR", "VECTOR",\r
186	&set_vec, &show_vec, NULL },\r
187	{ 0 }\r
188	};\r
189	\r
190	DEVICE pclk_dev = {\r
191	"PCLK", &pclk_unit, pclk_reg, pclk_mod,\r
192	1, 0, 0, 0, 0, 0,\r
193	NULL, NULL, &pclk_reset,\r
194	NULL, NULL, NULL,\r
195	&pclk_dib, DEV_DISABLE \| DEV_DIS \| DEV_UBUS \| DEV_QBUS\r
196	};\r
197	\r
198	/* Clock I/O address routines */\r
199	\r
200	t_stat pclk_rd (int32 *data, int32 PA, int32 access)\r
201	{\r
202	switch ((PA >> 1) & 03) {\r
203	\r
204	case 00: /* CSR */\r
205	data = pclk_csr & PCLKCSR_RDMASK; / return CSR */\r
206	pclk_csr = pclk_csr & ~(CSR_ERR \| CSR_DONE); /* clr err, done */\r
207	CLR_INT (PCLK); /* clr intr */\r
208	break;\r
209	\r
210	case 01: /* buffer */\r
211	data = 0; / read only */\r
212	break;\r
213	\r
214	case 02: /* counter */\r
215	data = pclk_ctr & DMASK; / return counter */\r
216	break;\r
217	}\r
218	\r
219	return SCPE_OK;\r
220	}\r
221	\r
222	t_stat pclk_wr (int32 data, int32 PA, int32 access)\r
223	{\r
224	int32 old_csr = pclk_csr;\r
225	int32 rv;\r
226	\r
227	switch ((PA >> 1) & 03) {\r
228	\r
229	case 00: /* CSR */\r
230	pclk_csr = data & PCLKCSR_WRMASK; /* clear and write */\r
231	CLR_INT (PCLK); /* clr intr */\r
232	rv = CSR_GETRATE (pclk_csr); /* new rate */\r
233	pclk_unit.wait = xtim[rv]; /* new delay */\r
234	if ((pclk_csr & CSR_GO) == 0) { /* stopped? */\r
235	sim_cancel (&pclk_unit); /* cancel */\r
236	if (data & CSR_FIX) pclk_tick (); /* fix? tick */\r
237	}\r
238	else if (((old_csr & CSR_GO) == 0) \|\| /* run 0 -> 1? */\r
239	(rv != CSR_GETRATE (old_csr))) { /* rate change? */\r
240	sim_cancel (&pclk_unit); /* cancel */\r
241	sim_activate (&pclk_unit, /* start clock */\r
242	sim_rtcn_init (pclk_unit.wait, TMR_PCLK));\r
243	}\r
244	break;\r
245	\r
246	case 01: /* buffer */\r
247	pclk_csb = pclk_ctr = data; /* store ctr */\r
248	pclk_csr = pclk_csr & ~(CSR_ERR \| CSR_DONE); /* clr err, done */\r
249	CLR_INT (PCLK); /* clr intr */\r
250	break;\r
251	\r
252	case 02: /* counter */\r
253	break; /* read only */\r
254	}\r
255	\r
256	return SCPE_OK;\r
257	}\r
258	\r
259	/* Clock tick (automatic or manual) */\r
260	\r
261	void pclk_tick (void)\r
262	{\r
263	if (pclk_csr & CSR_UPDN) /* up or down? */\r
264	pclk_ctr = (pclk_ctr + 1) & DMASK; /* 1 = up */\r
265	else pclk_ctr = (pclk_ctr - 1) & DMASK; /* 0 = down */\r
266	if (pclk_ctr == 0) { /* reached zero? */\r
267	if (pclk_csr & CSR_DONE) /* done already set? */\r
268	pclk_csr = pclk_csr \| CSR_ERR; /* set error */\r
269	else pclk_csr = pclk_csr \| CSR_DONE; /* else set done */\r
270	if (pclk_csr & CSR_IE) SET_INT (PCLK); /* if IE, set int */\r
271	if (pclk_csr & CSR_MODE) pclk_ctr = pclk_csb; /* if rpt, reload */\r
272	else {\r
273	pclk_csb = 0; /* else clr ctr */\r
274	pclk_csr = pclk_csr & ~CSR_GO; /* and clr go */\r
275	}\r
276	}\r
277	return;\r
278	}\r
279	\r
280	/* Clock service */\r
281	\r
282	t_stat pclk_svc (UNIT *uptr)\r
283	{\r
284	int32 rv;\r
285	\r
286	pclk_tick (); /* tick clock */\r
287	if ((pclk_csr & CSR_GO) == 0) return SCPE_OK; /* done? */\r
288	rv = CSR_GETRATE (pclk_csr); /* get rate */\r
289	sim_activate (&pclk_unit, sim_rtcn_calb (rate[rv], TMR_PCLK));\r
290	return SCPE_OK;\r
291	}\r
292	\r
293	/* Clock reset */\r
294	\r
295	t_stat pclk_reset (DEVICE *dptr)\r
296	{\r
297	pclk_csr = 0; /* clear reg */\r
298	pclk_csb = 0;\r
299	pclk_ctr = 0;\r
300	CLR_INT (PCLK); /* clear int */\r
301	sim_cancel (&pclk_unit); /* cancel */\r
302	pclk_unit.wait = xtim[0]; /* reset delay */\r
303	return SCPE_OK;\r
304	}\r
305	\r
306	/* Set line frequency */\r
307	\r
308	t_stat pclk_set_line (UNIT uptr, int32 val, char cptr, void *desc)\r
309	{\r
310	if (val == UNIT_LINE50HZ) rate[2] = 50;\r
311	else rate[2] = 60;\r
312	return SCPE_OK;\r
313	}\r