[simh.git] / PDP11 / pdp11_uqssp.h

/* pdp11_uqssp.h: Unibus/Qbus storage systems port definitions file\r
\r
   Copyright (c) 2001-2005, Robert M Supnik\r
   Derived from work by Stephen F. Shirron\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   30-Aug-02    RMS     Added TMSCP support\r
*/\r
\r
#ifndef _PDP11_UQSSP_H_\r
#define _PDP11_UQSSP_H_ 0\r
\r
/* IP register - initialization and polling\r
\r
   read - controller polls command queue\r
   write - controller re-initializes\r
*/\r
\r
/* SA register - status, address, and purge\r
\r
   read - data and error information\r
   write - host startup information, purge complete\r
*/\r
\r
#define SA_ER           0x8000                          /* error */\r
#define SA_S4           0x4000                          /* init step 4 */\r
#define SA_S3           0x2000                          /* init step 3 */\r
#define SA_S2           0x1000                          /* init step 2 */\r
#define SA_S1           0x0800                          /* init step 1 */\r
\r
/* Init step 1, controller to host */\r
\r
#define SA_S1C_NV       0x0400                          /* fixed vec NI */\r
#define SA_S1C_Q22      0x0200                          /* Q22 device */\r
#define SA_S1C_DI       0x0100                          /* ext diags */\r
#define SA_S1C_OD       0x0080                          /* odd addrs NI */\r
#define SA_S1C_MP       0x0040                          /* mapping */\r
#define SA_S1C_SM       0x0020                          /* spec fncs NI */\r
#define SA_S1C_CN       0x0010                          /* node name NI */\r
\r
/* Init step 1, host to controller */\r
\r
#define SA_S1H_VL       0x8000                          /* valid */\r
#define SA_S1H_WR       0x4000                          /* wrap mode */\r
#define SA_S1H_V_CQ     11                              /* cmd q len */\r
#define SA_S1H_M_CQ     0x7\r
#define SA_S1H_V_RQ     8                               /* resp q len */\r
#define SA_S1H_M_RQ     0x7\r
#define SA_S1H_IE       0x0080                          /* int enb */\r
#define SA_S1H_VEC      0x007F                          /* vector */\r
#define SA_S1H_CQ(x)    (1 << (((x) >> SA_S1H_V_CQ) & SA_S1H_M_CQ))\r
#define SA_S1H_RQ(x)    (1 << (((x) >> SA_S1H_V_RQ) & SA_S1H_M_RQ))\r
\r
/* Init step 2, controller to host */\r
\r
#define SA_S2C_PT       0x0000                          /* port type */\r
#define SA_S2C_V_EC     8                               /* info to echo */\r
#define SA_S2C_M_EC     0xFF\r
#define SA_S2C_EC(x)    (((x) >> SA_S2C_V_EC) & SA_S2C_M_EC)\r
\r
/* Init step 2, host to controller */\r
\r
#define SA_S2H_CLO      0xFFFE                          /* comm addr lo */\r
#define SA_S2H_PI       0x0001                          /* adp prg int */\r
\r
/* Init step 3, controller to host */\r
\r
#define SA_S3C_V_EC     0                               /* info to echo */\r
#define SA_S3C_M_EC     0xFF\r
#define SA_S3C_EC(x)    (((x) >> SA_S3C_V_EC) & SA_S3C_M_EC)\r
\r
/* Init step 3, host to controller */\r
\r
#define SA_S3H_PP       0x8000                          /* purge, poll test */\r
#define SA_S3H_CHI      0x7FFF                          /* comm addr hi */\r
\r
/* Init step 4, controller to host */\r
\r
#define SA_S4C_V_MOD    4                               /* adapter # */\r
#define SA_S4C_V_VER    0                               /* version # */\r
\r
/* Init step 4, host to controller */\r
\r
#define SA_S4H_CS       0x0400                          /* host scrpad NI */\r
#define SA_S4H_NN       0x0200                          /* snd node name NI */\r
#define SA_S4H_SF       0x0100                          /* spec fnc NI */\r
#define SA_S4H_LF       0x0002                          /* send last fail */\r
#define SA_S4H_GO       0x0001                          /* go */\r
\r
/* Fatal error codes (generic through 32) */\r
\r
#define PE_PRE          1                               /* packet read err */\r
#define PE_PWE          2                               /* packet write err */\r
#define PE_QRE          6                               /* queue read err */\r
#define PE_QWE          7                               /* queue write err */\r
#define PE_HAT          9                               /* host access tmo */\r
#define PE_ICI          14                              /* inv conn ident */\r
#define PE_PIE          20                              /* prot incompat */\r
#define PE_PPF          21                              /* prg/poll err */\r
#define PE_MRE          22                              /* map reg rd err */\r
#define PE_T11          475                             /* T11 err NI */\r
#define PE_SND          476                             /* SND err NI */\r
#define PE_RCV          477                             /* RCV err NI */\r
#define PE_NSR          478                             /* no such rsrc */\r
\r
/* Comm region offsets */\r
\r
#define SA_COMM_QQ      -8                              /* unused */\r
#define SA_COMM_PI      -6                              /* purge int */\r
#define SA_COMM_CI      -4                              /* cmd int */\r
#define SA_COMM_RI      -2                              /* resp int */\r
#define SA_COMM_MAX     ((4 << SA_S1H_M_CQ) + (4 << SA_S1H_M_RQ) - SA_COMM_QQ)\r
\r
/* Command/response rings */\r
\r
struct uq_ring {\r
    int32               ioff;                           /* intr offset */\r
    uint32              ba;                             /* base addr */\r
    uint32              lnt;                            /* size in bytes */\r
    uint32              idx;                            /* current index */\r
    };\r
\r
/* Ring descriptor entry */\r
\r
#define UQ_DESC_OWN     0x80000000                      /* ownership */\r
#define UQ_DESC_F       0x40000000                      /* flag */\r
#define UQ_ADDR         0x003FFFFE                      /* addr, word aligned */\r
\r
/* Packet header */\r
\r
#define UQ_HDR_OFF      -4                              /* offset */\r
\r
#define UQ_HLNT         0                               /* length */\r
#define UQ_HCTC         1                               /* credits, type, CID */\r
\r
#define UQ_HCTC_V_CR    0                               /* credits */\r
#define UQ_HCTC_M_CR    0xF\r
#define UQ_HCTC_V_TYP   4                               /* type */\r
#define UQ_HCTC_M_TYP   0xF\r
#define  UQ_TYP_SEQ     0                               /* sequential */\r
#define  UQ_TYP_DAT     1                               /* datagram */\r
#define UQ_HCTC_V_CID   8                               /* conn ID */\r
#define UQ_HCTC_M_CID   0xFF\r
#define  UQ_CID_MSCP    0                               /* MSCP */\r
#define  UQ_CID_TMSCP   1                               /* TMSCP */\r
#define  UQ_CID_DUP     2                               /* DUP */\r
#define  UQ_CID_DIAG    0xFF                            /* diagnostic */\r
\r
#endif\r
Commit	Line	Data
196ba1fc PH	1	/* pdp11_uqssp.h: Unibus/Qbus storage systems port definitions file\r
	2	\r
	3	Copyright (c) 2001-2005, Robert M Supnik\r
	4	Derived from work by Stephen F. Shirron\r
	5	\r
	6	Permission is hereby granted, free of charge, to any person obtaining a\r
	7	copy of this software and associated documentation files (the "Software"),\r
	8	to deal in the Software without restriction, including without limitation\r
	9	the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
	10	and/or sell copies of the Software, and to permit persons to whom the\r
	11	Software is furnished to do so, subject to the following conditions:\r
	12	\r
	13	The above copyright notice and this permission notice shall be included in\r
	14	all copies or substantial portions of the Software.\r
	15	\r
	16	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
	17	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
	18	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r
	19	ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
	20	IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
	21	CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
	22	\r
	23	Except as contained in this notice, the name of Robert M Supnik shall not be\r
	24	used in advertising or otherwise to promote the sale, use or other dealings\r
	25	in this Software without prior written authorization from Robert M Supnik.\r
	26	\r
	27	30-Aug-02 RMS Added TMSCP support\r
	28	*/\r
	29	\r
	30	#ifndef _PDP11_UQSSP_H_\r
	31	#define _PDP11_UQSSP_H_ 0\r
	32	\r
	33	/* IP register - initialization and polling\r
	34	\r
	35	read - controller polls command queue\r
	36	write - controller re-initializes\r
	37	*/\r
	38	\r
	39	/* SA register - status, address, and purge\r
	40	\r
	41	read - data and error information\r
	42	write - host startup information, purge complete\r
	43	*/\r
	44	\r
	45	#define SA_ER 0x8000 /* error */\r
	46	#define SA_S4 0x4000 /* init step 4 */\r
	47	#define SA_S3 0x2000 /* init step 3 */\r
	48	#define SA_S2 0x1000 /* init step 2 */\r
	49	#define SA_S1 0x0800 /* init step 1 */\r
	50	\r
	51	/* Init step 1, controller to host */\r
	52	\r
	53	#define SA_S1C_NV 0x0400 /* fixed vec NI */\r
	54	#define SA_S1C_Q22 0x0200 /* Q22 device */\r
	55	#define SA_S1C_DI 0x0100 /* ext diags */\r
	56	#define SA_S1C_OD 0x0080 /* odd addrs NI */\r
	57	#define SA_S1C_MP 0x0040 /* mapping */\r
	58	#define SA_S1C_SM 0x0020 /* spec fncs NI */\r
	59	#define SA_S1C_CN 0x0010 /* node name NI */\r
	60	\r
	61	/* Init step 1, host to controller */\r
	62	\r
	63	#define SA_S1H_VL 0x8000 /* valid */\r
	64	#define SA_S1H_WR 0x4000 /* wrap mode */\r
65	#define SA_S1H_V_CQ 11 /* cmd q len */\r
66	#define SA_S1H_M_CQ 0x7\r
67	#define SA_S1H_V_RQ 8 /* resp q len */\r
68	#define SA_S1H_M_RQ 0x7\r
69	#define SA_S1H_IE 0x0080 /* int enb */\r
70	#define SA_S1H_VEC 0x007F /* vector */\r
71	#define SA_S1H_CQ(x) (1 << (((x) >> SA_S1H_V_CQ) & SA_S1H_M_CQ))\r
72	#define SA_S1H_RQ(x) (1 << (((x) >> SA_S1H_V_RQ) & SA_S1H_M_RQ))\r
73	\r
74	/* Init step 2, controller to host */\r
75	\r
76	#define SA_S2C_PT 0x0000 /* port type */\r
77	#define SA_S2C_V_EC 8 /* info to echo */\r
78	#define SA_S2C_M_EC 0xFF\r
79	#define SA_S2C_EC(x) (((x) >> SA_S2C_V_EC) & SA_S2C_M_EC)\r
80	\r
81	/* Init step 2, host to controller */\r
82	\r
83	#define SA_S2H_CLO 0xFFFE /* comm addr lo */\r
84	#define SA_S2H_PI 0x0001 /* adp prg int */\r
85	\r
86	/* Init step 3, controller to host */\r
87	\r
88	#define SA_S3C_V_EC 0 /* info to echo */\r
89	#define SA_S3C_M_EC 0xFF\r
90	#define SA_S3C_EC(x) (((x) >> SA_S3C_V_EC) & SA_S3C_M_EC)\r
91	\r
92	/* Init step 3, host to controller */\r
93	\r
94	#define SA_S3H_PP 0x8000 /* purge, poll test */\r
95	#define SA_S3H_CHI 0x7FFF /* comm addr hi */\r
96	\r
97	/* Init step 4, controller to host */\r
98	\r
99	#define SA_S4C_V_MOD 4 /* adapter # */\r
100	#define SA_S4C_V_VER 0 /* version # */\r
101	\r
102	/* Init step 4, host to controller */\r
103	\r
104	#define SA_S4H_CS 0x0400 /* host scrpad NI */\r
105	#define SA_S4H_NN 0x0200 /* snd node name NI */\r
106	#define SA_S4H_SF 0x0100 /* spec fnc NI */\r
107	#define SA_S4H_LF 0x0002 /* send last fail */\r
108	#define SA_S4H_GO 0x0001 /* go */\r
109	\r
110	/* Fatal error codes (generic through 32) */\r
111	\r
112	#define PE_PRE 1 /* packet read err */\r
113	#define PE_PWE 2 /* packet write err */\r
114	#define PE_QRE 6 /* queue read err */\r
115	#define PE_QWE 7 /* queue write err */\r
116	#define PE_HAT 9 /* host access tmo */\r
117	#define PE_ICI 14 /* inv conn ident */\r
118	#define PE_PIE 20 /* prot incompat */\r
119	#define PE_PPF 21 /* prg/poll err */\r
120	#define PE_MRE 22 /* map reg rd err */\r
121	#define PE_T11 475 /* T11 err NI */\r
122	#define PE_SND 476 /* SND err NI */\r
123	#define PE_RCV 477 /* RCV err NI */\r
124	#define PE_NSR 478 /* no such rsrc */\r
125	\r
126	/* Comm region offsets */\r
127	\r
128	#define SA_COMM_QQ -8 /* unused */\r
129	#define SA_COMM_PI -6 /* purge int */\r
130	#define SA_COMM_CI -4 /* cmd int */\r
131	#define SA_COMM_RI -2 /* resp int */\r
132	#define SA_COMM_MAX ((4 << SA_S1H_M_CQ) + (4 << SA_S1H_M_RQ) - SA_COMM_QQ)\r
133	\r
134	/* Command/response rings */\r
135	\r
136	struct uq_ring {\r
137	int32 ioff; /* intr offset */\r
138	uint32 ba; /* base addr */\r
139	uint32 lnt; /* size in bytes */\r
140	uint32 idx; /* current index */\r
141	};\r
142	\r
143	/* Ring descriptor entry */\r
144	\r
145	#define UQ_DESC_OWN 0x80000000 /* ownership */\r
146	#define UQ_DESC_F 0x40000000 /* flag */\r
147	#define UQ_ADDR 0x003FFFFE /* addr, word aligned */\r
148	\r
149	/* Packet header */\r
150	\r
151	#define UQ_HDR_OFF -4 /* offset */\r
152	\r
153	#define UQ_HLNT 0 /* length */\r
154	#define UQ_HCTC 1 /* credits, type, CID */\r
155	\r
156	#define UQ_HCTC_V_CR 0 /* credits */\r
157	#define UQ_HCTC_M_CR 0xF\r
158	#define UQ_HCTC_V_TYP 4 /* type */\r
159	#define UQ_HCTC_M_TYP 0xF\r
160	#define UQ_TYP_SEQ 0 /* sequential */\r
161	#define UQ_TYP_DAT 1 /* datagram */\r
162	#define UQ_HCTC_V_CID 8 /* conn ID */\r
163	#define UQ_HCTC_M_CID 0xFF\r
164	#define UQ_CID_MSCP 0 /* MSCP */\r
165	#define UQ_CID_TMSCP 1 /* TMSCP */\r
166	#define UQ_CID_DUP 2 /* DUP */\r
167	#define UQ_CID_DIAG 0xFF /* diagnostic */\r
168	\r
169	#endif\r