First Commit of my working state

[simh.git] / PDP8 / pdp8_clk.c

/* pdp8_clk.c: PDP-8 real-time clock simulator\r
\r
   Copyright (c) 1993-2007, Robert M Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   clk          real time clock\r
\r
   18-Jun-07    RMS     Added UNIT_IDLE flag\r
   01-Mar-03    RMS     Aded SET/SHOW CLK FREQ support\r
   04-Oct-02    RMS     Added DIB, device number support\r
   30-Dec-01    RMS     Removed for generalized timers\r
   05-Sep-01    RMS     Added terminal multiplexor support\r
   17-Jul-01    RMS     Moved function prototype\r
   05-Mar-01    RMS     Added clock calibration support\r
\r
   Note: includes the IOT's for both the PDP-8/E and PDP-8/A clocks\r
*/\r
\r
#include "pdp8_defs.h"\r
\r
extern int32 int_req, int_enable, dev_done, stop_inst;\r
\r
int32 clk_tps = 60;                                     /* ticks/second */\r
int32 tmxr_poll = 16000;                                /* term mux poll */\r
\r
int32 clk (int32 IR, int32 AC);\r
t_stat clk_svc (UNIT *uptr);\r
t_stat clk_reset (DEVICE *dptr);\r
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);\r
\r
/* CLK data structures\r
\r
   clk_dev      CLK device descriptor\r
   clk_unit     CLK unit descriptor\r
   clk_reg      CLK register list\r
*/\r
\r
DIB clk_dib = { DEV_CLK, 1, { &clk } };\r
\r
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 16000 };\r
\r
REG clk_reg[] = {\r
    { FLDATA (DONE, dev_done, INT_V_CLK) },\r
    { FLDATA (ENABLE, int_enable, INT_V_CLK) },\r
    { FLDATA (INT, int_req, INT_V_CLK) },\r
    { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },\r
    { DRDATA (TPS, clk_tps, 8), PV_LEFT + REG_HRO },\r
    { NULL }\r
    };\r
\r
MTAB clk_mod[] = {\r
    { MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",\r
      &clk_set_freq, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",\r
      &clk_set_freq, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,\r
      NULL, &clk_show_freq, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev },\r
    { 0 }\r
    };\r
\r
DEVICE clk_dev = {\r
    "CLK", &clk_unit, clk_reg, clk_mod,\r
    1, 0, 0, 0, 0, 0,\r
    NULL, NULL, &clk_reset,\r
    NULL, NULL, NULL,\r
    &clk_dib, 0\r
    };\r
\r
/* IOT routine\r
\r
   IOT's 6131-6133 are the PDP-8/E clock\r
   IOT's 6135-6137 are the PDP-8/A clock\r
*/\r
\r
int32 clk (int32 IR, int32 AC)\r
{\r
switch (IR & 07) {                                      /* decode IR<9:11> */\r
\r
    case 1:                                             /* CLEI */\r
        int_enable = int_enable | INT_CLK;              /* enable clk ints */\r
        int_req = INT_UPDATE;                           /* update interrupts */\r
        return AC;\r
\r
    case 2:                                             /* CLDI */\r
        int_enable = int_enable & ~INT_CLK;             /* disable clk ints */\r
        int_req = int_req & ~INT_CLK;                   /* update interrupts */\r
        return AC;\r
\r
    case 3:                                             /* CLSC */\r
        if (dev_done & INT_CLK) {                       /* flag set? */\r
            dev_done = dev_done & ~INT_CLK;             /* clear flag */\r
            int_req = int_req & ~INT_CLK;               /* clear int req */\r
            return IOT_SKP + AC;\r
            }\r
        return AC;\r
\r
    case 5:                                             /* CLLE */\r
        if (AC & 1) int_enable = int_enable | INT_CLK;  /* test AC<11> */\r
        else int_enable = int_enable & ~INT_CLK;\r
        int_req = INT_UPDATE;                           /* update interrupts */\r
        return AC;\r
\r
    case 6:                                             /* CLCL */\r
        dev_done = dev_done & ~INT_CLK;                 /* clear flag */\r
        int_req = int_req & ~INT_CLK;                   /* clear int req */\r
        return AC;\r
\r
    case 7:                                             /* CLSK */\r
        return (dev_done & INT_CLK)? IOT_SKP + AC: AC;\r
\r
    default:\r
        return (stop_inst << IOT_V_REASON) + AC;\r
        }                                               /* end switch */\r
}\r
\r
/* Unit service */\r
\r
t_stat clk_svc (UNIT *uptr)\r
{\r
int32 t;\r
\r
dev_done = dev_done | INT_CLK;                          /* set done */\r
int_req = INT_UPDATE;                                   /* update interrupts */\r
t = sim_rtcn_calb (clk_tps, TMR_CLK);                   /* calibrate clock */\r
sim_activate (&clk_unit, t);                            /* reactivate unit */\r
tmxr_poll = t;                                          /* set mux poll */\r
return SCPE_OK;\r
}\r
\r
/* Reset routine */\r
\r
t_stat clk_reset (DEVICE *dptr)\r
{\r
int32 t;\r
\r
dev_done = dev_done & ~INT_CLK;                         /* clear done, int */\r
int_req = int_req & ~INT_CLK;\r
int_enable = int_enable & ~INT_CLK;                     /* clear enable */\r
t = sim_rtcn_init (clk_unit.wait, TMR_CLK);\r
sim_activate_abs (&clk_unit, t);                        /* activate unit */\r
tmxr_poll = t;\r
return SCPE_OK;\r
}\r
\r
/* Set frequency */\r
\r
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (cptr) return SCPE_ARG;\r
if ((val != 50) && (val != 60)) return SCPE_IERR;\r
clk_tps = val;\r
return SCPE_OK;\r
}\r
\r
/* Show frequency */\r
\r
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)\r
{\r
fprintf (st, (clk_tps == 50)? "50Hz": "60Hz");\r
return SCPE_OK;\r
}\r