[simh.git] / PDP8 / pdp8_df.c

/* pdp8_df.c: DF32 fixed head disk simulator\r
\r
   Copyright (c) 1993-2006, Robert M Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   df           DF32 fixed head disk\r
\r
   15-May-06    RMS     Fixed bug in autosize attach (reported by Dave Gesswein)\r
   07-Jan-06    RMS     Fixed unaligned register access bug (found by Doug Carman)\r
   04-Jan-04    RMS     Changed sim_fsize calling sequence\r
   26-Oct-03    RMS     Cleaned up buffer copy code\r
   26-Jul-03    RMS     Fixed bug in set size routine\r
   14-Mar-03    RMS     Fixed variable platter interaction with save/restore\r
   03-Mar-03    RMS     Fixed autosizing\r
   02-Feb-03    RMS     Added variable platter and autosizing support\r
   04-Oct-02    RMS     Added DIBs, device number support\r
   28-Nov-01    RMS     Added RL8A support\r
   25-Apr-01    RMS     Added device enable/disable support\r
\r
   The DF32 is a head-per-track disk.  It uses the three cycle data break\r
   facility.  To minimize overhead, the entire DF32 is buffered in memory.\r
\r
   Two timing parameters are provided:\r
\r
   df_time      Interword timing, must be non-zero\r
   df_burst     Burst mode, if 0, DMA occurs cycle by cycle; otherwise,\r
                DMA occurs in a burst\r
*/\r
\r
#include "pdp8_defs.h"\r
#include <math.h>\r
\r
#define UNIT_V_AUTO     (UNIT_V_UF + 0)                 /* autosize */\r
#define UNIT_V_PLAT     (UNIT_V_UF + 1)                 /* #platters - 1 */\r
#define UNIT_M_PLAT     03\r
#define UNIT_PLAT       (UNIT_M_PLAT << UNIT_V_PLAT)\r
#define UNIT_GETP(x)    ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)\r
#define UNIT_AUTO       (1 << UNIT_V_AUTO)\r
#define UNIT_PLAT       (UNIT_M_PLAT << UNIT_V_PLAT)\r
\r
/* Constants */\r
\r
#define DF_NUMWD        2048                            /* words/track */\r
#define DF_NUMTR        16                              /* tracks/disk */\r
#define DF_DKSIZE       (DF_NUMTR * DF_NUMWD)           /* words/disk */\r
#define DF_NUMDK        4                               /* disks/controller */\r
#define DF_WC           07750                           /* word count */\r
#define DF_MA           07751                           /* mem address */\r
#define DF_WMASK        (DF_NUMWD - 1)                  /* word mask */\r
\r
/* Parameters in the unit descriptor */\r
\r
#define FUNC            u4                              /* function */\r
#define DF_READ         2                               /* read */\r
#define DF_WRITE        4                               /* write */\r
\r
/* Status register */\r
\r
#define DFS_PCA         04000                           /* photocell status */\r
#define DFS_DEX         03700                           /* disk addr extension */\r
#define DFS_MEX         00070                           /* mem addr extension */\r
#define DFS_DRL         00004                           /* data late error */\r
#define DFS_WLS         00002                           /* write lock error */\r
#define DFS_NXD         00002                           /* non-existent disk */\r
#define DFS_PER         00001                           /* parity error */\r
#define DFS_ERR         (DFS_DRL | DFS_WLS | DFS_PER)\r
#define DFS_V_DEX       6\r
#define DFS_V_MEX       3\r
\r
#define GET_MEX(x)      (((x) & DFS_MEX) << (12 - DFS_V_MEX))\r
#define GET_DEX(x)      (((x) & DFS_DEX) << (12 - DFS_V_DEX))\r
#define GET_POS(x)      ((int) fmod (sim_gtime() / ((double) (x)), \\r
                        ((double) DF_NUMWD)))\r
#define UPDATE_PCELL    if (GET_POS (df_time) < 6) df_sta = df_sta | DFS_PCA; \\r
                        else df_sta = df_sta & ~DFS_PCA\r
\r
extern uint16 M[];\r
extern int32 int_req, stop_inst;\r
extern UNIT cpu_unit;\r
\r
int32 df_sta = 0;                                       /* status register */\r
int32 df_da = 0;                                        /* disk address */\r
int32 df_done = 0;                                      /* done flag */\r
int32 df_wlk = 0;                                       /* write lock */\r
int32 df_time = 10;                                     /* inter-word time */\r
int32 df_burst = 1;                                     /* burst mode flag */\r
int32 df_stopioe = 1;                                   /* stop on error */\r
\r
DEVICE df_dev;\r
int32 df60 (int32 IR, int32 AC);\r
int32 df61 (int32 IR, int32 AC);\r
int32 df62 (int32 IR, int32 AC);\r
t_stat df_svc (UNIT *uptr);\r
t_stat pcell_svc (UNIT *uptr);\r
t_stat df_reset (DEVICE *dptr);\r
t_stat df_boot (int32 unitno, DEVICE *dptr);\r
t_stat df_attach (UNIT *uptr, char *cptr);\r
t_stat df_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);\r
\r
/* DF32 data structures\r
\r
   df_dev       RF device descriptor\r
   df_unit      RF unit descriptor\r
   pcell_unit   photocell timing unit (orphan)\r
   df_reg       RF register list\r
*/\r
\r
DIB df_dib = { DEV_DF, 3, { &df60, &df61, &df62 } };\r
\r
UNIT df_unit = {\r
    UDATA (&df_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,\r
		   DF_DKSIZE)\r
    };\r
\r
REG df_reg[] = {\r
    { ORDATA (STA, df_sta, 12) },\r
    { ORDATA (DA, df_da, 12) },\r
    { ORDATA (WC, M[DF_WC], 12), REG_FIT },\r
    { ORDATA (MA, M[DF_MA], 12), REG_FIT },\r
    { FLDATA (DONE, df_done, 0) },\r
    { FLDATA (INT, int_req, INT_V_DF) },\r
    { ORDATA (WLS, df_wlk, 8) },\r
    { DRDATA (TIME, df_time, 24), REG_NZ + PV_LEFT },\r
    { FLDATA (BURST, df_burst, 0) },\r
    { FLDATA (STOP_IOE, df_stopioe, 0) },\r
    { DRDATA (CAPAC, df_unit.capac, 18), REG_HRO },\r
    { ORDATA (DEVNUM, df_dib.dev, 6), REG_HRO },\r
    { NULL }\r
    };\r
\r
MTAB df_mod[] = {\r
    { UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &df_set_size },\r
    { UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &df_set_size },\r
    { UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &df_set_size },\r
    { UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &df_set_size },\r
    { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",\r
      &set_dev, &show_dev, NULL },\r
    { 0 }\r
    };\r
\r
DEVICE df_dev = {\r
    "DF", &df_unit, df_reg, df_mod,\r
    1, 8, 17, 1, 8, 12,\r
    NULL, NULL, &df_reset,\r
    &df_boot, &df_attach, NULL,\r
    &df_dib, DEV_DISABLE\r
    };\r
\r
/* IOT routines */\r
\r
int32 df60 (int32 IR, int32 AC)\r
{\r
int32 t;\r
int32 pulse = IR & 07;\r
\r
UPDATE_PCELL;                                           /* update photocell */\r
if (pulse & 1) {                                        /* DCMA */\r
    df_da = 0;                                          /* clear disk addr */\r
    df_done = 0;                                        /* clear done */\r
    df_sta = df_sta & ~DFS_ERR;                         /* clear errors */\r
    int_req = int_req & ~INT_DF;                        /* clear int req */\r
    }\r
if (pulse & 6) {                                        /* DMAR, DMAW */\r
    df_da = df_da | AC;                                 /* disk addr |= AC */\r
    df_unit.FUNC = pulse & ~1;                          /* save function */\r
    t = (df_da & DF_WMASK) - GET_POS (df_time);         /* delta to new loc */\r
    if (t < 0) t = t + DF_NUMWD;                        /* wrap around? */\r
    sim_activate (&df_unit, t * df_time);               /* schedule op */\r
    AC = 0;                                             /* clear AC */\r
    }\r
return AC;\r
}\r
\r
/* Based on the hardware implementation.  DEAL and DEAC work as follows:\r
\r
   6615         pulse 1 = clear df_sta<dex,mex>\r
                pulse 4 = df_sta = df_sta | AC<dex,mex>\r
                          AC = AC | old_df_sta\r
   6616         pulse 2 = clear AC, skip if address confirmed\r
                pulse 4 = df_sta = df_sta | AC<dex,mex> = 0 (nop)\r
                          AC = AC | old_df_sta\r
*/\r
\r
int32 df61 (int32 IR, int32 AC)\r
{\r
int32 old_df_sta = df_sta;\r
int32 pulse = IR & 07;\r
\r
UPDATE_PCELL;                                           /* update photocell */\r
if (pulse & 1)                                          /* DCEA */\r
    df_sta = df_sta & ~(DFS_DEX | DFS_MEX);             /* clear dex, mex */\r
if (pulse & 2)                                          /* DSAC */\r
    AC = ((df_da & DF_WMASK) == GET_POS (df_time))? IOT_SKP: 0;\r
if (pulse & 4) {\r
    df_sta = df_sta | (AC & (DFS_DEX | DFS_MEX));       /* DEAL */\r
    AC = AC | old_df_sta;                               /* DEAC */\r
    }\r
return AC;\r
}\r
\r
int32 df62 (int32 IR, int32 AC)\r
{\r
int32 pulse = IR & 07;\r
\r
UPDATE_PCELL;                                           /* update photocell */\r
if (pulse & 1) {                                        /* DFSE */\r
    if ((df_sta & DFS_ERR) == 0) AC = AC | IOT_SKP;\r
    }\r
if (pulse & 2) {                                        /* DFSC */\r
    if (pulse & 4) AC = AC & ~07777;                    /* for DMAC */\r
    else if (df_done) AC = AC | IOT_SKP;\r
    }\r
if (pulse & 4) AC = AC | df_da;                         /* DMAC */\r
return AC;\r
}\r
\r
/* Unit service\r
\r
   Note that for reads and writes, memory addresses wrap around in the\r
   current field.  This code assumes the entire disk is buffered.\r
*/\r
\r
t_stat df_svc (UNIT *uptr)\r
{\r
int32 pa, t, mex;\r
uint32 da;\r
int16 *fbuf = uptr->filebuf;\r
\r
UPDATE_PCELL;                                           /* update photocell */\r
if ((uptr->flags & UNIT_BUF) == 0) {                    /* not buf? abort */\r
    df_done = 1;\r
    int_req = int_req | INT_DF;                         /* update int req */\r
    return IORETURN (df_stopioe, SCPE_UNATT);\r
    }\r
\r
mex = GET_MEX (df_sta);\r
da = GET_DEX (df_sta) | df_da;                          /* form disk addr */\r
do {\r
    if (da >= uptr->capac) {                            /* nx disk addr? */\r
        df_sta = df_sta | DFS_NXD;\r
        break;\r
		}\r
    M[DF_WC] = (M[DF_WC] + 1) & 07777;                  /* incr word count */\r
    M[DF_MA] = (M[DF_MA] + 1) & 07777;                  /* incr mem addr */\r
    pa = mex | M[DF_MA];                                /* add extension */\r
    if (uptr->FUNC == DF_READ) {                        /* read? */\r
        if (MEM_ADDR_OK (pa)) M[pa] = fbuf[da];         /* if !nxm, read wd */\r
        }\r
    else {                                              /* write */\r
        t = (da >> 14) & 07;                            /* check wr lock */\r
        if ((df_wlk >> t) & 1)                          /* locked? set err */\r
            df_sta = df_sta | DFS_WLS;\r
        else {                                          /* not locked */\r
            fbuf[da] = M[pa];							/* write word */\r
            if (da >= uptr->hwmark) uptr->hwmark = da + 1;\r
            }\r
        }\r
    da = (da + 1) & 0377777;                            /* incr disk addr */\r
    } while ((M[DF_WC] != 0) && (df_burst != 0));       /* brk if wc, no brst */\r
\r
if ((M[DF_WC] != 0) && ((df_sta & DFS_ERR) == 0))       /* more to do? */\r
    sim_activate (&df_unit, df_time);                   /* sched next */\r
else {\r
    if (uptr->FUNC != DF_READ) da = (da - 1) & 0377777;\r
    df_done = 1;                                        /* done */\r
    int_req = int_req | INT_DF;                         /* update int req */\r
    }\r
df_sta = (df_sta & ~DFS_DEX) | ((da >> (12 - DFS_V_DEX)) & DFS_DEX);\r
df_da = da & 07777;                                     /* separate disk addr */\r
return SCPE_OK;\r
}\r
\r
/* Reset routine */\r
\r
t_stat df_reset (DEVICE *dptr)\r
{\r
df_sta = df_da = 0;\r
df_done = 1;\r
int_req = int_req & ~INT_DF;                            /* clear interrupt */\r
sim_cancel (&df_unit);\r
return SCPE_OK;\r
}\r
\r
/* Bootstrap routine */\r
\r
#define OS8_START       07750\r
#define OS8_LEN         (sizeof (os8_rom) / sizeof (int16))\r
#define DM4_START       00200\r
#define DM4_LEN         (sizeof (dm4_rom) / sizeof (int16))\r
\r
static const uint16 os8_rom[] = {\r
    07600,                      /* 7750, CLA CLL        ; also word count */\r
    06603,                      /* 7751, DMAR           ; also address */\r
    06622,                      /* 7752, DFSC           ; done? */\r
    05352,                      /* 7753, JMP .-1        ; no */\r
    05752                       /* 7754, JMP @.-2       ; enter boot */\r
    };\r
\r
static const uint16 dm4_rom[] = {\r
    00200, 07600,               /* 0200, CLA CLL */\r
    00201, 06603,               /* 0201, DMAR           ; read */\r
    00202, 06622,               /* 0202, DFSC           ; done? */\r
    00203, 05202,               /* 0203, JMP .-1        ; no */\r
    00204, 05600,               /* 0204, JMP @.-4       ; enter boot */\r
    07750, 07576,               /* 7750, 7576           ; word count */\r
    07751, 07576                /* 7751, 7576           ; address */\r
    };\r
\r
t_stat df_boot (int32 unitno, DEVICE *dptr)\r
{\r
int32 i;\r
extern int32 sim_switches, saved_PC;\r
\r
if (sim_switches & SWMASK ('D')) {\r
    for (i = 0; i < DM4_LEN; i = i + 2)\r
        M[dm4_rom[i]] = dm4_rom[i + 1];\r
    saved_PC = DM4_START;\r
    }\r
else {\r
    for (i = 0; i < OS8_LEN; i++)\r
         M[OS8_START + i] = os8_rom[i];\r
    saved_PC = OS8_START;\r
    }\r
return SCPE_OK;\r
}\r
\r
/* Attach routine */\r
\r
t_stat df_attach (UNIT *uptr, char *cptr)\r
{\r
uint32 p, sz;\r
uint32 ds_bytes = DF_DKSIZE * sizeof (int16);\r
\r
if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {\r
    p = (sz + ds_bytes - 1) / ds_bytes;\r
    if (p >= DF_NUMDK) p = DF_NUMDK - 1;\r
    uptr->flags = (uptr->flags & ~UNIT_PLAT) |\r
         (p << UNIT_V_PLAT);\r
    }\r
uptr->capac = UNIT_GETP (uptr->flags) * DF_DKSIZE;\r
return attach_unit (uptr, cptr);\r
}\r
\r
/* Change disk size */\r
\r
t_stat df_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (val < 0) return SCPE_IERR;\r
if (uptr->flags & UNIT_ATT) return SCPE_ALATT;\r
uptr->capac = UNIT_GETP (val) * DF_DKSIZE;\r
uptr->flags = uptr->flags & ~UNIT_AUTO;\r
return SCPE_OK;\r
}\r
Commit	Line	Data
196ba1fc PH	1	/* pdp8_df.c: DF32 fixed head disk simulator\r
	2	\r
	3	Copyright (c) 1993-2006, Robert M Supnik\r
	4	\r
	5	Permission is hereby granted, free of charge, to any person obtaining a\r
	6	copy of this software and associated documentation files (the "Software"),\r
	7	to deal in the Software without restriction, including without limitation\r
	8	the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
	9	and/or sell copies of the Software, and to permit persons to whom the\r
	10	Software is furnished to do so, subject to the following conditions:\r
	11	\r
	12	The above copyright notice and this permission notice shall be included in\r
	13	all copies or substantial portions of the Software.\r
	14	\r
	15	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
	16	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
	17	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r
	18	ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
	19	IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
	20	CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
	21	\r
	22	Except as contained in this notice, the name of Robert M Supnik shall not be\r
	23	used in advertising or otherwise to promote the sale, use or other dealings\r
	24	in this Software without prior written authorization from Robert M Supnik.\r
	25	\r
	26	df DF32 fixed head disk\r
	27	\r
	28	15-May-06 RMS Fixed bug in autosize attach (reported by Dave Gesswein)\r
	29	07-Jan-06 RMS Fixed unaligned register access bug (found by Doug Carman)\r
	30	04-Jan-04 RMS Changed sim_fsize calling sequence\r
	31	26-Oct-03 RMS Cleaned up buffer copy code\r
	32	26-Jul-03 RMS Fixed bug in set size routine\r
	33	14-Mar-03 RMS Fixed variable platter interaction with save/restore\r
	34	03-Mar-03 RMS Fixed autosizing\r
	35	02-Feb-03 RMS Added variable platter and autosizing support\r
	36	04-Oct-02 RMS Added DIBs, device number support\r
	37	28-Nov-01 RMS Added RL8A support\r
	38	25-Apr-01 RMS Added device enable/disable support\r
	39	\r
	40	The DF32 is a head-per-track disk. It uses the three cycle data break\r
	41	facility. To minimize overhead, the entire DF32 is buffered in memory.\r
	42	\r
	43	Two timing parameters are provided:\r
	44	\r
	45	df_time Interword timing, must be non-zero\r
	46	df_burst Burst mode, if 0, DMA occurs cycle by cycle; otherwise,\r
	47	DMA occurs in a burst\r
	48	*/\r
	49	\r
	50	#include "pdp8_defs.h"\r
	51	#include <math.h>\r
	52	\r
	53	#define UNIT_V_AUTO (UNIT_V_UF + 0) /* autosize */\r
	54	#define UNIT_V_PLAT (UNIT_V_UF + 1) /* #platters - 1 */\r
	55	#define UNIT_M_PLAT 03\r
	56	#define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)\r
	57	#define UNIT_GETP(x) ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)\r
	58	#define UNIT_AUTO (1 << UNIT_V_AUTO)\r
	59	#define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)\r
	60	\r
	61	/* Constants */\r
	62	\r
	63	#define DF_NUMWD 2048 /* words/track */\r
	64	#define DF_NUMTR 16 /* tracks/disk */\r
65	#define DF_DKSIZE (DF_NUMTR * DF_NUMWD) /* words/disk */\r
66	#define DF_NUMDK 4 /* disks/controller */\r
67	#define DF_WC 07750 /* word count */\r
68	#define DF_MA 07751 /* mem address */\r
69	#define DF_WMASK (DF_NUMWD - 1) /* word mask */\r
70	\r
71	/* Parameters in the unit descriptor */\r
72	\r
73	#define FUNC u4 /* function */\r
74	#define DF_READ 2 /* read */\r
75	#define DF_WRITE 4 /* write */\r
76	\r
77	/* Status register */\r
78	\r
79	#define DFS_PCA 04000 /* photocell status */\r
80	#define DFS_DEX 03700 /* disk addr extension */\r
81	#define DFS_MEX 00070 /* mem addr extension */\r
82	#define DFS_DRL 00004 /* data late error */\r
83	#define DFS_WLS 00002 /* write lock error */\r
84	#define DFS_NXD 00002 /* non-existent disk */\r
85	#define DFS_PER 00001 /* parity error */\r
86	#define DFS_ERR (DFS_DRL \| DFS_WLS \| DFS_PER)\r
87	#define DFS_V_DEX 6\r
88	#define DFS_V_MEX 3\r
89	\r
90	#define GET_MEX(x) (((x) & DFS_MEX) << (12 - DFS_V_MEX))\r
91	#define GET_DEX(x) (((x) & DFS_DEX) << (12 - DFS_V_DEX))\r
92	#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \\r
93	((double) DF_NUMWD)))\r
94	#define UPDATE_PCELL if (GET_POS (df_time) < 6) df_sta = df_sta \| DFS_PCA; \\r
95	else df_sta = df_sta & ~DFS_PCA\r
96	\r
97	extern uint16 M[];\r
98	extern int32 int_req, stop_inst;\r
99	extern UNIT cpu_unit;\r
100	\r
101	int32 df_sta = 0; /* status register */\r
102	int32 df_da = 0; /* disk address */\r
103	int32 df_done = 0; /* done flag */\r
104	int32 df_wlk = 0; /* write lock */\r
105	int32 df_time = 10; /* inter-word time */\r
106	int32 df_burst = 1; /* burst mode flag */\r
107	int32 df_stopioe = 1; /* stop on error */\r
108	\r
109	DEVICE df_dev;\r
110	int32 df60 (int32 IR, int32 AC);\r
111	int32 df61 (int32 IR, int32 AC);\r
112	int32 df62 (int32 IR, int32 AC);\r
113	t_stat df_svc (UNIT *uptr);\r
114	t_stat pcell_svc (UNIT *uptr);\r
115	t_stat df_reset (DEVICE *dptr);\r
116	t_stat df_boot (int32 unitno, DEVICE *dptr);\r
117	t_stat df_attach (UNIT uptr, char cptr);\r
118	t_stat df_set_size (UNIT uptr, int32 val, char cptr, void *desc);\r
119	\r
120	/* DF32 data structures\r
121	\r
122	df_dev RF device descriptor\r
123	df_unit RF unit descriptor\r
124	pcell_unit photocell timing unit (orphan)\r
125	df_reg RF register list\r
126	*/\r
127	\r
128	DIB df_dib = { DEV_DF, 3, { &df60, &df61, &df62 } };\r
129	\r
130	UNIT df_unit = {\r
131	UDATA (&df_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,\r
132	DF_DKSIZE)\r
133	};\r
134	\r
135	REG df_reg[] = {\r
136	{ ORDATA (STA, df_sta, 12) },\r
137	{ ORDATA (DA, df_da, 12) },\r
138	{ ORDATA (WC, M[DF_WC], 12), REG_FIT },\r
139	{ ORDATA (MA, M[DF_MA], 12), REG_FIT },\r
140	{ FLDATA (DONE, df_done, 0) },\r
141	{ FLDATA (INT, int_req, INT_V_DF) },\r
142	{ ORDATA (WLS, df_wlk, 8) },\r
143	{ DRDATA (TIME, df_time, 24), REG_NZ + PV_LEFT },\r
144	{ FLDATA (BURST, df_burst, 0) },\r
145	{ FLDATA (STOP_IOE, df_stopioe, 0) },\r
146	{ DRDATA (CAPAC, df_unit.capac, 18), REG_HRO },\r
147	{ ORDATA (DEVNUM, df_dib.dev, 6), REG_HRO },\r
148	{ NULL }\r
149	};\r
150	\r
151	MTAB df_mod[] = {\r
152	{ UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &df_set_size },\r
153	{ UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &df_set_size },\r
154	{ UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &df_set_size },\r
155	{ UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &df_set_size },\r
156	{ MTAB_XTD\|MTAB_VDV, 0, "DEVNO", "DEVNO",\r
157	&set_dev, &show_dev, NULL },\r
158	{ 0 }\r
159	};\r
160	\r
161	DEVICE df_dev = {\r
162	"DF", &df_unit, df_reg, df_mod,\r
163	1, 8, 17, 1, 8, 12,\r
164	NULL, NULL, &df_reset,\r
165	&df_boot, &df_attach, NULL,\r
166	&df_dib, DEV_DISABLE\r
167	};\r
168	\r
169	/* IOT routines */\r
170	\r
171	int32 df60 (int32 IR, int32 AC)\r
172	{\r
173	int32 t;\r
174	int32 pulse = IR & 07;\r
175	\r
176	UPDATE_PCELL; /* update photocell */\r
177	if (pulse & 1) { /* DCMA */\r
178	df_da = 0; /* clear disk addr */\r
179	df_done = 0; /* clear done */\r
180	df_sta = df_sta & ~DFS_ERR; /* clear errors */\r
181	int_req = int_req & ~INT_DF; /* clear int req */\r
182	}\r
183	if (pulse & 6) { /* DMAR, DMAW */\r
184	df_da = df_da \| AC; /* disk addr \|= AC */\r
185	df_unit.FUNC = pulse & ~1; /* save function */\r
186	t = (df_da & DF_WMASK) - GET_POS (df_time); /* delta to new loc */\r
187	if (t < 0) t = t + DF_NUMWD; /* wrap around? */\r
188	sim_activate (&df_unit, t * df_time); /* schedule op */\r
189	AC = 0; /* clear AC */\r
190	}\r
191	return AC;\r
192	}\r
193	\r
194	/* Based on the hardware implementation. DEAL and DEAC work as follows:\r
195	\r
196	6615 pulse 1 = clear df_sta<dex,mex>\r
197	pulse 4 = df_sta = df_sta \| AC<dex,mex>\r
198	AC = AC \| old_df_sta\r
199	6616 pulse 2 = clear AC, skip if address confirmed\r
200	pulse 4 = df_sta = df_sta \| AC<dex,mex> = 0 (nop)\r
201	AC = AC \| old_df_sta\r
202	*/\r
203	\r
204	int32 df61 (int32 IR, int32 AC)\r
205	{\r
206	int32 old_df_sta = df_sta;\r
207	int32 pulse = IR & 07;\r
208	\r
209	UPDATE_PCELL; /* update photocell */\r
210	if (pulse & 1) /* DCEA */\r
211	df_sta = df_sta & ~(DFS_DEX \| DFS_MEX); /* clear dex, mex */\r
212	if (pulse & 2) /* DSAC */\r
213	AC = ((df_da & DF_WMASK) == GET_POS (df_time))? IOT_SKP: 0;\r
214	if (pulse & 4) {\r
215	df_sta = df_sta \| (AC & (DFS_DEX \| DFS_MEX)); /* DEAL */\r
216	AC = AC \| old_df_sta; /* DEAC */\r
217	}\r
218	return AC;\r
219	}\r
220	\r
221	int32 df62 (int32 IR, int32 AC)\r
222	{\r
223	int32 pulse = IR & 07;\r
224	\r
225	UPDATE_PCELL; /* update photocell */\r
226	if (pulse & 1) { /* DFSE */\r
227	if ((df_sta & DFS_ERR) == 0) AC = AC \| IOT_SKP;\r
228	}\r
229	if (pulse & 2) { /* DFSC */\r
230	if (pulse & 4) AC = AC & ~07777; /* for DMAC */\r
231	else if (df_done) AC = AC \| IOT_SKP;\r
232	}\r
233	if (pulse & 4) AC = AC \| df_da; /* DMAC */\r
234	return AC;\r
235	}\r
236	\r
237	/* Unit service\r
238	\r
239	Note that for reads and writes, memory addresses wrap around in the\r
240	current field. This code assumes the entire disk is buffered.\r
241	*/\r
242	\r
243	t_stat df_svc (UNIT *uptr)\r
244	{\r
245	int32 pa, t, mex;\r
246	uint32 da;\r
247	int16 *fbuf = uptr->filebuf;\r
248	\r
249	UPDATE_PCELL; /* update photocell */\r
250	if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */\r
251	df_done = 1;\r
252	int_req = int_req \| INT_DF; /* update int req */\r
253	return IORETURN (df_stopioe, SCPE_UNATT);\r
254	}\r
255	\r
256	mex = GET_MEX (df_sta);\r
257	da = GET_DEX (df_sta) \| df_da; /* form disk addr */\r
258	do {\r
259	if (da >= uptr->capac) { /* nx disk addr? */\r
260	df_sta = df_sta \| DFS_NXD;\r
261	break;\r
262	}\r
263	M[DF_WC] = (M[DF_WC] + 1) & 07777; /* incr word count */\r
264	M[DF_MA] = (M[DF_MA] + 1) & 07777; /* incr mem addr */\r
265	pa = mex \| M[DF_MA]; /* add extension */\r
266	if (uptr->FUNC == DF_READ) { /* read? */\r
267	if (MEM_ADDR_OK (pa)) M[pa] = fbuf[da]; /* if !nxm, read wd */\r
268	}\r
269	else { /* write */\r
270	t = (da >> 14) & 07; /* check wr lock */\r
271	if ((df_wlk >> t) & 1) /* locked? set err */\r
272	df_sta = df_sta \| DFS_WLS;\r
273	else { /* not locked */\r
274	fbuf[da] = M[pa]; /* write word */\r
275	if (da >= uptr->hwmark) uptr->hwmark = da + 1;\r
276	}\r
277	}\r
278	da = (da + 1) & 0377777; /* incr disk addr */\r
279	} while ((M[DF_WC] != 0) && (df_burst != 0)); /* brk if wc, no brst */\r
280	\r
281	if ((M[DF_WC] != 0) && ((df_sta & DFS_ERR) == 0)) /* more to do? */\r
282	sim_activate (&df_unit, df_time); /* sched next */\r
283	else {\r
284	if (uptr->FUNC != DF_READ) da = (da - 1) & 0377777;\r
285	df_done = 1; /* done */\r
286	int_req = int_req \| INT_DF; /* update int req */\r
287	}\r
288	df_sta = (df_sta & ~DFS_DEX) \| ((da >> (12 - DFS_V_DEX)) & DFS_DEX);\r
289	df_da = da & 07777; /* separate disk addr */\r
290	return SCPE_OK;\r
291	}\r
292	\r
293	/* Reset routine */\r
294	\r
295	t_stat df_reset (DEVICE *dptr)\r
296	{\r
297	df_sta = df_da = 0;\r
298	df_done = 1;\r
299	int_req = int_req & ~INT_DF; /* clear interrupt */\r
300	sim_cancel (&df_unit);\r
301	return SCPE_OK;\r
302	}\r
303	\r
304	/* Bootstrap routine */\r
305	\r
306	#define OS8_START 07750\r
307	#define OS8_LEN (sizeof (os8_rom) / sizeof (int16))\r
308	#define DM4_START 00200\r
309	#define DM4_LEN (sizeof (dm4_rom) / sizeof (int16))\r
310	\r
311	static const uint16 os8_rom[] = {\r
312	07600, /* 7750, CLA CLL ; also word count */\r
313	06603, /* 7751, DMAR ; also address */\r
314	06622, /* 7752, DFSC ; done? */\r
315	05352, /* 7753, JMP .-1 ; no */\r
316	05752 /* 7754, JMP @.-2 ; enter boot */\r
317	};\r
318	\r
319	static const uint16 dm4_rom[] = {\r
320	00200, 07600, /* 0200, CLA CLL */\r
321	00201, 06603, /* 0201, DMAR ; read */\r
322	00202, 06622, /* 0202, DFSC ; done? */\r
323	00203, 05202, /* 0203, JMP .-1 ; no */\r
324	00204, 05600, /* 0204, JMP @.-4 ; enter boot */\r
325	07750, 07576, /* 7750, 7576 ; word count */\r
326	07751, 07576 /* 7751, 7576 ; address */\r
327	};\r
328	\r
329	t_stat df_boot (int32 unitno, DEVICE *dptr)\r
330	{\r
331	int32 i;\r
332	extern int32 sim_switches, saved_PC;\r
333	\r
334	if (sim_switches & SWMASK ('D')) {\r
335	for (i = 0; i < DM4_LEN; i = i + 2)\r
336	M[dm4_rom[i]] = dm4_rom[i + 1];\r
337	saved_PC = DM4_START;\r
338	}\r
339	else {\r
340	for (i = 0; i < OS8_LEN; i++)\r
341	M[OS8_START + i] = os8_rom[i];\r
342	saved_PC = OS8_START;\r
343	}\r
344	return SCPE_OK;\r
345	}\r
346	\r
347	/* Attach routine */\r
348	\r
349	t_stat df_attach (UNIT uptr, char cptr)\r
350	{\r
351	uint32 p, sz;\r
352	uint32 ds_bytes = DF_DKSIZE * sizeof (int16);\r
353	\r
354	if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {\r
355	p = (sz + ds_bytes - 1) / ds_bytes;\r
356	if (p >= DF_NUMDK) p = DF_NUMDK - 1;\r
357	uptr->flags = (uptr->flags & ~UNIT_PLAT) \|\r
358	(p << UNIT_V_PLAT);\r
359	}\r
360	uptr->capac = UNIT_GETP (uptr->flags) * DF_DKSIZE;\r
361	return attach_unit (uptr, cptr);\r
362	}\r
363	\r
364	/* Change disk size */\r
365	\r
366	t_stat df_set_size (UNIT uptr, int32 val, char cptr, void *desc)\r
367	{\r
368	if (val < 0) return SCPE_IERR;\r
369	if (uptr->flags & UNIT_ATT) return SCPE_ALATT;\r
370	uptr->capac = UNIT_GETP (val) * DF_DKSIZE;\r
371	uptr->flags = uptr->flags & ~UNIT_AUTO;\r
372	return SCPE_OK;\r
373	}\r