First Commit of my working state

[simh.git] / S3 / system3.txt

    The IBM System/3 simulator is configured as follows:\r
\r
	CPU	5410 (Model 10) CPU with 64KB of memory.\r
	PKB	5471 Printer/Keyboard console.\r
	CDR	1442 Card Reader\r
	CDP	1442 Card Punch	\r
	CDP2	1442 2nd stacker	\r
	LPT	1403 Line Printer\r
	R1	5444 Top Drive (removeable)\r
	F1	5444 Top Drive (fixed)\r
	R2	5444 Bottom Drive (removeable)\r
	F2	5444 Bottom Drive (fixed\r
 \r
    The only CPU options are to set Model 15 mode (not implemented), DPF\r
(Dual Programming Facility, not implemented), and the memory size 8K, 16K,\r
32K, 48K, or 64K.\r
\r
    CPU registers are the standard System/3 set:\r
\r
	name		size	Description\r
\r
	IAR-P1		16	Instruction Address Register for Program Level 1\r
	ARR-P2		16	Address Recall Register for Program Level 1\r
	IAR-P2		16	IAR for Program Level 2 (not implemented)\r
	ARR-P2		16	ARR for Program Level 2 (not implemented)\r
	AAR		16	A-Address Register\r
	BAR		16	B-Address Register\r
	PSR		16	Program Status Register\r
	XR1		16	Index Register 1\r
	XR2		16	Index Register 2\r
	IAR<0:7>	16	IAR for interrupt level 0 thru 7\r
	ARR<0:7>	16	ARR for interrupt level 0 thru 7\r
\r
	Plus these simulator registers:\r
\r
	IAR		16	Value of last IAR used.\r
	LEVEL		 8	Current operating level (8=P1, 9=P2,\r
					0 thru 7 = Interrupt level)\r
	SR		16	Front Panel switches\r
	INT		16	Interrupt Request Flags\r
	WRU		8	Simulator Interrupt Character\r
	BREAK		17	Breakpoint Address\r
	DEBUG		16	Debugging bits:\r
				0x01: Write all instructions executed to\r
					file trace.log.\r
				0x02: Write details of all Disk I/O \r
					requests to trace.log.\r
				0x80: Breakpoint on first character\r
					written to 5471 printer.\r
\r
1	5471 Printer/Keyboard\r
\r
	This is the operator console.  It has the following registers:\r
\r
	FLAG	5471 Flag Bytes\r
	IBUF:	Input character from keyboard\r
	OBUF:	Output character to printer\r
	POS:	Number of characters printed\r
	TIME:	Delay for device operation\r
	REQKEY:	ASCII value of key mapped to 5471 REQUEST key\r
	RTNKEY:	ASCII value of key mapped to 5471 RETURN key\r
	ENDKEY:	ASCII value of key mapped to 5471 END key\r
	CANKEY:	ASCII value of key mapped to 5471 CANCEL key\r
	\r
\r
2	1442 Card Reader.  This reader reads 80-column cards; the input\r
	is usually an ASCII file which is translated to EBCDIC when read,\r
	but optionally can be a binary file in EBCDIC format (such as an\r
	object program).\r
\r
	LAST	Last card switch\r
	ERR	Card Reader Error\r
	NOTRDY	1442 reader not ready (not attached or past EOF)\r
	DAR	Data Address Register (shared with punch)\r
	LCR	Length Count Register (shared with punch)\r
	EBCDIC	EBCDIC mode flag: if 1, input is 80-col EBCDIC binary.\r
		(IPL from 1442 automatically sets this to 1).\r
	S2	Stacker 2 is selected when this is 1\r
	POS	Number of cards read\r
	TIME	Device Delay\r
\r
	The real hardware 1442 had only 1 hopper for cards, whether\r
	these were used for blank cards for punching, or cards to be\r
	read.  Cards could be read without a feed cycle, then\r
	punched.  When punching cards, the SCP does a read of a card,\r
	makes sure it is blank, and then punches it.  To simulate\r
	this without requiring that a stack of blank lines be attached\r
	to the card reader device, a special feature of the simulator\r
	is this:  if no file is attached to the cdr device, but a file\r
	is attached to the cdp or the cdp2 devices, any read from the\r
	reader will return a blank card -- i.e. when punching, an\r
	unattached cdr device is assumed to be loaded with an unlimited\r
	supply of blank cards.\r
\r
\r
3	1442 Card Punch.  Normally cards are written to the attached\r
	disk file as ASCII with newline/cr delimiters.  But an optional\r
	flag allows writing as 80-column binary EBCDIC.\r
\r
	ERR	Card Punch Error\r
	EBCDIC	When this is 1, output will be 80-col EBCDIC.\r
	S2	When this is 1, output is placed in stacker 2\r
	NOTRDY	1442 punch not ready (not attached)\r
	DAR	Data Address Register (shared with reader)\r
	LCR	Length Count Register (shared with reader)\r
	POS	Number of cards punched\r
	TIME	Device Delay\r
\r
4 	1442 Stacker 2.  When cards are to be punched in stacker 2,\r
	attach a disk file to this device (cdp2) to hold that output.\r
	Note: When SCP punches cards, the default is to punch in\r
	stacker 2.\r
\r
	POS0	Number of cards punched.\r
\r
5	1403 Printer.  This is a 132-column output device, emulating\r
	the famous IBM 1403, models 2, 6, and N1.  Output is always\r
	translated to ASCII with newline/CR delimiters.  Page advance\r
	is output as a form feed.\r
\r
	ERR	1403 error flags\r
	LPDAR	Data Address Register\r
	LPFLR	Forms Length Register\r
	LPIAR	Image Address Register\r
	LINECT	Current Line on form\r
	POS	Number of lines printed\r
\r
6 	5444 Disk Drives (R1, R2, F1, F2)\r
\r
	The 5444 came as a set of two drives, each with two disks.  The\r
	top disk in a drive was removable, the bottom fixed.  The first\r
	drive consists of disks R1 and F1, the second drive R2 and F2.\r
	Each disk holds 2,467,600 bytes of user data, plus 3 alternate\r
	tracks and a CE track.  Flagging of alternate tracks is not\r
	supported in this version of the simulator.\r
\r
	NOTRDY	Drive not ready (not attached)\r
	SEEK	Drive is busy with a seek operation\r
	DAR	Data Address Register\r
	CAR	Control Address Register\r
	ERR	Error Flags (16 bits)\r
	CYL	Current Cylinder (0 thru 203)\r
	HEAD	Current head (0 or 1)\r
	POS	Current position in attached disk file\r
	TIME	Device Delay\r
\r
7  	Symbolic Display and Input\r
\r
	The System/3 Simulator supports symbolic display and input.\r
	Display is controlled by command line switches:\r
\r
	(none)	display as hex EBCDIC\r
	-c	display bytes as characters\r
	-m	display instruction mnemonics.\r
	-a	display a 256-byte block of memory in both hex and ASCII.\r
\r
   	The symbolic  format contains the same elements as the machine\r
	language operation, but not always in the same order.  The\r
	operation code frequently specifies both the opcode and the Q byte,\r
	and the top nybble of the opcode is determined by the format of the\r
	addresses.\r
\r
	Addresses take two forms:  the direct address in hex, or a relative\r
	address specified thusly: (byte,XRx) where 'byte' is a 1-byte\r
	offset, and XRx is either XR1 or XR2 for the two index registers. \r
	Use these formats when 'address' is indicated below:\r
\r
   	When 'reg' is mentioned, a mnemonic may be used for the register,\r
   	thusly:\r
	\r
	IAR	Instruction Address Register for the current program level\r
	ARR	Address Recall Register for the current program level\r
	P1IAR	IAR for Program Level 1\r
	P2IAR	IAR for Program Level 2\r
	PSR	Program Status Register\r
	XR1	Index Register 1\r
	XR2 	Index Register 2\r
	IARx	IAR for the interrupt level x (x = 0 thru 7)\r
	   \r
   	All other operands mentioned below are single-byte hex, except for\r
	the length (len) operand of the two-address instructions, which is a\r
	decimal length in the range 1-256.\r
\r
        In operations where there is a source and a destination, the \r
	destination is always operand 1, the source is operand 2.\r
   \r
   	No-address formats:\r
   	------------------\r
   \r
   	HPL hex,hex		Halt Program Level, the operands are the\r
				Q and R bytes.\r
   \r
   \r
   	One-address formats:\r
  	-------------------\r
   \r
	A reg,address        	Add to register\r
   	CLI address,byte	Compare Logical Immediate\r
   	MVI address,byte	Move Immediate\r
   	TBF address,mask	Test Bits Off\r
   	TBN address,mask	Test Bits On\r
  	SBF address,mask	Set Bits Off\r
   	SBN address,mask	Set Bits On\r
   	ST reg,address		Store Register\r
   	L reg,address		Load Register\r
   	LA reg,address		Load Address (reg can only be XR1 or XR2)\r
   	JC address,cond		Jump on Condition\r
   	BC address,cond		Branch on Condition\r
   \r
   	These operations do not specify a qbyte, it is implicit in the\r
   	opcode:\r
   \r
   	B address		Unconditional branch to address\r
   	BE address		Branch Equal\r
   	BNE address		Branch Not Equal\r
   	BH address		Branch High\r
   	BNH address		Branch Not High\r
   	BL address		Branch Low\r
   	BNL address		Branch Not Low\r
   	BT address		Branch True\r
   	BF address		Branch False\r
   	BP address		Branch Plus\r
   	BM address		Branch Minus\r
   	BNP address		Branch Not Plus\r
   	BNM address		Branch Not Minus\r
   	BZ address		Branch Zero\r
   	BNZ address		Branch Not Zero\r
   	BOZ address		Branch Overflow Zoned\r
   	BOL address		Branch Overflow Logical\r
   	BNOZ address		Branch No Overflow Zoned\r
   	BNOL address		Branch No Overflow Logical\r
   	NOPB address		No - never branch\r
   \r
   	(substitute J for B above for a set of Jumps -- 1-byte operand (not\r
    	2), always jumps forward up to 255 bytes from the address following\r
    	the Jump instruction. In this case, 'address' cannot be less than\r
    	the current address, nor greater than the current address + 255)\r
   \r
   	Two-address formats (first address is destination, len is decimal 1-256):\r
   	-------------------\r
   \r
   	MVC address,address,len		Move Characters\r
   	CLC address,address,len		Compare Logical Characters\r
   	ALC address,address,len		Add Logical Characters\r
   	SLC address,address,len		Subtract Logical Characters\r
   	ED address,address,len		Edit\r
   	ITC address,address,len		Insert and Test Characters\r
   	AZ address,address,len		Add Zoned Decimal\r
   	SZ address,address,len		Subtract Zoned Decimal\r
   \r
   	MNN address,address		Move Numeric to Numeric\r
   	MNZ address,address		Move Numeric to Zone\r
   	MZZ address,address		Move Zone to Zone\r
   	MZN address,address		Move Zone to Numeric\r
   \r
   	I/O Format\r
  	----------\r
   \r
   	In the I/O format, there are always 3 fields:\r
   \r
   	da - Device Address 0-15 (decimal)\r
   	m - Modifier 0-1\r
   	n - Function 0-7\r
   	\r
   	The meaning of these is entirely defined by the device addressed.	\r
   	\r
   	There may be an optional control byte, or an optional address (based\r
	on the type of instruction).\r
\r
	SNS da,m,n,address		Sense I/O\r
	LIO da,m,n,address		Load I/O\r
	TIO da,m,n,address		Test I/O\r
	\r
	SIO da,m,n,cc			Start I/O -- cc is a control byte\r
	\r
	APL da,m,n			Advance Program Level \r
\r
\r
8	Device Programming.\r
\r
	Note: On a model 15, interrupts are used for all devices.  On\r
	other models, interrupts are only used for the printer/keyboard.\r
\r
	This is a summary of the DA, M, N, and CC codes for all supported\r
	devices:\r
\r
	5471 Printer Keyboard\r
	---------------------\r
\r
		The PKB has 2 visible indicators: Proceed and Request\r
		Pending.  It has a normal keyboard and 4 special keys:\r
		Request, Return, End, and Cancel.\r
\r
		SIO 1,0,0,XX	Start Keyboard Operation, bit masks for XX are:\r
				X'20': Request Pending Indicator On\r
				X'10': Proceed Indicator On\r
				X'04': Request Key Interrupts Enable (1) Disable (0)\r
				X'02': Other Key Interrupts Enable (1) Disable (0)\r
				X'01': Reset request key and other key interrupts\r
\r
		SIO 1,1,0,XX	Start Printer Operation, bit masks for XX are:\r
				X'80': Start Printing\r
				X'40': Start Carrier Return\r
				X'04': Printer Interrupt Enable(1) or Disable (0)\r
				X'01': Reset Printer Interrupt\r
\r
		LIO 1,1,0,addr	Load Printer Output Character\r
				addr is address of low-order (highest numbered)\r
				byte of two-byte field, and high-order byte\r
				(that is, addr - 1) is loaded into output\r
				register to print.  Printing is done one character\r
				at a time.\r
\r
		SNS 1,0,1,addr	Sense Status Bytes 0 and 1:\r
				Byte 0 (leftmost) is the character typed in\r
					in EBCDIC.\r
				Byte 1 is status:\r
				X'80': Request key interrupt pending\r
				X'40': End or Cancel key interrupt pending\r
				X'20': Cancel key pressed\r
				X'10': End Key Pressed\r
				X'08': Return or data key interrupt pending\r
				X'04': Return key pressed\r
\r
		SNS 1,0,3,addr	Sense Status Bytes 2 and 3: returns 0000 in\r
					this sim.\r
\r
	1442 Reader/Punch\r
	-----------------\r
\r
		SIO 5,0,0,XX	Feed Card without reading/punching\r
				XX is stacker select for all functions: 0 = stacker\r
				1 (normal), 1 = stacker 2.\r
\r
		SIO 5,0,1,XX	Read Card\r
		SIO 5,0,2,XX	Punch and Feed\r
		SIO 5,0,3,XX	Read Column Binary\r
		SIO 5,0,4,XX	Punch with no feed\r
\r
		TIO 5,0,0,addr	Branch to addr if not ready or busy\r
		TIO 5,0,2,addr	Branch to addr if busy\r
		TIO 5,0,5,addr	(mod 15 only) branch if interrupt pending\r
\r
		APL 5,0,0	Loop (or switch prog levels) if not ready/busy\r
		APL 5,0,2	Loop (or switch) if busy\r
		APL 5,0,5	Loop (or switch) if interrupt pending (mod 15 only)\r
\r
		LIO 5,0,0,addr	Load 2-byte field to Length Count Register\r
		LIO 5,0,4,addr	Load 2-byte field to Data Address Register\r
				(DAR is incremented by a read/punch operation and must\r
				be reset every card)\r
\r
		SNS 5,0,1,addr	Sense CE indicators (0000 returned in this sim)\r
		SNS 5,0,2,addr	Sense CE indicators (0000 returned in this sim)\r
		SNS 5,0,3,addr	Sense Status Indicators: (only simulated bits shown)\r
				X'8000': Read Check\r
				X'4000': Last Card\r
				X'2000': Punch Check\r
				X'1000': Data Overrun\r
				X'0800': Not Ready\r
\r
\r
	1403 Printer\r
	------------\r
\r
		SIO 14,0,0,XX	Line space XX lines (0-3 valid in XX)\r
		SIO 14,0,2,XX	Print a line space (0-3 valid in XX)\r
		SIO 14,0,4,XX	Skip Only (line number 1-112 in XX)\r
\r
		SIO 14,0,6,XX	Print and Skip (line number 0-112 in XX)\r
\r
		TIO 14,0,0,addr	Branch to addr if not ready\r
		TIO 14,0,2,addr	Branch to addr if buffer busy\r
		TIO 14,0,3,addr	Branch to addr if interrupt pending (mod 15 only)\r
		TIO 14,0,4,addr	Branch if carriage busy\r
		TIO 14,0,6,addr	Branch if printer busy\r
\r
		APL 14,0,0	Loop (or switch prog levels) if not ready/check\r
		APL 14,0,2	Loop (or switch) if buffer busy\r
		APL 14,0,3	Loop (or switch) if interrupt pending (mod 15 only)\r
		APL 14,0,4	Loop (or switch) if carriage busy\r
		APL 14,0,6	Loop (or switch) if printer busy\r
\r
		LIO 14,0,0,addr	Load 1 byte to Forms Length Reg at addr-1\r
		LIO 14,0,4,addr	Load 2 bytes to Chain Image Address Register\r
		LIO 14,0,6,addr	Load 2 bytes to Data Address Register\r
\r
		SNS 14,0,0,addr	Sense Character Count\r
		SNS 14,0,4,addr	Sense LPIAR (Image Address Register)\r
		SNS 14,0,6,addr	Sense LPDAR (data addres register)\r
\r
\r
	5444 Disk Drives\r
	----------------\r
\r
		Each drive has two disks (upper and lower), each disk\r
		has two surfaces (upper and lower), each surface has\r
		24 256-byte sectors, sectors are number 0 thru 23 on\r
		upper surface, 32 thru 55 on lower.\r
\r
		d = drive, 0 is R1/F1, 1 is R2/F2\r
		s = surface, 0 = upper (removable), 1 = lower (fixed)\r
\r
		The Control register points to the leftmost byte of a 4-byte\r
		control field in memory with these bytes:\r
\r
			F - Flag byte (not supported in this sim)\r
			C - Cylinder Address (0-203)\r
			S - Sector Number (0-23, or 32-55) in top 6 bits\r
			N - Number of sectors minus 1\r
\r
		These have meaning for all operations except seek, seek uses\r
		the fields differently.\r
\r
		SIO 1d,s,0,XX	Seek, XX not used, control field is used:\r
\r
			F - not used\r
			C - not used\r
			S - high bit is head to be used 0-upper 1-lower\r
			    low bit is direction to move 0-back 1-forward\r
			N - number of cylinders to move\r
\r
		SIO 1d,s,1,XX	Read, values of XX are as follows:\r
			X'00':	Read Data\r
			X'01':	Read Identifier (updates control field, no\r
					data is read)\r
			X'02':	Read Data Diagnostic\r
			X'03':	Verify (does not read, but checks)\r
\r
		SIO 1d,s,2,XX	Write, values of XX are as follows:\r
			X'00':	Write Data\r
			X'01':	Write Identifier (24 sectors with byte at\r
					data address register)\r
		\r
		SIO 1d,s,3,XX	Scan. All 256 bytes in memory at data\r
				address register are compared to disk\r
				sectors on current track, except those\r
				bytes of X'FF' are not compared.  Values of\r
				XX are:\r
\r
				X'00': Scan Equal\r
				X'01': Scan Low or Equal\r
				X'02': Scan High or Equal\r
\r
		LIO 1d,0,4,addr	Load Data Address Register\r
		LIO 1d,0,6,addr	Load Disk Control Address Register\r
\r
		TIO 1d,0,0,addr	Branch if not ready/unit check\r
		TIO 1d,0,2,addr	Branch if busy\r
		TIO 1d,0,4,addr	Branch if Scan Found\r
\r
		APL 1d,0,0	Loop if not ready/unit check\r
		APL 1d,0,2	Loop if busy\r
		APL 1d,0,4	Loop if scan found\r
\r
		SNS 1d,0,2,addr	Sense Status Bytes 0 and 1: (simulated \r
				bits only are shown, otehrs are 0):\r
				X'1000': equipment check\r
				X'0800': data check\r
				X'0400': No record found\r
				X'0100': Seek Check (past cyl 203)\r
				X'0080': Scan equal Hit\r
				X'0040': Cylinder 0\r
				X'0020': End of Cylinder \r
				X'0010': Seek Busy\r
		SNS 1d,0,3,addr	Sense bytes 2 and 3 (0000 in this sim)\r
		SNS 1d,0,4,addr	Sense Data Address Register\r
		SNS 1d,0,6,addr	Sense Control Address Register\r
\r
\r
 \r
\r