First Commit of my working state

[simh.git] / SDS / sds_diag.txt

SDS Diagnostics, using the SDS 930/940 Master Diagnostic Tape image (D930X4A.TAP)\r
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Summary\r
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930 0-16K Memory Test			passed\r
930 16K-32K Memory Test			passed\r
930 Instruction Test			passed\r
930 P&S Register Test			passed\r
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---\r
930 0-16K Memory Test\r
\r
sim> att mt diag.tap\r
sim> d a 1\r
sim> d bpt4 1				; stop every 1/2 cycle\r
sim> boot mt\r
\r
HALT instruction, P: 00050 (STA 122,4)\r
sim> ex a\r
A:	00000000			; error count\r
sim> c\r
\r
HALT instruction, P: 37650 (STA 37722,4)\r
\r
sim> ex a\r
A:	00000000			; error count\r
\r
---\r
930 16K-32K Memory Test\r
\r
sim> att mt diag.tap\r
sim> d a 2\r
sim> d bpt4 2				; stop every 1/2 cycle\r
sim> boot mt\r
\r
\r
HALT instruction, P: 00050 (STA 6)\r
sim> ex a\r
A:      00000000			; error count\r
sim> c\r
\r
HALT instruction, P: 37650 (STA 37406)\r
sim> ex a\r
A:      00000000			; error count\r
sim> c\r
\r
---\r
930 Instruction Diagnostic\r
\r
sim> att mt diag.tap\r
sim> d a 3\r
sim> br 17				; catch start of diagnostic\r
sim> boot mt\r
\r
Breakpoint, P: 00017 (BRR 12,2)\r
sim> nobr 17\r
sim> br 112				; catch end of diagnostic\r
sim> c\r
\r
Breakpoint, P: 00112 (BRU 3)\r
\r
---\r
930 P&S Register Test\r
\r
sim> att mt diag.tap\r
sim> d a 4\r
sim> br 60				; catch end of pass\r
sim> boot mt\r
\r
Breakpoint, P: 00060 (BRU 22)\r
\r
---\r
Bugs\r
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1.  IO: Channel WAR not cleared after memory store\r
2.  IO: dev_map should contain _flags, not _v_flags\r
3.  SYS: Errors in system tables\r
4.  SYS: Character conversion table had 0 (space) as illegal, should be -1\r
5.  IO: Channel CPW calculation wrong for 12b mode\r
6.  RAD, DSK, MT: Instruction masks wrong for RAD, DSK, MT\r
7.  IO: Missing subscripts in dev_disp references\r
8.  RAD: typos referencing DSK\r
9.  IO: SKS 3 call incorrect\r
10. DRM: Drum track mask width incorrect\r
11. CPU: Memory management trap left reason in bogus state, stopped simulator\r
12. CPU: Interrupts require api_lvl as well as api_lvlhi, like PDP-10, PDP-15\r
13. CPU: Bug in find interrupt request\r
14. CPU: Interrupt priority scheme recoded for left to right priority\r
15. CPU: overflow test coded backwards\r
16. CPU: Rotates operate mod 48, not with upper limit of 48 (manual incorrect)\r
17. CPU: RSH not handling >= 48 correctly\r
18. CPU: CNA is 2's complement not 1's complement\r
19. CPU: MUL failed to mask cross product correctly\r
20. CPU: EM2, EM3 test using wrong 'channel'\r
21. CPU: EM3 test tested EM2 instead\r
22. CPU: POP must save EM2, EM3 like BRM (manual incorrect)\r
23. CPU: Shifts need special EA calculation, direct cycles using 9b indexing\r
24. CPU: Shifts ignore addr<13:14>\r
25. CPU: Diagnostic uses undefined shift 'normalize cyclic'\r
26. CPU: Divide 2'c complement of AB leaves B<23> unchanged\r
27. CPU: Divide overflow test requires special cases for divd.h == divr\r
28. CPU: Divide uses non-restoring algorithm\r
29. CPU: Channel terminate output must be deferred until channel buffer clears\r
30. CPU: Channel terminate output to magtape is convert to scan, must be\r
    handled in channel logic\r
31. SYS: duplicate entries for shifts\r
32. SYS: mask for shifts did not include indirect flag\r
33. MUX: Genie/SDS use inverted meanings for line enable flag\r
34. MT: missing fseek before write eof\r
35. MT: displayed characters only 7b wide instead of 8b\r
36. CPU: EOD 20000 used by diagnostic (EM change is NOP)\r
37. CPU: SKD sets all 24b of X, not just exponent\r
38. CPU: reset should not clear A, B, X\r