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1 | /* sds_drm.c: SDS 940 Project Genie drum simulator\r |
2 | \r | |
3 | Copyright (c) 2002-2005, Robert M. Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | drm drum\r | |
27 | \r | |
28 | The drum is buffered in memory.\r | |
29 | \r | |
30 | Note: the Project Genie documentation and the actual monitor sources disagree\r | |
31 | on the I/O instruction definitions for the drum. The simulator follows the\r | |
32 | monitor sources, as follows:\r | |
33 | \r | |
34 | DCC OP 00230404B RESET DRUM CHANNEL\r | |
35 | DSC OP 00230204B START DRUM CHANNEL (NO CHAIN)\r | |
36 | DRA OP 00230504B READ DRUM TIMING COUNTER INTO 21B\r | |
37 | DSR OP 04030204B SKIP IF DRUM NOT BUSY\r | |
38 | DSE OP 04037404B SKIP IF NO DRUM ERROR\r | |
39 | */\r | |
40 | \r | |
41 | #include "sds_defs.h"\r | |
42 | #include <math.h>\r | |
43 | \r | |
44 | /* Constants */\r | |
45 | \r | |
46 | #define DRM_N_WD 11 /* word addr width */\r | |
47 | #define DRM_V_WD 0 /* position */\r | |
48 | #define DRM_M_WD ((1 << DRM_N_WD) - 1) /* word mask */\r | |
49 | #define DRM_NUMWD (1 << DRM_N_WD) /* words/sector */\r | |
50 | #define DRM_NUMGP 236 /* gap/sector */\r | |
51 | #define DRM_PHYWD (DRM_NUMWD + DRM_NUMGP) /* phys wds/sector */\r | |
52 | #define DRM_N_SC 3 /* sect addr width */\r | |
53 | #define DRM_V_SC (DRM_N_WD) /* position */\r | |
54 | #define DRM_M_SC ((1 << DRM_N_SC) - 1) /* sector mask */\r | |
55 | #define DRM_NUMSC (1 << DRM_N_SC) /* sectors/track */\r | |
56 | #define DRM_N_TR 7 /* track addr width */\r | |
57 | #define DRM_V_TR (DRM_N_WD+DRM_N_SC) /* position */\r | |
58 | #define DRM_M_TR ((1 << DRM_N_TR) - 1) /* track mask */\r | |
59 | #define DRM_NUMTR 84 /* tracks/drum */\r | |
60 | #define DRM_N_ADDR (DRM_N_WD+DRM_N_SC+DRM_N_TR) /* drum addr width */\r | |
61 | #define DRM_SWMASK ((1 << (DRM_N_WD+DRM_N_SC)) - 1)/* sector+word mask */\r | |
62 | #define DRM_DAMASK ((1 << DRM_N_ADDR) - 1) /* drum addr mask */\r | |
63 | #define DRM_SIZE (DRM_NUMTR*DRM_NUMSC*DRM_NUMWD) /* words/disk */\r | |
64 | #define DRM_WCMASK 037777 /* wc mask */\r | |
65 | #define DRM_GETSC(x) (((x) >> DRM_V_SC) & DRM_M_SC)\r | |
66 | \r | |
67 | #define DRM_PC 020\r | |
68 | #define DRM_AD 021\r | |
69 | #define DRM_ADAT (1 << (DRM_N_WD + DRM_N_SC)) /* data flag */\r | |
70 | \r | |
71 | #define DRM_SFET 0 /* fetch state */\r | |
72 | #define DRM_SFCA 1 /* fetch CA */\r | |
73 | #define DRM_SFDA 2 /* fetch DA */\r | |
74 | #define DRM_SXFR 3 /* xfer */\r | |
75 | \r | |
76 | #define DRM_V_OP 21 /* drum op */\r | |
77 | #define DRM_M_OP 07\r | |
78 | #define DRM_V_RW 20\r | |
79 | #define DRM_GETOP(x) (((x) >> DRM_V_OP) & DRM_M_OP)\r | |
80 | #define DRM_GETRW(x) (((x) >> DRM_V_RW) & 1)\r | |
81 | #define DRM_OXF 0 /* xfer */\r | |
82 | #define DRM_OCX 1 /* cond xfer */\r | |
83 | #define DRM_OBR 2 /* branch */\r | |
84 | #define DRM_ORS 3 /* reset error */\r | |
85 | #define DRM_END 4 /* end prog */\r | |
86 | #define DRM_EIE 5 /* end int if err */\r | |
87 | #define DRM_EIU 7 /* end int uncond */\r | |
88 | \r | |
89 | #define GET_TWORD(x) ((int32) fmod (sim_gtime() / ((double) (x)), \\r | |
90 | ((double) (DRM_NUMSC * DRM_PHYWD))))\r | |
91 | \r | |
92 | extern uint32 M[]; /* memory */\r | |
93 | extern uint32 alert, int_req;\r | |
94 | extern int32 stop_invins, stop_invdev, stop_inviop;\r | |
95 | uint32 drm_da = 0; /* disk address */\r | |
96 | uint32 drm_ca = 0; /* core address */\r | |
97 | uint32 drm_wc = 0; /* word count */\r | |
98 | int32 drm_par = 0; /* cumulative par */\r | |
99 | int32 drm_err = 0; /* error */\r | |
100 | int32 drm_rw = 0; /* read/write */\r | |
101 | int32 drm_sta = 0; /* drum state */\r | |
102 | int32 drm_ftime = 3; /* time to fetch */\r | |
103 | int32 drm_xtime = 1; /* time to xfr */\r | |
104 | int32 drm_stopioe = 1; /* stop on error */\r | |
105 | \r | |
106 | DEVICE drm_dev;\r | |
107 | t_stat drm (uint32 fnc, uint32 inst, uint32 *dat);\r | |
108 | t_stat drm_svc (UNIT *uptr);\r | |
109 | t_stat drm_reset (DEVICE *dptr);\r | |
110 | \r | |
111 | /* DRM data structures\r | |
112 | \r | |
113 | drm_dev device descriptor\r | |
114 | drm_unit unit descriptor\r | |
115 | drm_reg register list\r | |
116 | */\r | |
117 | \r | |
118 | DIB drm_dib = { -1, DEV3_GDRM, 0, NULL, &drm };\r | |
119 | \r | |
120 | UNIT drm_unit = {\r | |
121 | UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,\r | |
122 | DRM_SIZE)\r | |
123 | };\r | |
124 | \r | |
125 | REG drm_reg[] = {\r | |
126 | { ORDATA (DA, drm_da, DRM_N_ADDR) },\r | |
127 | { ORDATA (CA, drm_ca, 16) },\r | |
128 | { ORDATA (WC, drm_wc, 14) },\r | |
129 | { ORDATA (PAR, drm_par, 12) },\r | |
130 | { FLDATA (RW, drm_rw, 0) },\r | |
131 | { FLDATA (ERR, drm_err, 0) },\r | |
132 | { ORDATA (STA, drm_sta, 2) },\r | |
133 | { DRDATA (FTIME, drm_ftime, 24), REG_NZ + PV_LEFT },\r | |
134 | { DRDATA (XTIME, drm_xtime, 24), REG_NZ + PV_LEFT },\r | |
135 | { FLDATA (STOP_IOE, drm_stopioe, 0) },\r | |
136 | { NULL }\r | |
137 | };\r | |
138 | \r | |
139 | DEVICE drm_dev = {\r | |
140 | "DRM", &drm_unit, drm_reg, NULL,\r | |
141 | 1, 8, DRM_N_ADDR, 1, 8, 24,\r | |
142 | NULL, NULL, &drm_reset,\r | |
143 | NULL, NULL, NULL,\r | |
144 | &drm_dib, DEV_DISABLE | DEV_DIS\r | |
145 | };\r | |
146 | \r | |
147 | /* Drum routine - EOM/SKS 3xx04 */\r | |
148 | \r | |
149 | t_stat drm (uint32 fnc, uint32 inst, uint32 *dat)\r | |
150 | {\r | |
151 | int32 t, op = inst & 07700;\r | |
152 | \r | |
153 | switch (fnc) {\r | |
154 | \r | |
155 | case IO_CONN: /* connect */\r | |
156 | if (op == 00400) return drm_reset (&drm_dev); /* EOM 404 = reset */\r | |
157 | if (op == 00500) { /* EOM 504 = read DA */\r | |
158 | if (sim_is_active (&drm_unit)) return SCPE_OK; /* must be idle */\r | |
159 | t = GET_TWORD (drm_xtime); /* get position */\r | |
160 | if (t < DRM_NUMGP) M[DRM_AD] = DRM_NUMWD - t; /* in gap? */\r | |
161 | else M[DRM_AD] = (t - DRM_NUMGP) | DRM_ADAT;/* in data */\r | |
162 | }\r | |
163 | else if (op == 00200) { /* EOM 204 = start */\r | |
164 | if (sim_is_active (&drm_unit)) return SCPE_OK; /* must be idle */\r | |
165 | drm_sta = DRM_SFET; /* state = fetch */\r | |
166 | sim_activate (&drm_unit, drm_ftime); /* activate */\r | |
167 | }\r | |
168 | else CRETINS;\r | |
169 | break;\r | |
170 | \r | |
171 | case IO_SKS: /* SKS */\r | |
172 | if (((op == 07400) && !drm_err) || /* 37404: no err */\r | |
173 | ((op == 00200) && !sim_is_active (&drm_unit))) /* 30204: idle */\r | |
174 | *dat = 1;\r | |
175 | break;\r | |
176 | \r | |
177 | default:\r | |
178 | return SCPE_IERR;\r | |
179 | }\r | |
180 | \r | |
181 | return SCPE_OK;\r | |
182 | }\r | |
183 | \r | |
184 | /* Unit service */\r | |
185 | \r | |
186 | t_stat drm_svc (UNIT *uptr)\r | |
187 | {\r | |
188 | int32 t, rda;\r | |
189 | uint32 dpc, dwd;\r | |
190 | uint32 *fbuf = uptr->filebuf;\r | |
191 | \r | |
192 | if (drm_sta != DRM_SXFR) { /* fetch drum prog? */\r | |
193 | dpc = M[DRM_PC]; /* get drum PC */\r | |
194 | dwd = M[dpc & PAMASK]; /* get drum inst */\r | |
195 | M[DRM_PC] = (dpc + 1) & PAMASK; /* update drum PC */\r | |
196 | if (drm_sta == DRM_SFCA) { /* fetch core addr? */\r | |
197 | drm_rw = DRM_GETRW (dwd); /* set op */\r | |
198 | drm_ca = dwd & PAMASK; /* set core addr */\r | |
199 | drm_sta = DRM_SFDA; /* next is disk addr */\r | |
200 | }\r | |
201 | else if (drm_sta == DRM_SFDA) { /* fetch disk addr? */\r | |
202 | drm_da = dwd & DRM_DAMASK; /* set disk addr */\r | |
203 | drm_sta = DRM_SXFR; /* next is xfer */\r | |
204 | drm_par = 0; /* init parity */\r | |
205 | rda = (drm_da & DRM_SWMASK) + (DRM_GETSC (drm_da) * DRM_NUMGP);\r | |
206 | t = rda - GET_TWORD (drm_xtime); /* difference */\r | |
207 | if (t <= 0) t = t + (DRM_NUMSC * DRM_PHYWD); /* add trk lnt */\r | |
208 | sim_activate (&drm_unit, t * drm_xtime); /* activate */\r | |
209 | }\r | |
210 | else {\r | |
211 | switch (DRM_GETOP (dwd)) {\r | |
212 | \r | |
213 | case DRM_OCX: /* cond xfr */\r | |
214 | if (drm_err) { /* error? */\r | |
215 | int_req = int_req | INT_DRM; /* req int */\r | |
216 | return SCPE_OK; /* done */\r | |
217 | }\r | |
218 | case DRM_OXF: /* transfer */\r | |
219 | drm_wc = dwd & DRM_WCMASK; /* save wc */\r | |
220 | drm_sta = DRM_SFCA; /* next state */\r | |
221 | break;\r | |
222 | \r | |
223 | case DRM_OBR: /* branch */\r | |
224 | M[DRM_PC] = dwd & PAMASK; /* new drum PC */\r | |
225 | break;\r | |
226 | \r | |
227 | case DRM_END: /* end */\r | |
228 | return SCPE_OK;\r | |
229 | \r | |
230 | case DRM_EIE: /* end, int if err */\r | |
231 | if (!drm_err) return SCPE_OK;\r | |
232 | \r | |
233 | case DRM_EIU: /* end, int uncond */\r | |
234 | int_req = int_req | INT_DRM;\r | |
235 | return SCPE_OK;\r | |
236 | } /* end switch */\r | |
237 | } /* end else sta */\r | |
238 | sim_activate (uptr, drm_ftime); /* fetch next word */\r | |
239 | } /* end if !xfr */\r | |
240 | else { /* transfer word */\r | |
241 | if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */\r | |
242 | drm_err = 1; /* error */\r | |
243 | CRETIOE (drm_stopioe, SCPE_UNATT);\r | |
244 | }\r | |
245 | if (drm_rw) { /* write? */\r | |
246 | dwd = M[drm_ca]; /* get mem word */\r | |
247 | fbuf[drm_da] = dwd; /* write to drum */\r | |
248 | if (drm_da >= uptr->hwmark) uptr->hwmark = drm_da + 1;\r | |
249 | }\r | |
250 | else { /* read */\r | |
251 | dwd = fbuf[drm_da]; /* get drum word */\r | |
252 | M[drm_ca] = dwd; /* write to mem */\r | |
253 | }\r | |
254 | drm_da = drm_da + 1; /* inc drum addr */\r | |
255 | if (drm_da >= DRM_SIZE) drm_da = 0; /* wrap */\r | |
256 | drm_ca = (drm_ca + 1) & PAMASK; /* inc core addr */\r | |
257 | drm_wc = (drm_wc - 1) & DRM_WCMASK; /* dec word cnt */\r | |
258 | drm_par = drm_par ^ (dwd >> 12); /* parity */\r | |
259 | drm_par = ((drm_par << 1) | (drm_par >> 11)) & 07777;\r | |
260 | drm_par = drm_par ^ (dwd & 07777);\r | |
261 | if (drm_wc) { /* more to do */\r | |
262 | if (drm_da & DRM_M_WD) sim_activate (uptr, drm_xtime);\r | |
263 | else sim_activate (uptr, drm_xtime * DRM_NUMGP);\r | |
264 | }\r | |
265 | else { /* end xfr */\r | |
266 | #if defined (DRM_PAR)\r | |
267 | if ((drm_da & DRM_M_WD) && drm_rw) { /* wr end mid sector? */\r | |
268 | M[drm_da] = drm_par << 12; /* clobber data */\r | |
269 | if (drm_da >= uptr->hwmark) uptr->hwmark = drm_da + 1;\r | |
270 | }\r | |
271 | #endif\r | |
272 | drm_sta = DRM_SFET; /* back to fetch */\r | |
273 | sim_activate (uptr, drm_ftime); /* schedule */\r | |
274 | } /* end else end xfr */\r | |
275 | } /* end else xfr */\r | |
276 | return SCPE_OK;\r | |
277 | }\r | |
278 | \r | |
279 | /* Reset routine */\r | |
280 | \r | |
281 | t_stat drm_reset (DEVICE *dptr)\r | |
282 | {\r | |
283 | drm_da = 0; /* clear state */\r | |
284 | drm_ca = 0;\r | |
285 | drm_wc = 0;\r | |
286 | drm_par = 0;\r | |
287 | drm_sta = 0;\r | |
288 | drm_err = 0;\r | |
289 | drm_rw = 0;\r | |
290 | int_req = int_req & ~INT_DRM; /* clear intr */\r | |
291 | sim_cancel (&drm_unit); /* deactivate */\r | |
292 | return SCPE_OK;\r | |
293 | }\r |