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First Commit of my working state
[simh.git] / SDS / sds_mux.c
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PH		 1/* sds_mux.c: SDS 940 terminal multiplexor simulator\r
2\r
3 Copyright (c) 2001-2006, Robert M Supnik\r
4\r
5 Permission is hereby granted, free of charge, to any person obtaining a\r
6 copy of this software and associated documentation files (the "Software"),\r
7 to deal in the Software without restriction, including without limitation\r
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
9 and/or sell copies of the Software, and to permit persons to whom the\r
10 Software is furnished to do so, subject to the following conditions:\r
11\r
12 The above copyright notice and this permission notice shall be included in\r
13 all copies or substantial portions of the Software.\r
14\r
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
21\r
22 Except as contained in this notice, the name of Robert M Supnik shall not be\r
23 used in advertising or otherwise to promote the sale, use or other dealings\r
24 in this Software without prior written authorization from Robert M Supnik.\r
25\r
26 mux terminal multiplexor\r
27\r
28 29-Dec-06 RMS Revised to use console conversion routines\r
29 29-Jun-05 RMS Added SET MUXLn DISCONNECT\r
30 21-Jun-05 RMS Fixed bug in SHOW CONN/STATS\r
31 05-Jan-04 RMS Revised for tmxr library changes\r
32 09-May-03 RMS Added network device flag\r
33\r
34 This module implements up to 32 individual serial interfaces, representing\r
35 either the project Genie terminal multiplexor or the SDS 940 CTE option.\r
36*/\r
37\r
38#include "sds_defs.h"\r
39#include "sim_sock.h"\r
40#include "sim_tmxr.h"\r
41#include <ctype.h>\r
42\r
43#define PROJ_GENIE (cpu_unit.flags & UNIT_GENIE)\r
44#define MUX_NUMLIN mux_desc.lines\r
45\r
46#define MUX_LINES 32 /* lines */\r
47#define MUX_FLAGS 4 /* intr per line */\r
48#define MUX_FLAGMASK (MUX_FLAGS - 1)\r
49#define MUX_SCANMAX (MUX_LINES * MUX_FLAGS) /* flags to scan */\r
50#define MUX_SCANMASK (MUX_SCANMAX - 1)\r
51#define MUX_INIT_POLL 8000\r
52#define MUXL_WAIT 500\r
53#define MUX_SETFLG(l,x) mux_flags[((l) * MUX_FLAGS) + (x)] = 1\r
54#define MUX_SETINT(x) int_req = int_req | (INT_MUXR >> (x))\r
55#define MUX_CLRINT(x) int_req = int_req & ~(INT_MUXR >> (x))\r
56\r
57/* PIN/POT */\r
58\r
59#define P_V_CHAR 16 /* char */\r
60#define P_M_CHAR 0377\r
61#define P_CHAR(x) (((x) >> P_V_CHAR) & P_M_CHAR)\r
62#define PIN_OVR 000100000 /* overrun */\r
63#define POT_NOX 000100000 /* no xmit */\r
64#define POT_XMI 000040000 /* xmit int */\r
65#define POT_GLNE 000020000 /* Genie: enable */\r
66#define POT_SCDT 000020000 /* 940: clr DTR */\r
67#define P_V_CHAN 0 /* channel */\r
68#define P_M_CHAN (MUX_LINES - 1)\r
69#define P_CHAN(x) (((x) >> P_V_CHAN) & P_M_CHAN)\r
70\r
71/* SKS 940 */\r
72\r
73#define SKS_XBE 000001000 /* xmt buf empty */\r
74#define SKS_CRO 000000400 /* carrier on */\r
75#define SKS_DSR 000000200 /* data set ready */\r
76#define SKS_CHAN(x) P_CHAN(x)\r
77\r
78/* SKS Genie */\r
79\r
80#define SKG_V_CHAN 7\r
81#define SKG_M_CHAN (MUX_LINES - 1)\r
82#define SKG_CHAN(x) (((x) >> SKG_V_CHAN) & SKG_M_CHAN)\r
83\r
84/* Flags */\r
85\r
86#define MUX_FRCV 0 /* receive */\r
87#define MUX_FXMT 1 /* transmit */\r
88#define MUX_FCRN 2 /* carrier on */\r
89#define MUX_FCRF 3 /* carrier off */\r
90\r
91/* Line status */\r
92\r
93#define MUX_SCHP 001 /* char pending */\r
94#define MUX_SOVR 002 /* overrun */\r
95#define MUX_SLNE 004 /* line enabled */\r
96#define MUX_SXIE 010 /* xmt int enab */\r
97#define MUX_SCRO 020 /* carrier on */\r
98#define MUX_SDSR 040 /* data set ready */\r
99\r
100/* Data */\r
101\r
102extern uint32 alert, int_req;\r
103extern int32 stop_invins, stop_invdev, stop_inviop;\r
104extern UNIT cpu_unit;\r
105\r
106uint8 mux_rbuf[MUX_LINES]; /* rcv buf */\r
107uint8 mux_xbuf[MUX_LINES]; /* xmt buf */\r
108uint8 mux_sta[MUX_LINES]; /* status */\r
109uint8 mux_flags[MUX_SCANMAX]; /* flags */\r
110uint32 mux_tps = 100; /* polls/second */\r
111uint32 mux_scan = 0; /* scanner */\r
112uint32 mux_slck = 0; /* scanner locked */\r
113\r
114TMLN mux_ldsc[MUX_LINES] = { 0 }; /* line descriptors */\r
115TMXR mux_desc = { MUX_LINES, 0, 0, mux_ldsc }; /* mux descriptor */\r
116\r
117t_stat mux (uint32 fnc, uint32 inst, uint32 *dat);\r
118t_stat muxi_svc (UNIT *uptr);\r
119t_stat muxo_svc (UNIT *uptr);\r
120t_stat mux_reset (DEVICE *dptr);\r
121t_stat mux_attach (UNIT *uptr, char *cptr);\r
122t_stat mux_detach (UNIT *uptr);\r
123t_stat mux_summ (FILE *st, UNIT *uptr, int32 val, void *desc);\r
124t_stat mux_show (FILE *st, UNIT *uptr, int32 val, void *desc);\r
125t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc);\r
126void mux_reset_ln (int32 ln);\r
127void mux_scan_next (void);\r
128\r
129/* MUX data structures\r
130\r
131 mux_dev MUX device descriptor\r
132 mux_unit MUX unit descriptor\r
133 mux_reg MUX register list\r
134 mux_mod MUX modifiers list\r
135*/\r
136\r
137DIB mux_dib = { -1, DEV3_GMUX, 0, NULL, &mux };\r
138\r
139REG mux_nlreg = { DRDATA (NLINES, MUX_NUMLIN, 6), PV_LEFT };\r
140\r
141UNIT mux_unit = { UDATA (&muxi_svc, UNIT_ATTABLE, 0), MUX_INIT_POLL };\r
142\r
143REG mux_reg[] = {\r
144 { BRDATA (STA, mux_sta, 8, 6, MUX_LINES) },\r
145 { BRDATA (RBUF, mux_rbuf, 8, 8, MUX_LINES) },\r
146 { BRDATA (XBUF, mux_xbuf, 8, 8, MUX_LINES) },\r
147 { BRDATA (INT, mux_flags, 8, 1, MUX_SCANMAX) },\r
148 { ORDATA (SCAN, mux_scan, 7) },\r
149 { FLDATA (SLCK, mux_slck, 0) },\r
150 { DRDATA (TPS, mux_tps, 8), REG_NZ + PV_LEFT },\r
151 { NULL }\r
152 };\r
153\r
154MTAB mux_mod[] = {\r
155 { MTAB_XTD | MTAB_VDV | MTAB_VAL, 0, "lines", "LINES",\r
156 &mux_vlines, NULL, &mux_nlreg },\r
157 { MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",\r
158 &tmxr_dscln, NULL, &mux_desc },\r
159 { UNIT_ATT, UNIT_ATT, "connections", NULL, NULL, &mux_summ },\r
160 { MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,\r
161 NULL, &mux_show, NULL },\r
162 { MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,\r
163 NULL, &mux_show, NULL },\r
164 { 0 }\r
165 };\r
166\r
167DEVICE mux_dev = {\r
168 "MUX", &mux_unit, mux_reg, mux_mod,\r
169 1, 10, 31, 1, 8, 8,\r
170 &tmxr_ex, &tmxr_dep, &mux_reset,\r
171 NULL, &mux_attach, &mux_detach,\r
172 &mux_dib, DEV_NET | DEV_DISABLE\r
173 };\r
174\r
175/* MUXL data structures\r
176\r
177 muxl_dev MUXL device descriptor\r
178 muxl_unit MUXL unit descriptor\r
179 muxl_reg MUXL register list\r
180 muxl_mod MUXL modifiers list\r
181*/\r
182\r
183UNIT muxl_unit[] = {\r
184 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
185 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
186 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
187 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
188 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
189 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
190 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
191 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
192 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
193 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
194 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
195 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
196 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
197 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
198 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
199 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
200 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
201 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
202 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
203 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
204 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
205 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
206 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
207 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
208 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
209 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
210 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
211 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
212 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
213 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
214 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },\r
215 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT }\r
216 };\r
217\r
218MTAB muxl_mod[] = {\r
219 { TT_MODE, TT_MODE_UC, "UC", "UC", NULL },\r
220 { TT_MODE, TT_MODE_7B, "7b", "7B", NULL },\r
221 { TT_MODE, TT_MODE_8B, "8b", "8B", NULL },\r
222 { TT_MODE, TT_MODE_7P, "7p", "7P", NULL },\r
223 { MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",\r
224 &tmxr_dscln, NULL, &mux_desc },\r
225 { MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",\r
226 &tmxr_set_log, &tmxr_show_log, &mux_desc },\r
227 { MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",\r
228 &tmxr_set_nolog, NULL, &mux_desc },\r
229 { 0 }\r
230 };\r
231\r
232REG muxl_reg[] = {\r
233 { URDATA (TIME, muxl_unit[0].wait, 10, 24, 0,\r
234 MUX_LINES, REG_NZ + PV_LEFT) },\r
235 { NULL }\r
236 };\r
237\r
238DEVICE muxl_dev = {\r
239 "MUXL", muxl_unit, muxl_reg, muxl_mod,\r
240 MUX_LINES, 10, 31, 1, 8, 8,\r
241 NULL, NULL, &mux_reset,\r
242 NULL, NULL, NULL,\r
243 NULL, 0\r
244 };\r
245\r
246/* MUX: IO routine */\r
247\r
248/* Mux routine - EOM 30001 or EOM 77777,2 */\r
249\r
250t_stat mux (uint32 fnc, uint32 inst, uint32 *dat)\r
251{\r
252uint32 ln;\r
253\r
254switch (fnc) {\r
255\r
256 case IO_CONN: /* connect */\r
257 if ((PROJ_GENIE && (inst == 000230001)) || /* set alert */\r
258 (!PROJ_GENIE && (inst == 020277777))) alert = POT_MUX;\r
259 else CRETINS;\r
260 break;\r
261\r
262 case IO_SKS: /* skip */\r
263 if (PROJ_GENIE && ((inst & 077770077) == 004030001)) {\r
264 ln = SKG_CHAN (inst); /* get line */\r
265 if (!sim_is_active (&muxl_unit[ln])) *dat = 1;\r
266 }\r
267 else if (!PROJ_GENIE && ((inst & 077776000) == 024076000)) {\r
268 ln = SKS_CHAN (inst); /* get line */\r
269 if (inst & (SKS_XBE|SKS_CRO|SKS_DSR)) *dat = 1;\r
270 if (((inst & SKS_XBE) && sim_is_active (&muxl_unit[ln])) ||\r
271 ((inst & SKS_CRO) && !(mux_sta[ln] & MUX_SCRO)) ||\r
272 ((inst & SKS_DSR) && !(mux_sta[ln] & MUX_SDSR)))\r
273 *dat = 0; /* no skip if fail */\r
274 }\r
275 else CRETINS; \r
276\r
277 default:\r
278 return SCPE_IERR;\r
279 } /* end case */\r
280\r
281return SCPE_OK;\r
282}\r
283\r
284/* PIN routine */\r
285\r
286t_stat pin_mux (uint32 num, uint32 *dat)\r
287{\r
288uint32 ln = mux_scan >> 2;\r
289uint32 flag = mux_scan & MUX_FLAGMASK;\r
290\r
291mux_scan = mux_scan & MUX_SCANMASK; /* mask scan */\r
292mux_flags[mux_scan] = 0; /* clear flag */\r
293if (flag == MUX_FRCV) { /* rcv event? */\r
294 *dat = ln | ((uint32) mux_rbuf[ln] << P_V_CHAR) | /* line + char + */\r
295 ((mux_sta[ln] & MUX_SOVR)? PIN_OVR: 0); /* overrun */\r
296 mux_sta[ln] = mux_sta[ln] & ~(MUX_SCHP | MUX_SOVR);\r
297 }\r
298else *dat = ln; /* just line */\r
299mux_slck = 0; /* unlock scanner */\r
300mux_scan_next (); /* kick scanner */\r
301return SCPE_OK;\r
302}\r
303\r
304t_stat pot_mux (uint32 num, uint32 *dat)\r
305{\r
306uint32 ln = P_CHAN (*dat);\r
307uint32 chr = P_CHAR (*dat);\r
308\r
309if (PROJ_GENIE && ((*dat & POT_GLNE) == 0)) { /* Genie disable? */\r
310 mux_sta[ln] = mux_sta[ln] & ~MUX_SLNE; /* clear status */\r
311 mux_ldsc[ln].rcve = 0;\r
312 }\r
313else if (!PROJ_GENIE && (*dat & POT_SCDT)) { /* SDS disable? */\r
314 if (mux_ldsc[ln].conn) { /* connected? */\r
315 tmxr_linemsg (&mux_ldsc[ln], "\r\nLine hangup\r\n");\r
316 tmxr_reset_ln (&mux_ldsc[ln]); /* reset line */\r
317 mux_reset_ln (ln); /* reset state */\r
318 MUX_SETFLG (ln, MUX_FCRF); /* set carrier off */\r
319 mux_scan_next (); /* kick scanner */\r
320 }\r
321 mux_sta[ln] = mux_sta[ln] & ~MUX_SLNE; /* clear status */\r
322 mux_ldsc[ln].rcve = 0;\r
323 }\r
324else { /* enabled */\r
325 if ((*dat & POT_NOX) == 0) { /* output char? */\r
326 mux_xbuf[ln] = chr; /* store char */\r
327 sim_activate (&muxl_unit[ln], muxl_unit[ln].wait);\r
328 }\r
329 if (*dat & POT_XMI) mux_sta[ln] = mux_sta[ln] | MUX_SXIE;\r
330 else mux_sta[ln] = mux_sta[ln] & ~MUX_SXIE;\r
331 mux_sta[ln] = mux_sta[ln] | MUX_SLNE; /* line is enabled */\r
332 mux_ldsc[ln].rcve = 1;\r
333 }\r
334return SCPE_OK;\r
335}\r
336\r
337/* Unit service - receive side\r
338\r
339 Poll all active lines for input\r
340 Poll for new connections\r
341*/\r
342\r
343t_stat muxi_svc (UNIT *uptr)\r
344{\r
345int32 ln, c, t;\r
346\r
347if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK; /* attached? */\r
348t = sim_rtcn_calb (mux_tps, TMR_MUX); /* calibrate */\r
349sim_activate (uptr, t); /* continue poll */\r
350ln = tmxr_poll_conn (&mux_desc); /* look for connect */\r
351if (ln >= 0) { /* got one? */\r
352 if (!PROJ_GENIE && (mux_sta[ln] & MUX_SLNE)) { /* modem & DTR? */\r
353 mux_sta[ln] = mux_sta[ln] | (MUX_SCRO|MUX_SDSR);/* carrier on */\r
354 MUX_SETFLG (ln, MUX_FCRN); /* set carr on flag */\r
355 mux_scan_next (); /* kick scanner */\r
356 }\r
357 mux_ldsc[ln].rcve = 1; /* set rcv enable */\r
358 }\r
359tmxr_poll_rx (&mux_desc); /* poll for input */\r
360for (ln = 0; ln < MUX_NUMLIN; ln++) { /* loop thru lines */\r
361 if (mux_ldsc[ln].conn) { /* connected? */\r
362 if (c = tmxr_getc_ln (&mux_ldsc[ln])) { /* get char */\r
363 if (mux_sta[ln] & MUX_SCHP) /* already got one? */\r
364 mux_sta[ln] = mux_sta[ln] | MUX_SOVR; /* overrun */\r
365 else mux_sta[ln] = mux_sta[ln] | MUX_SCHP; /* char pending */\r
366 if (c & SCPE_BREAK) c = 0; /* break? */\r
367 else c = sim_tt_inpcvt (c, TT_GET_MODE (muxl_unit[ln].flags));\r
368 mux_rbuf[ln] = c; /* save char */\r
369 MUX_SETFLG (ln, MUX_FRCV); /* set rcv flag */\r
370 mux_scan_next (); /* kick scanner */\r
371 }\r
372 }\r
373 else mux_sta[ln] = 0; /* disconnected */\r
374 } /* end for */\r
375return SCPE_OK;\r
376}\r
377\r
378/* Unit service - transmit side */\r
379\r
380t_stat muxo_svc (UNIT *uptr)\r
381{\r
382int32 c;\r
383uint32 ln = uptr - muxl_unit; /* line # */\r
384\r
385if (mux_ldsc[ln].conn) { /* connected? */\r
386 if (mux_ldsc[ln].xmte) { /* xmt enabled? */\r
387 c = sim_tt_outcvt (mux_xbuf[ln], TT_GET_MODE (muxl_unit[ln].flags));\r
388 if (c >= 0) tmxr_putc_ln (&mux_ldsc[ln], c); /* output char */\r
389 tmxr_poll_tx (&mux_desc); /* poll xmt */\r
390 }\r
391 else { /* buf full */\r
392 tmxr_poll_tx (&mux_desc); /* poll xmt */\r
393 sim_activate (uptr, muxl_unit[ln].wait); /* wait */\r
394 return SCPE_OK;\r
395 }\r
396 }\r
397if (mux_sta[ln] & MUX_SXIE) {\r
398 MUX_SETFLG (ln, MUX_FXMT); /* set flag */\r
399 mux_scan_next (); /* kick scanner */\r
400 }\r
401return SCPE_OK;\r
402}\r
403\r
404/* Kick scanner */\r
405\r
406void mux_scan_next (void)\r
407{\r
408int32 i;\r
409\r
410if (mux_slck) return; /* locked? */\r
411for (i = 0; i < MUX_SCANMAX; i++) { /* scan flags */\r
412 mux_scan = (mux_scan + 1) & MUX_SCANMASK; /* next flag */\r
413 if (mux_flags[mux_scan]) { /* flag set? */\r
414 mux_slck = 1; /* lock scanner */\r
415 MUX_SETINT (mux_scan & MUX_FLAGMASK); /* request int */\r
416 return;\r
417 }\r
418 }\r
419return;\r
420}\r
421\r
422/* Reset routine */\r
423\r
424t_stat mux_reset (DEVICE *dptr)\r
425{\r
426int32 i, t;\r
427\r
428if (mux_dev.flags & DEV_DIS) /* master disabled? */\r
429 muxl_dev.flags = muxl_dev.flags | DEV_DIS; /* disable lines */\r
430else muxl_dev.flags = muxl_dev.flags & ~DEV_DIS;\r
431if (mux_unit.flags & UNIT_ATT) { /* master att? */\r
432 if (!sim_is_active (&mux_unit)) {\r
433 t = sim_rtcn_init (mux_unit.wait, TMR_MUX);\r
434 sim_activate (&mux_unit, t); /* activate */\r
435 }\r
436 }\r
437else sim_cancel (&mux_unit); /* else stop */\r
438for (i = 0; i < MUX_LINES; i++) mux_reset_ln (i);\r
439for (i = 0; i < MUX_FLAGS; i++) MUX_CLRINT (i); /* clear all ints */\r
440return SCPE_OK;\r
441}\r
442\r
443/* Attach master unit */\r
444\r
445t_stat mux_attach (UNIT *uptr, char *cptr)\r
446{\r
447t_stat r;\r
448int32 t;\r
449\r
450r = tmxr_attach (&mux_desc, uptr, cptr); /* attach */\r
451if (r != SCPE_OK) return r; /* error */\r
452t = sim_rtcn_init (mux_unit.wait, TMR_MUX);\r
453sim_activate (uptr, t); /* start poll */\r
454return SCPE_OK;\r
455}\r
456\r
457/* Detach master unit */\r
458\r
459t_stat mux_detach (UNIT *uptr)\r
460{\r
461int32 i;\r
462t_stat r;\r
463\r
464r = tmxr_detach (&mux_desc, uptr); /* detach */\r
465for (i = 0; i < MUX_LINES; i++) mux_ldsc[i].rcve = 0; /* disable rcv */\r
466sim_cancel (uptr); /* stop poll */\r
467return r;\r
468}\r
469\r
470/* Show summary processor */\r
471\r
472t_stat mux_summ (FILE *st, UNIT *uptr, int32 val, void *desc)\r
473{\r
474int32 i, t;\r
475\r
476for (i = t = 0; i < MUX_LINES; i++) t = t + (mux_ldsc[i].conn != 0);\r
477if (t == 1) fprintf (st, "1 connection");\r
478else fprintf (st, "%d connections", t);\r
479return SCPE_OK;\r
480}\r
481\r
482/* SHOW CONN/STAT processor */\r
483\r
484t_stat mux_show (FILE *st, UNIT *uptr, int32 val, void *desc)\r
485{\r
486int32 i, t;\r
487\r
488for (i = t = 0; i < MUX_LINES; i++) t = t + (mux_ldsc[i].conn != 0);\r
489if (t) {\r
490 for (i = 0; i < MUX_LINES; i++) {\r
491 if (mux_ldsc[i].conn) {\r
492 if (val) tmxr_fconns (st, &mux_ldsc[i], i);\r
493 else tmxr_fstats (st, &mux_ldsc[i], i);\r
494 }\r
495 }\r
496 }\r
497else fprintf (st, "all disconnected\n");\r
498return SCPE_OK;\r
499}\r
500\r
501/* Change number of lines */\r
502\r
503t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc)\r
504{\r
505int32 newln, i, t;\r
506t_stat r;\r
507\r
508if (cptr == NULL) return SCPE_ARG;\r
509newln = get_uint (cptr, 10, MUX_LINES, &r);\r
510if ((r != SCPE_OK) || (newln == MUX_NUMLIN)) return r;\r
511if (newln == 0) return SCPE_ARG;\r
512if (newln < MUX_NUMLIN) {\r
513 for (i = newln, t = 0; i < MUX_NUMLIN; i++) t = t | mux_ldsc[i].conn;\r
514 if (t && !get_yn ("This will disconnect users; proceed [N]?", FALSE))\r
515 return SCPE_OK;\r
516 for (i = newln; i < MUX_NUMLIN; i++) {\r
517 if (mux_ldsc[i].conn) {\r
518 tmxr_linemsg (&mux_ldsc[i], "\r\nOperator disconnected line\r\n");\r
519 tmxr_reset_ln (&mux_ldsc[i]); /* reset line */\r
520 }\r
521 muxl_unit[i].flags = muxl_unit[i].flags | UNIT_DIS;\r
522 mux_reset_ln (i);\r
523 }\r
524 }\r
525else {\r
526 for (i = MUX_NUMLIN; i < newln; i++) {\r
527 muxl_unit[i].flags = muxl_unit[i].flags & ~UNIT_DIS;\r
528 mux_reset_ln (i);\r
529 }\r
530 }\r
531MUX_NUMLIN = newln;\r
532return SCPE_OK;\r
533}\r
534\r
535/* Reset an individual line */\r
536\r
537void mux_reset_ln (int32 ln)\r
538{\r
539int32 flg = ln * MUX_FLAGS;\r
540\r
541if (mux_ldsc[ln].conn) mux_sta[ln] = MUX_SCRO | MUX_SDSR;\r
542else mux_sta[ln] = 0;\r
543sim_cancel (&muxl_unit[ln]);\r
544mux_flags[flg + MUX_FRCV] = 0;\r
545mux_flags[flg + MUX_FXMT] = 0;\r
546mux_flags[flg + MUX_FCRN] = 0;\r
547mux_flags[flg + MUX_FCRF] = 0;\r
548return;\r
549}\r
Magically enhanced SIMH