projects / simh.git / blame
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| 196ba1fc PH |
1 | /* vax_fpa.c - VAX f_, d_, g_floating instructions\r |
| 2 | \r | |
| 3 | Copyright (c) 1998-2008, Robert M Supnik\r | |
| 4 | \r | |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
| 6 | copy of this software and associated documentation files (the "Software"),\r | |
| 7 | to deal in the Software without restriction, including without limitation\r | |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
| 10 | Software is furnished to do so, subject to the following conditions:\r | |
| 11 | \r | |
| 12 | The above copyright notice and this permission notice shall be included in\r | |
| 13 | all copies or substantial portions of the Software.\r | |
| 14 | \r | |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
| 21 | \r | |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r | |
| 25 | \r | |
| 26 | 28-May-08 RMS Inlined physical memory routines\r | |
| 27 | 16-May-06 RMS Fixed bug in 32b floating multiply routine\r | |
| 28 | Fixed bug in 64b extended modulus routine\r | |
| 29 | 03-May-06 RMS Fixed POLYD, POLYG to clear R4, R5\r | |
| 30 | Fixed POLYD, POLYG to set R3 correctly\r | |
| 31 | Fixed POLYD, POLYG to not exit prematurely if arg = 0\r | |
| 32 | Fixed POLYD, POLYG to do full 64b multiply\r | |
| 33 | Fixed POLYF, POLYD, POLYG to remove truncation on add\r | |
| 34 | Fixed POLYF, POLYD, POLYG to mask mul reslt to 31b/63b/63b\r | |
| 35 | Fixed fp add routine to test for zero via fraction\r | |
| 36 | to support "denormal" argument from POLYF, POLYD, POLYG\r | |
| 37 | (all reported by Tim Stark)\r | |
| 38 | 27-Sep-05 RMS Fixed bug in 32b structure definitions (from Jason Stevens)\r | |
| 39 | 30-Sep-04 RMS Comment and formating changes based on vax_octa.c\r | |
| 40 | 18-Apr-04 RMS Moved format definitions to vax_defs.h\r | |
| 41 | 19-Jun-03 RMS Simplified add algorithm\r | |
| 42 | 16-May-03 RMS Fixed bug in floating to integer convert overflow\r | |
| 43 | Fixed multiple bugs in EMODx\r | |
| 44 | Integrated 32b only code\r | |
| 45 | 05-Jul-02 RMS Changed internal routine names for C library conflict\r | |
| 46 | 17-Apr-02 RMS Fixed bug in EDIV zero quotient\r | |
| 47 | \r | |
| 48 | This module contains the instruction simulators for\r | |
| 49 | \r | |
| 50 | - 64 bit arithmetic (ASHQ, EMUL, EDIV)\r | |
| 51 | - single precision floating point\r | |
| 52 | - double precision floating point, D and G format\r | |
| 53 | */\r | |
| 54 | \r | |
| 55 | #include "vax_defs.h"\r | |
| 56 | #include <setjmp.h>\r | |
| 57 | \r | |
| 58 | extern int32 R[16];\r | |
| 59 | extern int32 PSL;\r | |
| 60 | extern int32 p1;\r | |
| 61 | extern jmp_buf save_env;\r | |
| 62 | \r | |
| 63 | #if defined (USE_INT64)\r | |
| 64 | \r | |
| 65 | #define M64 0xFFFFFFFFFFFFFFFF /* 64b */\r | |
| 66 | #define FD_FRACW (0xFFFF & ~(FD_EXP | FPSIGN))\r | |
| 67 | #define FD_FRACL (FD_FRACW | 0xFFFF0000) /* f/d fraction */\r | |
| 68 | #define G_FRACW (0xFFFF & ~(G_EXP | FPSIGN))\r | |
| 69 | #define G_FRACL (G_FRACW | 0xFFFF0000) /* g fraction */\r | |
| 70 | #define UNSCRAM(h,l) (((((t_uint64) (h)) << 48) & 0xFFFF000000000000) | \\r | |
| 71 | ((((t_uint64) (h)) << 16) & 0x0000FFFF00000000) | \\r | |
| 72 | ((((t_uint64) (l)) << 16) & 0x00000000FFFF0000) | \\r | |
| 73 | ((((t_uint64) (l)) >> 16) & 0x000000000000FFFF))\r | |
| 74 | #define CONCAT(h,l) ((((t_uint64) (h)) << 32) | ((uint32) (l)))\r | |
| 75 | \r | |
| 76 | typedef struct {\r | |
| 77 | int32 sign;\r | |
| 78 | int32 exp;\r | |
| 79 | t_uint64 frac;\r | |
| 80 | } UFP;\r | |
| 81 | \r | |
| 82 | #define UF_NM 0x8000000000000000 /* normalized */\r | |
| 83 | #define UF_FRND 0x0000008000000000 /* F round */\r | |
| 84 | #define UF_DRND 0x0000000000000080 /* D round */\r | |
| 85 | #define UF_GRND 0x0000000000000400 /* G round */\r | |
| 86 | #define UF_V_NM 63\r | |
| 87 | #define UF_V_FDHI 40\r | |
| 88 | #define UF_V_FDLO (UF_V_FDHI - 32)\r | |
| 89 | #define UF_V_GHI 43\r | |
| 90 | #define UF_V_GLO (UF_V_GHI - 32)\r | |
| 91 | #define UF_GETFDHI(x) (int32) ((((x) >> (16 + UF_V_FDHI)) & FD_FRACW) | \\r | |
| 92 | (((x) >> (UF_V_FDHI - 16)) & ~0xFFFF))\r | |
| 93 | #define UF_GETFDLO(x) (int32) ((((x) >> (16 + UF_V_FDLO)) & 0xFFFF) | \\r | |
| 94 | (((x) << (16 - UF_V_FDLO)) & ~0xFFFF))\r | |
| 95 | #define UF_GETGHI(x) (int32) ((((x) >> (16 + UF_V_GHI)) & G_FRACW) | \\r | |
| 96 | (((x) >> (UF_V_GHI - 16)) & ~0xFFFF))\r | |
| 97 | #define UF_GETGLO(x) (int32) ((((x) >> (16 + UF_V_GLO)) & 0xFFFF) | \\r | |
| 98 | (((x) << (16 - UF_V_GLO)) & ~0xFFFF))\r | |
| 99 | \r | |
| 100 | void unpackf (int32 hi, UFP *a);\r | |
| 101 | void unpackd (int32 hi, int32 lo, UFP *a);\r | |
| 102 | void unpackg (int32 hi, int32 lo, UFP *a);\r | |
| 103 | void norm (UFP *a);\r | |
| 104 | int32 rpackfd (UFP *a, int32 *rh);\r | |
| 105 | int32 rpackg (UFP *a, int32 *rh);\r | |
| 106 | void vax_fadd (UFP *a, UFP *b);\r | |
| 107 | void vax_fmul (UFP *a, UFP *b, t_bool qd, int32 bias, uint32 mhi, uint32 mlo);\r | |
| 108 | void vax_fdiv (UFP *b, UFP *a, int32 prec, int32 bias);\r | |
| 109 | void vax_fmod (UFP *a, int32 bias, int32 *intgr, int32 *flg);\r | |
| 110 | \r | |
| 111 | /* Quadword arithmetic shift\r | |
| 112 | \r | |
| 113 | opnd[0] = shift count (cnt.rb)\r | |
| 114 | opnd[1:2] = source (src.rq)\r | |
| 115 | opnd[3:4] = destination (dst.wq)\r | |
| 116 | */\r | |
| 117 | \r | |
| 118 | int32 op_ashq (int32 *opnd, int32 *rh, int32 *flg)\r | |
| 119 | {\r | |
| 120 | t_int64 src, r;\r | |
| 121 | int32 sc = opnd[0];\r | |
| 122 | \r | |
| 123 | src = CONCAT (opnd[2], opnd[1]); /* build src */\r | |
| 124 | if (sc & BSIGN) { /* right shift? */\r | |
| 125 | *flg = 0; /* no ovflo */\r | |
| 126 | sc = 0x100 - sc; /* |shift| */\r | |
| 127 | if (sc > 63) r = (opnd[2] & LSIGN)? -1: 0; /* sc > 63? */\r | |
| 128 | else r = src >> sc;\r | |
| 129 | }\r | |
| 130 | else {\r | |
| 131 | if (sc > 63) { /* left shift */\r | |
| 132 | r = 0; /* sc > 63? */\r | |
| 133 | *flg = (src != 0); /* ovflo test */\r | |
| 134 | }\r | |
| 135 | else {\r | |
| 136 | r = src << sc; /* do shift */\r | |
| 137 | *flg = (src != (r >> sc)); /* ovflo test */\r | |
| 138 | }\r | |
| 139 | }\r | |
| 140 | *rh = (int32) ((r >> 32) & LMASK); /* hi result */\r | |
| 141 | return ((int32) (r & LMASK)); /* lo result */\r | |
| 142 | }\r | |
| 143 | \r | |
| 144 | /* Extended multiply subroutine */\r | |
| 145 | \r | |
| 146 | int32 op_emul (int32 mpy, int32 mpc, int32 *rh)\r | |
| 147 | {\r | |
| 148 | t_int64 lmpy = mpy;\r | |
| 149 | t_int64 lmpc = mpc;\r | |
| 150 | \r | |
| 151 | lmpy = lmpy * lmpc;\r | |
| 152 | *rh = (int32) ((lmpy >> 32) & LMASK);\r | |
| 153 | return ((int32) (lmpy & LMASK));\r | |
| 154 | }\r | |
| 155 | \r | |
| 156 | /* Extended divide\r | |
| 157 | \r | |
| 158 | opnd[0] = divisor (non-zero)\r | |
| 159 | opnd[1:2] = dividend\r | |
| 160 | */\r | |
| 161 | \r | |
| 162 | int32 op_ediv (int32 *opnd, int32 *rh, int32 *flg)\r | |
| 163 | {\r | |
| 164 | t_int64 ldvd, ldvr;\r | |
| 165 | int32 quo, rem;\r | |
| 166 | \r | |
| 167 | *flg = CC_V; /* assume error */\r | |
| 168 | *rh = 0;\r | |
| 169 | ldvr = ((opnd[0] & LSIGN)? -opnd[0]: opnd[0]) & LMASK; /* |divisor| */\r | |
| 170 | ldvd = CONCAT (opnd[2], opnd[1]); /* 64b dividend */\r | |
| 171 | if (opnd[2] & LSIGN) ldvd = -ldvd; /* |dividend| */\r | |
| 172 | if (((ldvd >> 32) & LMASK) >= ldvr) return opnd[1]; /* divide work? */\r | |
| 173 | quo = (int32) (ldvd / ldvr); /* do divide */\r | |
| 174 | rem = (int32) (ldvd % ldvr);\r | |
| 175 | if ((opnd[0] ^ opnd[2]) & LSIGN) { /* result -? */\r | |
| 176 | quo = -quo; /* negate */\r | |
| 177 | if (quo && ((quo & LSIGN) == 0)) return opnd[1]; /* right sign? */\r | |
| 178 | }\r | |
| 179 | else if (quo & LSIGN) return opnd[1];\r | |
| 180 | if (opnd[2] & LSIGN) rem = -rem; /* sign of rem */\r | |
| 181 | *flg = 0; /* no overflow */\r | |
| 182 | *rh = rem & LMASK; /* set rem */\r | |
| 183 | return (quo & LMASK); /* return quo */\r | |
| 184 | }\r | |
| 185 | \r | |
| 186 | /* Compare floating */\r | |
| 187 | \r | |
| 188 | int32 op_cmpfd (int32 h1, int32 l1, int32 h2, int32 l2)\r | |
| 189 | {\r | |
| 190 | t_uint64 n1, n2;\r | |
| 191 | \r | |
| 192 | if ((h1 & FD_EXP) == 0) {\r | |
| 193 | if (h1 & FPSIGN) RSVD_OPND_FAULT;\r | |
| 194 | h1 = l1 = 0;\r | |
| 195 | }\r | |
| 196 | if ((h2 & FD_EXP) == 0) {\r | |
| 197 | if (h2 & FPSIGN) RSVD_OPND_FAULT;\r | |
| 198 | h2 = l2 = 0;\r | |
| 199 | }\r | |
| 200 | if ((h1 ^ h2) & FPSIGN) return ((h1 & FPSIGN)? CC_N: 0);\r | |
| 201 | n1 = UNSCRAM (h1, l1);\r | |
| 202 | n2 = UNSCRAM (h2, l2);\r | |
| 203 | if (n1 == n2) return CC_Z;\r | |
| 204 | return (((n1 < n2) ^ ((h1 & FPSIGN) != 0))? CC_N: 0);\r | |
| 205 | }\r | |
| 206 | \r | |
| 207 | int32 op_cmpg (int32 h1, int32 l1, int32 h2, int32 l2)\r | |
| 208 | {\r | |
| 209 | t_uint64 n1, n2;\r | |
| 210 | \r | |
| 211 | if ((h1 & G_EXP) == 0) {\r | |
| 212 | if (h1 & FPSIGN) RSVD_OPND_FAULT;\r | |
| 213 | h1 = l1 = 0;\r | |
| 214 | }\r | |
| 215 | if ((h2 & G_EXP) == 0) {\r | |
| 216 | if (h2 & FPSIGN) RSVD_OPND_FAULT;\r | |
| 217 | h2 = l2 = 0;\r | |
| 218 | }\r | |
| 219 | if ((h1 ^ h2) & FPSIGN) return ((h1 & FPSIGN)? CC_N: 0);\r | |
| 220 | n1 = UNSCRAM (h1, l1);\r | |
| 221 | n2 = UNSCRAM (h2, l2);\r | |
| 222 | if (n1 == n2) return CC_Z;\r | |
| 223 | return (((n1 < n2) ^ ((h1 & FPSIGN) != 0))? CC_N: 0);\r | |
| 224 | }\r | |
| 225 | \r | |
| 226 | /* Integer to floating convert */\r | |
| 227 | \r | |
| 228 | int32 op_cvtifdg (int32 val, int32 *rh, int32 opc)\r | |
| 229 | {\r | |
| 230 | UFP a;\r | |
| 231 | \r | |
| 232 | if (val == 0) {\r | |
| 233 | if (rh) *rh = 0;\r | |
| 234 | return 0;\r | |
| 235 | }\r | |
| 236 | if (val < 0) {\r | |
| 237 | a.sign = FPSIGN;\r | |
| 238 | val = - val;\r | |
| 239 | }\r | |
| 240 | else a.sign = 0;\r | |
| 241 | a.exp = 32 + ((opc & 0x100)? G_BIAS: FD_BIAS);\r | |
| 242 | a.frac = ((t_uint64) val) << (UF_V_NM - 31);\r | |
| 243 | norm (&a);\r | |
| 244 | if (opc & 0x100) return rpackg (&a, rh);\r | |
| 245 | return rpackfd (&a, rh);\r | |
| 246 | }\r | |
| 247 | \r | |
| 248 | /* Floating to integer convert */\r | |
| 249 | \r | |
| 250 | int32 op_cvtfdgi (int32 *opnd, int32 *flg, int32 opc)\r | |
| 251 | {\r | |
| 252 | UFP a;\r | |
| 253 | int32 lnt = opc & 03;\r | |
| 254 | int32 ubexp;\r | |
| 255 | static t_uint64 maxv[4] = { 0x7F, 0x7FFF, 0x7FFFFFFF, 0x7FFFFFFF };\r | |
| 256 | \r | |
| 257 | *flg = 0;\r | |
| 258 | if (opc & 0x100) {\r | |
| 259 | unpackg (opnd[0], opnd[1], &a);\r | |
| 260 | ubexp = a.exp - G_BIAS;\r | |
| 261 | }\r | |
| 262 | else {\r | |
| 263 | if (opc & 0x20) unpackd (opnd[0], opnd[1], &a);\r | |
| 264 | else unpackf (opnd[0], &a);\r | |
| 265 | ubexp = a.exp - FD_BIAS;\r | |
| 266 | }\r | |
| 267 | if ((a.exp == 0) || (ubexp < 0)) return 0;\r | |
| 268 | if (ubexp <= UF_V_NM) {\r | |
| 269 | a.frac = a.frac >> (UF_V_NM - ubexp); /* leave rnd bit */\r | |
| 270 | if ((opc & 03) == 03) a.frac = a.frac + 1; /* if CVTR, round */\r | |
| 271 | a.frac = a.frac >> 1; /* now justified */\r | |
| 272 | if (a.frac > (maxv[lnt] + (a.sign? 1: 0))) *flg = CC_V;\r | |
| 273 | }\r | |
| 274 | else {\r | |
| 275 | *flg = CC_V; /* set overflow */\r | |
| 276 | if (ubexp > (UF_V_NM + 32)) return 0;\r | |
| 277 | a.frac = a.frac << (ubexp - UF_V_NM - 1); /* no rnd bit */\r | |
| 278 | }\r | |
| 279 | return ((int32) ((a.sign? (a.frac ^ LMASK) + 1: a.frac) & LMASK));\r | |
| 280 | }\r | |
| 281 | \r | |
| 282 | /* Extended modularize\r | |
| 283 | \r | |
| 284 | One of three floating point instructions dropped from the architecture,\r | |
| 285 | EMOD presents two sets of complications. First, it requires an extended\r | |
| 286 | fraction multiply, with precise (and unusual) truncation conditions.\r | |
| 287 | Second, it has two write operands, a dubious distinction it shares\r | |
| 288 | with EDIV.\r | |
| 289 | */\r | |
| 290 | \r | |
| 291 | int32 op_emodf (int32 *opnd, int32 *intgr, int32 *flg)\r | |
| 292 | {\r | |
| 293 | UFP a, b;\r | |
| 294 | \r | |
| 295 | unpackf (opnd[0], &a); /* unpack operands */\r | |
| 296 | unpackf (opnd[2], &b);\r | |
| 297 | a.frac = a.frac | (((t_uint64) opnd[1]) << 32); /* extend src1 */\r | |
| 298 | vax_fmul (&a, &b, 0, FD_BIAS, 0, LMASK); /* multiply */\r | |
| 299 | vax_fmod (&a, FD_BIAS, intgr, flg); /* sep int & frac */\r | |
| 300 | return rpackfd (&a, NULL); /* return frac */\r | |
| 301 | }\r | |
| 302 | \r | |
| 303 | int32 op_emodd (int32 *opnd, int32 *flo, int32 *intgr, int32 *flg)\r | |
| 304 | {\r | |
| 305 | UFP a, b;\r | |
| 306 | \r | |
| 307 | unpackd (opnd[0], opnd[1], &a); /* unpack operands */\r | |
| 308 | unpackd (opnd[3], opnd[4], &b);\r | |
| 309 | a.frac = a.frac | opnd[2]; /* extend src1 */\r | |
| 310 | vax_fmul (&a, &b, 1, FD_BIAS, 0, 0); /* multiply */\r | |
| 311 | vax_fmod (&a, FD_BIAS, intgr, flg); /* sep int & frac */\r | |
| 312 | return rpackfd (&a, flo); /* return frac */\r | |
| 313 | }\r | |
| 314 | \r | |
| 315 | int32 op_emodg (int32 *opnd, int32 *flo, int32 *intgr, int32 *flg)\r | |
| 316 | {\r | |
| 317 | UFP a, b;\r | |
| 318 | \r | |
| 319 | unpackg (opnd[0], opnd[1], &a); /* unpack operands */\r | |
| 320 | unpackg (opnd[3], opnd[4], &b);\r | |
| 321 | a.frac = a.frac | (opnd[2] >> 5); /* extend src1 */\r | |
| 322 | vax_fmul (&a, &b, 1, G_BIAS, 0, 0); /* multiply */\r | |
| 323 | vax_fmod (&a, G_BIAS, intgr, flg); /* sep int & frac */\r | |
| 324 | return rpackg (&a, flo); /* return frac */\r | |
| 325 | }\r | |
| 326 | \r | |
| 327 | /* Unpacked floating point routines */\r | |
| 328 | \r | |
| 329 | void vax_fadd (UFP *a, UFP *b)\r | |
| 330 | {\r | |
| 331 | int32 ediff;\r | |
| 332 | UFP t;\r | |
| 333 | \r | |
| 334 | if (a->frac == 0) { /* s1 = 0? */\r | |
| 335 | *a = *b;\r | |
| 336 | return;\r | |
| 337 | }\r | |
| 338 | if (b->frac == 0) return; /* s2 = 0? */\r | |
| 339 | if ((a->exp < b->exp) || /* |s1| < |s2|? swap */\r | |
| 340 | ((a->exp == b->exp) && (a->frac < b->frac))) {\r | |
| 341 | t = *a;\r | |
| 342 | *a = *b;\r | |
| 343 | *b = t;\r | |
| 344 | }\r | |
| 345 | ediff = a->exp - b->exp; /* exp diff */\r | |
| 346 | if (a->sign ^ b->sign) { /* eff sub? */\r | |
| 347 | if (ediff) { /* exp diff? */\r | |
| 348 | if (ediff > 63) b->frac = M64; /* retain sticky */\r | |
| 349 | else b->frac = ((-((t_int64) b->frac) >> ediff) | /* denormalize */\r | |
| 350 | (M64 << (64 - ediff))); /* preserve sign */\r | |
| 351 | a->frac = a->frac + b->frac; /* add frac */\r | |
| 352 | }\r | |
| 353 | else a->frac = a->frac - b->frac; /* sub frac */\r | |
| 354 | norm (a); /* normalize */\r | |
| 355 | }\r | |
| 356 | else {\r | |
| 357 | if (ediff > 63) b->frac = 0; /* add */\r | |
| 358 | else if (ediff) b->frac = b->frac >> ediff; /* denormalize */\r | |
| 359 | a->frac = a->frac + b->frac; /* add frac */\r | |
| 360 | if (a->frac < b->frac) { /* chk for carry */\r | |
| 361 | a->frac = UF_NM | (a->frac >> 1); /* shift in carry */\r | |
| 362 | a->exp = a->exp + 1; /* skip norm */\r | |
| 363 | }\r | |
| 364 | }\r | |
| 365 | return;\r | |
| 366 | }\r | |
| 367 | \r | |
| 368 | /* Floating multiply - 64b * 64b with cross products */\r | |
| 369 | \r | |
| 370 | void vax_fmul (UFP *a, UFP *b, t_bool qd, int32 bias, uint32 mhi, uint32 mlo)\r | |
| 371 | {\r | |
| 372 | t_uint64 ah, bh, al, bl, rhi, rlo, rmid1, rmid2;\r | |
| 373 | t_uint64 mask = (((t_uint64) mhi) << 32) | ((t_uint64) mlo);\r | |
| 374 | \r | |
| 375 | if ((a->exp == 0) || (b->exp == 0)) { /* zero argument? */\r | |
| 376 | a->frac = a->sign = a->exp = 0; /* result is zero */\r | |
| 377 | return;\r | |
| 378 | }\r | |
| 379 | a->sign = a->sign ^ b->sign; /* sign of result */\r | |
| 380 | a->exp = a->exp + b->exp - bias; /* add exponents */\r | |
| 381 | ah = (a->frac >> 32) & LMASK; /* split operands */\r | |
| 382 | bh = (b->frac >> 32) & LMASK; /* into 32b chunks */\r | |
| 383 | rhi = ah * bh; /* high result */\r | |
| 384 | if (qd) { /* 64b needed? */\r | |
| 385 | al = a->frac & LMASK;\r | |
| 386 | bl = b->frac & LMASK;\r | |
| 387 | rmid1 = ah * bl;\r | |
| 388 | rmid2 = al * bh;\r | |
| 389 | rlo = al * bl;\r | |
| 390 | rhi = rhi + ((rmid1 >> 32) & LMASK) + ((rmid2 >> 32) & LMASK);\r | |
| 391 | rmid1 = rlo + (rmid1 << 32); /* add mid1 to lo */\r | |
| 392 | if (rmid1 < rlo) rhi = rhi + 1; /* carry? incr hi */\r | |
| 393 | rmid2 = rmid1 + (rmid2 << 32); /* add mid2 to lo */\r | |
| 394 | if (rmid2 < rmid1) rhi = rhi + 1; /* carry? incr hi */\r | |
| 395 | }\r | |
| 396 | a->frac = rhi & ~mask;\r | |
| 397 | norm (a); /* normalize */\r | |
| 398 | return;\r | |
| 399 | }\r | |
| 400 | \r | |
| 401 | /* Floating modulus - there are three cases\r | |
| 402 | \r | |
| 403 | exp <= bias - integer is 0, fraction is input,\r | |
| 404 | no overflow\r | |
| 405 | bias < exp <= bias+64 - separate integer and fraction,\r | |
| 406 | integer overflow may occur\r | |
| 407 | bias+64 < exp - result is integer, fraction is 0\r | |
| 408 | integer overflow\r | |
| 409 | */\r | |
| 410 | \r | |
| 411 | void vax_fmod (UFP *a, int32 bias, int32 *intgr, int32 *flg)\r | |
| 412 | {\r | |
| 413 | if (a->exp <= bias) *intgr = *flg = 0; /* 0 or <1? int = 0 */\r | |
| 414 | else if (a->exp <= (bias + 64)) { /* in range [1,64]? */\r | |
| 415 | *intgr = (int32) (a->frac >> (64 - (a->exp - bias)));\r | |
| 416 | if ((a->exp > (bias + 32)) || /* test ovflo */\r | |
| 417 | ((a->exp == (bias + 32)) &&\r | |
| 418 | (((uint32) *intgr) > (a->sign? 0x80000000: 0x7FFFFFFF))))\r | |
| 419 | *flg = CC_V;\r | |
| 420 | else *flg = 0;\r | |
| 421 | if (a->sign) *intgr = -*intgr; /* -? comp int */\r | |
| 422 | if (a->exp == (bias + 64)) a->frac = 0; /* special case 64 */\r | |
| 423 | else a->frac = a->frac << (a->exp - bias);\r | |
| 424 | a->exp = bias;\r | |
| 425 | }\r | |
| 426 | else {\r | |
| 427 | *intgr = 0; /* out of range */\r | |
| 428 | a->frac = a->sign = a->exp = 0; /* result 0 */\r | |
| 429 | *flg = CC_V; /* overflow */\r | |
| 430 | }\r | |
| 431 | norm (a); /* normalize */\r | |
| 432 | return;\r | |
| 433 | }\r | |
| 434 | \r | |
| 435 | /* Floating divide\r | |
| 436 | Needs to develop at least one rounding bit. Since the first\r | |
| 437 | divide step can fail, caller should specify 2 more bits than\r | |
| 438 | the precision of the fraction.\r | |
| 439 | */\r | |
| 440 | \r | |
| 441 | void vax_fdiv (UFP *a, UFP *b, int32 prec, int32 bias)\r | |
| 442 | {\r | |
| 443 | int32 i;\r | |
| 444 | t_uint64 quo = 0;\r | |
| 445 | \r | |
| 446 | if (a->exp == 0) FLT_DZRO_FAULT; /* divr = 0? */\r | |
| 447 | if (b->exp == 0) return; /* divd = 0? */\r | |
| 448 | b->sign = b->sign ^ a->sign; /* result sign */\r | |
| 449 | b->exp = b->exp - a->exp + bias + 1; /* unbiased exp */\r | |
| 450 | a->frac = a->frac >> 1; /* allow 1 bit left */\r | |
| 451 | b->frac = b->frac >> 1;\r | |
| 452 | for (i = 0; (i < prec) && b->frac; i++) { /* divide loop */\r | |
| 453 | quo = quo << 1; /* shift quo */\r | |
| 454 | if (b->frac >= a->frac) { /* div step ok? */\r | |
| 455 | b->frac = b->frac - a->frac; /* subtract */\r | |
| 456 | quo = quo + 1; /* quo bit = 1 */\r | |
| 457 | }\r | |
| 458 | b->frac = b->frac << 1; /* shift divd */\r | |
| 459 | }\r | |
| 460 | b->frac = quo << (UF_V_NM - i + 1); /* shift quo */\r | |
| 461 | norm (b); /* normalize */\r | |
| 462 | return;\r | |
| 463 | }\r | |
| 464 | \r | |
| 465 | /* Support routines */\r | |
| 466 | \r | |
| 467 | void unpackf (int32 hi, UFP *r)\r | |
| 468 | {\r | |
| 469 | r->sign = hi & FPSIGN; /* get sign */\r | |
| 470 | r->exp = FD_GETEXP (hi); /* get exponent */\r | |
| 471 | if (r->exp == 0) { /* exp = 0? */\r | |
| 472 | if (r->sign) RSVD_OPND_FAULT; /* if -, rsvd op */\r | |
| 473 | r->frac = 0; /* else 0 */\r | |
| 474 | return;\r | |
| 475 | }\r | |
| 476 | hi = (((hi & FD_FRACW) | FD_HB) << 16) | ((hi >> 16) & 0xFFFF);\r | |
| 477 | r->frac = ((t_uint64) hi) << (32 + UF_V_FDLO);\r | |
| 478 | return;\r | |
| 479 | }\r | |
| 480 | \r | |
| 481 | void unpackd (int32 hi, int32 lo, UFP *r)\r | |
| 482 | {\r | |
| 483 | r->sign = hi & FPSIGN; /* get sign */\r | |
| 484 | r->exp = FD_GETEXP (hi); /* get exponent */\r | |
| 485 | if (r->exp == 0) { /* exp = 0? */\r | |
| 486 | if (r->sign) RSVD_OPND_FAULT; /* if -, rsvd op */\r | |
| 487 | r->frac = 0; /* else 0 */\r | |
| 488 | return;\r | |
| 489 | }\r | |
| 490 | hi = (hi & FD_FRACL) | FD_HB; /* canonical form */\r | |
| 491 | r->frac = UNSCRAM (hi, lo) << UF_V_FDLO; /* guard bits */\r | |
| 492 | return;\r | |
| 493 | }\r | |
| 494 | \r | |
| 495 | void unpackg (int32 hi, int32 lo, UFP *r)\r | |
| 496 | {\r | |
| 497 | r->sign = hi & FPSIGN; /* get sign */\r | |
| 498 | r->exp = G_GETEXP (hi); /* get exponent */\r | |
| 499 | if (r->exp == 0) { /* exp = 0? */\r | |
| 500 | if (r->sign) RSVD_OPND_FAULT; /* if -, rsvd op */\r | |
| 501 | r->frac = 0; /* else 0 */\r | |
| 502 | return;\r | |
| 503 | }\r | |
| 504 | hi = (hi & G_FRACL) | G_HB; /* canonical form */\r | |
| 505 | r->frac = UNSCRAM (hi, lo) << UF_V_GLO; /* guard bits */\r | |
| 506 | return;\r | |
| 507 | }\r | |
| 508 | \r | |
| 509 | void norm (UFP *r)\r | |
| 510 | {\r | |
| 511 | int32 i;\r | |
| 512 | static t_uint64 normmask[5] = {\r | |
| 513 | 0xc000000000000000, 0xf000000000000000, 0xff00000000000000,\r | |
| 514 | 0xffff000000000000, 0xffffffff00000000\r | |
| 515 | };\r | |
| 516 | static int32 normtab[6] = { 1, 2, 4, 8, 16, 32};\r | |
| 517 | \r | |
| 518 | if (r->frac == 0) { /* if fraction = 0 */\r | |
| 519 | r->sign = r->exp = 0; /* result is 0 */\r | |
| 520 | return;\r | |
| 521 | }\r | |
| 522 | while ((r->frac & UF_NM) == 0) { /* normalized? */\r | |
| 523 | for (i = 0; i < 5; i++) { /* find first 1 */\r | |
| 524 | if (r->frac & normmask[i]) break;\r | |
| 525 | }\r | |
| 526 | r->frac = r->frac << normtab[i]; /* shift frac */\r | |
| 527 | r->exp = r->exp - normtab[i]; /* decr exp */\r | |
| 528 | }\r | |
| 529 | return;\r | |
| 530 | }\r | |
| 531 | \r | |
| 532 | int32 rpackfd (UFP *r, int32 *rh)\r | |
| 533 | {\r | |
| 534 | if (rh) *rh = 0; /* assume 0 */\r | |
| 535 | if (r->frac == 0) return 0; /* result 0? */\r | |
| 536 | r->frac = r->frac + (rh? UF_DRND: UF_FRND); /* round */\r | |
| 537 | if ((r->frac & UF_NM) == 0) { /* carry out? */\r | |
| 538 | r->frac = r->frac >> 1; /* renormalize */\r | |
| 539 | r->exp = r->exp + 1;\r | |
| 540 | }\r | |
| 541 | if (r->exp > (int32) FD_M_EXP) FLT_OVFL_FAULT; /* ovflo? fault */\r | |
| 542 | if (r->exp <= 0) { /* underflow? */\r | |
| 543 | if (PSL & PSW_FU) FLT_UNFL_FAULT; /* fault if fu */\r | |
| 544 | return 0; /* else 0 */\r | |
| 545 | }\r | |
| 546 | if (rh) *rh = UF_GETFDLO (r->frac); /* get low */\r | |
| 547 | return r->sign | (r->exp << FD_V_EXP) | UF_GETFDHI (r->frac);\r | |
| 548 | }\r | |
| 549 | \r | |
| 550 | int32 rpackg (UFP *r, int32 *rh)\r | |
| 551 | {\r | |
| 552 | *rh = 0; /* assume 0 */\r | |
| 553 | if (r->frac == 0) return 0; /* result 0? */\r | |
| 554 | r->frac = r->frac + UF_GRND; /* round */\r | |
| 555 | if ((r->frac & UF_NM) == 0) { /* carry out? */\r | |
| 556 | r->frac = r->frac >> 1; /* renormalize */\r | |
| 557 | r->exp = r->exp + 1;\r | |
| 558 | }\r | |
| 559 | if (r->exp > (int32) G_M_EXP) FLT_OVFL_FAULT; /* ovflo? fault */\r | |
| 560 | if (r->exp <= 0) { /* underflow? */\r | |
| 561 | if (PSL & PSW_FU) FLT_UNFL_FAULT; /* fault if fu */\r | |
| 562 | return 0; /* else 0 */\r | |
| 563 | }\r | |
| 564 | if (rh) *rh = UF_GETGLO (r->frac); /* get low */\r | |
| 565 | return r->sign | (r->exp << G_V_EXP) | UF_GETGHI (r->frac);\r | |
| 566 | }\r | |
| 567 | \r | |
| 568 | #else /* 32b code */\r | |
| 569 | \r | |
| 570 | #define WORDSWAP(x) ((((x) & WMASK) << 16) | (((x) >> 16) & WMASK))\r | |
| 571 | \r | |
| 572 | typedef struct {\r | |
| 573 | uint32 lo;\r | |
| 574 | uint32 hi;\r | |
| 575 | } UDP;\r | |
| 576 | \r | |
| 577 | typedef struct {\r | |
| 578 | int32 sign;\r | |
| 579 | int32 exp;\r | |
| 580 | UDP frac;\r | |
| 581 | } UFP;\r | |
| 582 | \r | |
| 583 | #define UF_NM_H 0x80000000 /* normalized */\r | |
| 584 | #define UF_FRND_H 0x00000080 /* F round */\r | |
| 585 | #define UF_FRND_L 0x00000000\r | |
| 586 | #define UF_DRND_H 0x00000000 /* D round */\r | |
| 587 | #define UF_DRND_L 0x00000080\r | |
| 588 | #define UF_GRND_H 0x00000000 /* G round */\r | |
| 589 | #define UF_GRND_L 0x00000400\r | |
| 590 | #define UF_V_NM 63\r | |
| 591 | \r | |
| 592 | void unpackf (uint32 hi, UFP *a);\r | |
| 593 | void unpackd (uint32 hi, uint32 lo, UFP *a);\r | |
| 594 | void unpackg (uint32 hi, uint32 lo, UFP *a);\r | |
| 595 | void norm (UFP *a);\r | |
| 596 | int32 rpackfd (UFP *a, int32 *rh);\r | |
| 597 | int32 rpackg (UFP *a, int32 *rh);\r | |
| 598 | void vax_fadd (UFP *a, UFP *b);\r | |
| 599 | void vax_fmul (UFP *a, UFP *b, t_bool qd, int32 bias, uint32 mhi, uint32 mlo);\r | |
| 600 | void vax_fmod (UFP *a, int32 bias, int32 *intgr, int32 *flg);\r | |
| 601 | void vax_fdiv (UFP *b, UFP *a, int32 prec, int32 bias);\r | |
| 602 | void dp_add (UDP *a, UDP *b);\r | |
| 603 | void dp_inc (UDP *a);\r | |
| 604 | void dp_sub (UDP *a, UDP *b);\r | |
| 605 | void dp_imul (uint32 a, uint32 b, UDP *r);\r | |
| 606 | void dp_lsh (UDP *a, uint32 sc);\r | |
| 607 | void dp_rsh (UDP *a, uint32 sc);\r | |
| 608 | void dp_rsh_s (UDP *a, uint32 sc, uint32 neg);\r | |
| 609 | void dp_neg (UDP *a);\r | |
| 610 | int32 dp_cmp (UDP *a, UDP *b);\r | |
| 611 | \r | |
| 612 | /* Quadword arithmetic shift\r | |
| 613 | \r | |
| 614 | opnd[0] = shift count (cnt.rb)\r | |
| 615 | opnd[1:2] = source (src.rq)\r | |
| 616 | opnd[3:4] = destination (dst.wq)\r | |
| 617 | */\r | |
| 618 | \r | |
| 619 | int32 op_ashq (int32 *opnd, int32 *rh, int32 *flg)\r | |
| 620 | {\r | |
| 621 | UDP r, sr;\r | |
| 622 | uint32 sc = opnd[0];\r | |
| 623 | \r | |
| 624 | r.lo = opnd[1]; /* get source */\r | |
| 625 | r.hi = opnd[2];\r | |
| 626 | *flg = 0; /* assume no ovflo */\r | |
| 627 | if (sc & BSIGN) /* right shift? */\r | |
| 628 | dp_rsh_s (&r, 0x100 - sc, r.hi & LSIGN); /* signed right */\r | |
| 629 | else {\r | |
| 630 | dp_lsh (&r, sc); /* left shift */\r | |
| 631 | sr = r; /* copy result */\r | |
| 632 | dp_rsh_s (&sr, sc, sr.hi & LSIGN); /* signed right */\r | |
| 633 | if ((sr.hi != ((uint32) opnd[2])) || /* reshift != orig? */\r | |
| 634 | (sr.lo != ((uint32) opnd[1]))) *flg = 1; /* overflow */\r | |
| 635 | }\r | |
| 636 | *rh = r.hi; /* hi result */\r | |
| 637 | return r.lo; /* lo result */\r | |
| 638 | }\r | |
| 639 | \r | |
| 640 | /* Extended multiply subroutine */\r | |
| 641 | \r | |
| 642 | int32 op_emul (int32 mpy, int32 mpc, int32 *rh)\r | |
| 643 | {\r | |
| 644 | UDP r;\r | |
| 645 | int32 sign = mpy ^ mpc; /* sign of result */\r | |
| 646 | \r | |
| 647 | if (mpy & LSIGN) mpy = -mpy; /* abs value */\r | |
| 648 | if (mpc & LSIGN) mpc = -mpc;\r | |
| 649 | dp_imul (mpy & LMASK, mpc & LMASK, &r); /* 32b * 32b -> 64b */\r | |
| 650 | if (sign & LSIGN) dp_neg (&r); /* negative result? */\r | |
| 651 | *rh = r.hi;\r | |
| 652 | return r.lo;\r | |
| 653 | }\r | |
| 654 | \r | |
| 655 | /* Extended divide\r | |
| 656 | \r | |
| 657 | opnd[0] = divisor (non-zero)\r | |
| 658 | opnd[1:2] = dividend\r | |
| 659 | */\r | |
| 660 | \r | |
| 661 | int32 op_ediv (int32 *opnd, int32 *rh, int32 *flg)\r | |
| 662 | {\r | |
| 663 | UDP dvd;\r | |
| 664 | uint32 i, dvr, quo;\r | |
| 665 | \r | |
| 666 | dvr = opnd[0]; /* get divisor */\r | |
| 667 | dvd.lo = opnd[1]; /* get dividend */\r | |
| 668 | dvd.hi = opnd[2];\r | |
| 669 | *flg = CC_V; /* assume error */\r | |
| 670 | *rh = 0;\r | |
| 671 | if (dvd.hi & LSIGN) dp_neg (&dvd); /* |dividend| */\r | |
| 672 | if (dvr & LSIGN) dvr = NEG (dvr); /* |divisor| */\r | |
| 673 | if (dvd.hi >= dvr) return opnd[1]; /* divide work? */\r | |
| 674 | for (i = quo = 0; i < 32; i++) { /* 32 iterations */\r | |
| 675 | quo = quo << 1; /* shift quotient */\r | |
| 676 | dp_lsh (&dvd, 1); /* shift dividend */\r | |
| 677 | if (dvd.hi >= dvr) { /* step work? */\r | |
| 678 | dvd.hi = (dvd.hi - dvr) & LMASK; /* subtract dvr */\r | |
| 679 | quo = quo + 1;\r | |
| 680 | }\r | |
| 681 | }\r | |
| 682 | if ((opnd[0] ^ opnd[2]) & LSIGN) { /* result -? */\r | |
| 683 | quo = NEG (quo); /* negate */\r | |
| 684 | if (quo && ((quo & LSIGN) == 0)) return opnd[1]; /* right sign? */\r | |
| 685 | }\r | |
| 686 | else if (quo & LSIGN) return opnd[1];\r | |
| 687 | if (opnd[2] & LSIGN) *rh = NEG (dvd.hi); /* sign of rem */\r | |
| 688 | else *rh = dvd.hi;\r | |
| 689 | *flg = 0; /* no overflow */\r | |
| 690 | return quo; /* return quo */\r | |
| 691 | }\r | |
| 692 | \r | |
| 693 | /* Compare floating */\r | |
| 694 | \r | |
| 695 | int32 op_cmpfd (int32 h1, int32 l1, int32 h2, int32 l2)\r | |
| 696 | {\r | |
| 697 | UFP a, b;\r | |
| 698 | int32 r;\r | |
| 699 | \r | |
| 700 | unpackd (h1, l1, &a);\r | |
| 701 | unpackd (h2, l2, &b);\r | |
| 702 | if (a.sign != b.sign) return (a.sign? CC_N: 0);\r | |
| 703 | r = a.exp - b.exp;\r | |
| 704 | if (r == 0) r = dp_cmp (&a.frac, &b.frac);\r | |
| 705 | if (r < 0) return (a.sign? 0: CC_N);\r | |
| 706 | if (r > 0) return (a.sign? CC_N: 0);\r | |
| 707 | return CC_Z;\r | |
| 708 | }\r | |
| 709 | \r | |
| 710 | int32 op_cmpg (int32 h1, int32 l1, int32 h2, int32 l2)\r | |
| 711 | {\r | |
| 712 | UFP a, b;\r | |
| 713 | int32 r;\r | |
| 714 | \r | |
| 715 | unpackg (h1, l1, &a);\r | |
| 716 | unpackg (h2, l2, &b);\r | |
| 717 | if (a.sign != b.sign) return (a.sign? CC_N: 0);\r | |
| 718 | r = a.exp - b.exp;\r | |
| 719 | if (r == 0) r = dp_cmp (&a.frac, &b.frac);\r | |
| 720 | if (r < 0) return (a.sign? 0: CC_N);\r | |
| 721 | if (r > 0) return (a.sign? CC_N: 0);\r | |
| 722 | return CC_Z;\r | |
| 723 | }\r | |
| 724 | \r | |
| 725 | /* Integer to floating convert */\r | |
| 726 | \r | |
| 727 | int32 op_cvtifdg (int32 val, int32 *rh, int32 opc)\r | |
| 728 | {\r | |
| 729 | UFP a;\r | |
| 730 | \r | |
| 731 | if (val == 0) { /* zero? */\r | |
| 732 | if (rh) *rh = 0; /* return true 0 */\r | |
| 733 | return 0;\r | |
| 734 | }\r | |
| 735 | if (val < 0) { /* negative? */\r | |
| 736 | a.sign = FPSIGN; /* sign = - */\r | |
| 737 | val = -val;\r | |
| 738 | }\r | |
| 739 | else a.sign = 0; /* else sign = + */\r | |
| 740 | a.exp = 32 + ((opc & 0x100)? G_BIAS: FD_BIAS); /* initial exp */\r | |
| 741 | a.frac.hi = val & LMASK; /* fraction */\r | |
| 742 | a.frac.lo = 0;\r | |
| 743 | norm (&a); /* normalize */\r | |
| 744 | if (opc & 0x100) return rpackg (&a, rh); /* pack and return */\r | |
| 745 | return rpackfd (&a, rh);\r | |
| 746 | }\r | |
| 747 | \r | |
| 748 | /* Floating to integer convert */\r | |
| 749 | \r | |
| 750 | int32 op_cvtfdgi (int32 *opnd, int32 *flg, int32 opc)\r | |
| 751 | {\r | |
| 752 | UFP a;\r | |
| 753 | int32 lnt = opc & 03;\r | |
| 754 | int32 ubexp;\r | |
| 755 | static uint32 maxv[4] = { 0x7F, 0x7FFF, 0x7FFFFFFF, 0x7FFFFFFF };\r | |
| 756 | \r | |
| 757 | *flg = 0;\r | |
| 758 | if (opc & 0x100) { /* G? */\r | |
| 759 | unpackg (opnd[0], opnd[1], &a); /* unpack */\r | |
| 760 | ubexp = a.exp - G_BIAS; /* unbiased exp */\r | |
| 761 | }\r | |
| 762 | else {\r | |
| 763 | if (opc & 0x20) unpackd (opnd[0], opnd[1], &a); /* F or D */\r | |
| 764 | else unpackf (opnd[0], &a); /* unpack */\r | |
| 765 | ubexp = a.exp - FD_BIAS; /* unbiased exp */\r | |
| 766 | }\r | |
| 767 | if ((a.exp == 0) || (ubexp < 0)) return 0; /* true zero or frac? */\r | |
| 768 | if (ubexp <= UF_V_NM) { /* exp in range? */\r | |
| 769 | dp_rsh (&a.frac, UF_V_NM - ubexp); /* leave rnd bit */\r | |
| 770 | if (lnt == 03) dp_inc (&a.frac); /* if CVTR, round */\r | |
| 771 | dp_rsh (&a.frac, 1); /* now justified */\r | |
| 772 | if ((a.frac.hi != 0) ||\r | |
| 773 | (a.frac.lo > (maxv[lnt] + (a.sign? 1: 0)))) *flg = CC_V;\r | |
| 774 | }\r | |
| 775 | else {\r | |
| 776 | *flg = CC_V; /* always ovflo */\r | |
| 777 | if (ubexp > (UF_V_NM + 32)) return 0; /* in ext range? */\r | |
| 778 | dp_lsh (&a.frac, ubexp - UF_V_NM - 1); /* no rnd bit */\r | |
| 779 | }\r | |
| 780 | return (a.sign? NEG (a.frac.lo): a.frac.lo); /* return lo frac */\r | |
| 781 | }\r | |
| 782 | \r | |
| 783 | /* Extended modularize\r | |
| 784 | \r | |
| 785 | One of three floating point instructions dropped from the architecture,\r | |
| 786 | EMOD presents two sets of complications. First, it requires an extended\r | |
| 787 | fraction multiply, with precise (and unusual) truncation conditions.\r | |
| 788 | Second, it has two write operands, a dubious distinction it shares\r | |
| 789 | with EDIV.\r | |
| 790 | */\r | |
| 791 | \r | |
| 792 | int32 op_emodf (int32 *opnd, int32 *intgr, int32 *flg)\r | |
| 793 | {\r | |
| 794 | UFP a, b;\r | |
| 795 | \r | |
| 796 | unpackf (opnd[0], &a); /* unpack operands */\r | |
| 797 | unpackf (opnd[2], &b);\r | |
| 798 | a.frac.hi = a.frac.hi | opnd[1]; /* extend src1 */\r | |
| 799 | vax_fmul (&a, &b, 0, FD_BIAS, 0, LMASK); /* multiply */\r | |
| 800 | vax_fmod (&a, FD_BIAS, intgr, flg); /* sep int & frac */\r | |
| 801 | return rpackfd (&a, NULL); /* return frac */\r | |
| 802 | }\r | |
| 803 | \r | |
| 804 | int32 op_emodd (int32 *opnd, int32 *flo, int32 *intgr, int32 *flg)\r | |
| 805 | {\r | |
| 806 | UFP a, b;\r | |
| 807 | \r | |
| 808 | unpackd (opnd[0], opnd[1], &a); /* unpack operands */\r | |
| 809 | unpackd (opnd[3], opnd[4], &b);\r | |
| 810 | a.frac.lo = a.frac.lo | opnd[2]; /* extend src1 */\r | |
| 811 | vax_fmul (&a, &b, 1, FD_BIAS, 0, 0); /* multiply */\r | |
| 812 | vax_fmod (&a, FD_BIAS, intgr, flg); /* sep int & frac */\r | |
| 813 | return rpackfd (&a, flo); /* return frac */\r | |
| 814 | }\r | |
| 815 | \r | |
| 816 | int32 op_emodg (int32 *opnd, int32 *flo, int32 *intgr, int32 *flg)\r | |
| 817 | {\r | |
| 818 | UFP a, b;\r | |
| 819 | \r | |
| 820 | unpackg (opnd[0], opnd[1], &a); /* unpack operands */\r | |
| 821 | unpackg (opnd[3], opnd[4], &b);\r | |
| 822 | a.frac.lo = a.frac.lo | (opnd[2] >> 5); /* extend src1 */\r | |
| 823 | vax_fmul (&a, &b, 1, G_BIAS, 0, 0); /* multiply */\r | |
| 824 | vax_fmod (&a, G_BIAS, intgr, flg); /* sep int & frac */\r | |
| 825 | return rpackg (&a, flo); /* return frac */\r | |
| 826 | }\r | |
| 827 | \r | |
| 828 | /* Unpacked floating point routines */\r | |
| 829 | \r | |
| 830 | /* Floating add */\r | |
| 831 | \r | |
| 832 | void vax_fadd (UFP *a, UFP *b)\r | |
| 833 | {\r | |
| 834 | int32 ediff;\r | |
| 835 | UFP t;\r | |
| 836 | \r | |
| 837 | if ((a->frac.hi == 0) && (a->frac.lo == 0)) { /* s1 = 0? */\r | |
| 838 | *a = *b;\r | |
| 839 | return;\r | |
| 840 | }\r | |
| 841 | if ((b->frac.hi == 0) && (b->frac.lo == 0)) return; /* s2 = 0? */\r | |
| 842 | if ((a->exp < b->exp) || /* |s1| < |s2|? swap */\r | |
| 843 | ((a->exp == b->exp) && (dp_cmp (&a->frac, &b->frac) < 0))) {\r | |
| 844 | t = *a;\r | |
| 845 | *a = *b;\r | |
| 846 | *b = t;\r | |
| 847 | }\r | |
| 848 | ediff = a->exp - b->exp; /* exp diff */\r | |
| 849 | if (a->sign ^ b->sign) { /* eff sub? */\r | |
| 850 | if (ediff) { /* exp diff? */\r | |
| 851 | dp_neg (&b->frac); /* negate fraction */\r | |
| 852 | dp_rsh_s (&b->frac, ediff, 1); /* signed right */\r | |
| 853 | dp_add (&a->frac, &b->frac); /* "add" frac */\r | |
| 854 | }\r | |
| 855 | else dp_sub (&a->frac, &b->frac); /* a >= b */\r | |
| 856 | norm (a); /* normalize */\r | |
| 857 | }\r | |
| 858 | else {\r | |
| 859 | if (ediff) dp_rsh (&b->frac, ediff); /* add, denormalize */\r | |
| 860 | dp_add (&a->frac, &b->frac); /* add frac */\r | |
| 861 | if (dp_cmp (&a->frac, &b->frac) < 0) { /* chk for carry */\r | |
| 862 | dp_rsh (&a->frac, 1); /* renormalize */\r | |
| 863 | a->frac.hi = a->frac.hi | UF_NM_H; /* add norm bit */\r | |
| 864 | a->exp = a->exp + 1; /* skip norm */\r | |
| 865 | }\r | |
| 866 | }\r | |
| 867 | return;\r | |
| 868 | }\r | |
| 869 | \r | |
| 870 | /* Floating multiply - 64b * 64b with cross products */\r | |
| 871 | \r | |
| 872 | void vax_fmul (UFP *a, UFP *b, t_bool qd, int32 bias, uint32 mhi, uint32 mlo)\r | |
| 873 | {\r | |
| 874 | UDP rhi, rlo, rmid1, rmid2;\r | |
| 875 | \r | |
| 876 | if ((a->exp == 0) || (b->exp == 0)) { /* zero argument? */\r | |
| 877 | a->frac.hi = a->frac.lo = 0; /* result is zero */\r | |
| 878 | a->sign = a->exp = 0;\r | |
| 879 | return;\r | |
| 880 | }\r | |
| 881 | a->sign = a->sign ^ b->sign; /* sign of result */\r | |
| 882 | a->exp = a->exp + b->exp - bias; /* add exponents */\r | |
| 883 | dp_imul (a->frac.hi, b->frac.hi, &rhi); /* high result */\r | |
| 884 | if (qd) { /* 64b needed? */\r | |
| 885 | dp_imul (a->frac.hi, b->frac.lo, &rmid1); /* cross products */\r | |
| 886 | dp_imul (a->frac.lo, b->frac.hi, &rmid2);\r | |
| 887 | dp_imul (a->frac.lo, b->frac.lo, &rlo); /* low result */\r | |
| 888 | rhi.lo = (rhi.lo + rmid1.hi) & LMASK; /* add hi cross */\r | |
| 889 | if (rhi.lo < rmid1.hi) /* to low high res */\r | |
| 890 | rhi.hi = (rhi.hi + 1) & LMASK;\r | |
| 891 | rhi.lo = (rhi.lo + rmid2.hi) & LMASK;\r | |
| 892 | if (rhi.lo < rmid2.hi)\r | |
| 893 | rhi.hi = (rhi.hi + 1) & LMASK;\r | |
| 894 | rlo.hi = (rlo.hi + rmid1.lo) & LMASK; /* add mid1 to low res */\r | |
| 895 | if (rlo.hi < rmid1.lo) dp_inc (&rhi); /* carry? incr high res */\r | |
| 896 | rlo.hi = (rlo.hi + rmid2.lo) & LMASK; /* add mid2 to low res */\r | |
| 897 | if (rlo.hi < rmid2.lo) dp_inc (&rhi); /* carry? incr high res */\r | |
| 898 | }\r | |
| 899 | a->frac.hi = rhi.hi & ~mhi; /* mask fraction */\r | |
| 900 | a->frac.lo = rhi.lo & ~mlo;\r | |
| 901 | norm (a); /* normalize */\r | |
| 902 | return;\r | |
| 903 | }\r | |
| 904 | \r | |
| 905 | /* Floating modulus - there are three cases\r | |
| 906 | \r | |
| 907 | exp <= bias - integer is 0, fraction is input,\r | |
| 908 | no overflow\r | |
| 909 | bias < exp <= bias+64 - separate integer and fraction,\r | |
| 910 | integer overflow may occur\r | |
| 911 | bias+64 < exp - result is integer, fraction is 0\r | |
| 912 | integer overflow\r | |
| 913 | */\r | |
| 914 | \r | |
| 915 | void vax_fmod (UFP *a, int32 bias, int32 *intgr, int32 *flg)\r | |
| 916 | {\r | |
| 917 | UDP ifr;\r | |
| 918 | \r | |
| 919 | if (a->exp <= bias) *intgr = *flg = 0; /* 0 or <1? int = 0 */\r | |
| 920 | else if (a->exp <= (bias + 64)) { /* in range [1,64]? */\r | |
| 921 | ifr = a->frac;\r | |
| 922 | dp_rsh (&ifr, 64 - (a->exp - bias)); /* separate integer */\r | |
| 923 | if ((a->exp > (bias + 32)) || /* test ovflo */\r | |
| 924 | ((a->exp == (bias + 32)) &&\r | |
| 925 | (ifr.lo > (a->sign? 0x80000000: 0x7FFFFFFF))))\r | |
| 926 | *flg = CC_V;\r | |
| 927 | else *flg = 0;\r | |
| 928 | *intgr = ifr.lo;\r | |
| 929 | if (a->sign) *intgr = -*intgr; /* -? comp int */\r | |
| 930 | dp_lsh (&a->frac, a->exp - bias); /* excise integer */\r | |
| 931 | a->exp = bias;\r | |
| 932 | }\r | |
| 933 | else {\r | |
| 934 | *intgr = 0; /* out of range */\r | |
| 935 | a->frac.hi = a->frac.lo = a->sign = a->exp = 0; /* result 0 */\r | |
| 936 | *flg = CC_V; /* overflow */\r | |
| 937 | }\r | |
| 938 | norm (a); /* normalize */\r | |
| 939 | return;\r | |
| 940 | }\r | |
| 941 | \r | |
| 942 | /* Floating divide\r | |
| 943 | Needs to develop at least one rounding bit. Since the first\r | |
| 944 | divide step can fail, caller should specify 2 more bits than\r | |
| 945 | the precision of the fraction.\r | |
| 946 | */\r | |
| 947 | \r | |
| 948 | void vax_fdiv (UFP *a, UFP *b, int32 prec, int32 bias)\r | |
| 949 | {\r | |
| 950 | int32 i;\r | |
| 951 | UDP quo = { 0, 0 };\r | |
| 952 | \r | |
| 953 | if (a->exp == 0) FLT_DZRO_FAULT; /* divr = 0? */\r | |
| 954 | if (b->exp == 0) return; /* divd = 0? */\r | |
| 955 | b->sign = b->sign ^ a->sign; /* result sign */\r | |
| 956 | b->exp = b->exp - a->exp + bias + 1; /* unbiased exp */\r | |
| 957 | dp_rsh (&a->frac, 1); /* allow 1 bit left */\r | |
| 958 | dp_rsh (&b->frac, 1);\r | |
| 959 | for (i = 0; i < prec; i++) { /* divide loop */\r | |
| 960 | dp_lsh (&quo, 1); /* shift quo */\r | |
| 961 | if (dp_cmp (&b->frac, &a->frac) >= 0) { /* div step ok? */\r | |
| 962 | dp_sub (&b->frac, &a->frac); /* subtract */\r | |
| 963 | quo.lo = quo.lo + 1; /* quo bit = 1 */\r | |
| 964 | }\r | |
| 965 | dp_lsh (&b->frac, 1); /* shift divd */\r | |
| 966 | }\r | |
| 967 | dp_lsh (&quo, UF_V_NM - prec + 1); /* put in position */\r | |
| 968 | b->frac = quo;\r | |
| 969 | norm (b); /* normalize */\r | |
| 970 | return;\r | |
| 971 | }\r | |
| 972 | \r | |
| 973 | /* Double precision integer routines */\r | |
| 974 | \r | |
| 975 | int32 dp_cmp (UDP *a, UDP *b)\r | |
| 976 | {\r | |
| 977 | if (a->hi < b->hi) return -1; /* compare hi */\r | |
| 978 | if (a->hi > b->hi) return +1;\r | |
| 979 | if (a->lo < b->lo) return -1; /* hi =, compare lo */\r | |
| 980 | if (a->lo > b->lo) return +1;\r | |
| 981 | return 0; /* hi, lo equal */\r | |
| 982 | }\r | |
| 983 | \r | |
| 984 | void dp_add (UDP *a, UDP *b)\r | |
| 985 | {\r | |
| 986 | a->lo = (a->lo + b->lo) & LMASK; /* add lo */\r | |
| 987 | if (a->lo < b->lo) a->hi = a->hi + 1; /* carry? */\r | |
| 988 | a->hi = (a->hi + b->hi) & LMASK; /* add hi */\r | |
| 989 | return;\r | |
| 990 | }\r | |
| 991 | \r | |
| 992 | void dp_inc (UDP *a)\r | |
| 993 | {\r | |
| 994 | a->lo = (a->lo + 1) & LMASK; /* inc lo */\r | |
| 995 | if (a->lo == 0) a->hi = (a->hi + 1) & LMASK; /* carry? inc hi */\r | |
| 996 | return;\r | |
| 997 | }\r | |
| 998 | \r | |
| 999 | void dp_sub (UDP *a, UDP *b)\r | |
| 1000 | {\r | |
| 1001 | if (a->lo < b->lo) a->hi = a->hi - 1; /* borrow? decr hi */\r | |
| 1002 | a->lo = (a->lo - b->lo) & LMASK; /* sub lo */\r | |
| 1003 | a->hi = (a->hi - b->hi) & LMASK; /* sub hi */\r | |
| 1004 | return;\r | |
| 1005 | }\r | |
| 1006 | \r | |
| 1007 | void dp_lsh (UDP *r, uint32 sc)\r | |
| 1008 | {\r | |
| 1009 | if (sc > 63) r->hi = r->lo = 0; /* > 63? result 0 */\r | |
| 1010 | else if (sc > 31) { /* [32,63]? */\r | |
| 1011 | r->hi = (r->lo << (sc - 32)) & LMASK;\r | |
| 1012 | r->lo = 0;\r | |
| 1013 | }\r | |
| 1014 | else if (sc != 0) {\r | |
| 1015 | r->hi = ((r->hi << sc) | (r->lo >> (32 - sc))) & LMASK;\r | |
| 1016 | r->lo = (r->lo << sc) & LMASK;\r | |
| 1017 | }\r | |
| 1018 | return;\r | |
| 1019 | }\r | |
| 1020 | \r | |
| 1021 | void dp_rsh (UDP *r, uint32 sc)\r | |
| 1022 | {\r | |
| 1023 | if (sc > 63) r->hi = r->lo = 0; /* > 63? result 0 */\r | |
| 1024 | else if (sc > 31) { /* [32,63]? */\r | |
| 1025 | r->lo = (r->hi >> (sc - 32)) & LMASK;\r | |
| 1026 | r->hi = 0;\r | |
| 1027 | }\r | |
| 1028 | else if (sc != 0) {\r | |
| 1029 | r->lo = ((r->lo >> sc) | (r->hi << (32 - sc))) & LMASK;\r | |
| 1030 | r->hi = (r->hi >> sc) & LMASK;\r | |
| 1031 | }\r | |
| 1032 | return;\r | |
| 1033 | }\r | |
| 1034 | \r | |
| 1035 | void dp_rsh_s (UDP *r, uint32 sc, uint32 neg)\r | |
| 1036 | {\r | |
| 1037 | dp_rsh (r, sc); /* do unsigned right */\r | |
| 1038 | if (neg && sc) { /* negative? */\r | |
| 1039 | if (sc > 63) r->hi = r->lo = LMASK; /* > 63? result -1 */\r | |
| 1040 | else {\r | |
| 1041 | UDP ones = { LMASK, LMASK };\r | |
| 1042 | dp_lsh (&ones, 64 - sc); /* shift ones */\r | |
| 1043 | r->hi = r->hi | ones.hi; /* or into result */\r | |
| 1044 | r->lo = r->lo | ones.lo;\r | |
| 1045 | }\r | |
| 1046 | }\r | |
| 1047 | return;\r | |
| 1048 | }\r | |
| 1049 | \r | |
| 1050 | void dp_imul (uint32 a, uint32 b, UDP *r)\r | |
| 1051 | {\r | |
| 1052 | uint32 ah, bh, al, bl, rhi, rlo, rmid1, rmid2;\r | |
| 1053 | \r | |
| 1054 | if ((a == 0) || (b == 0)) { /* zero argument? */\r | |
| 1055 | r->hi = r->lo = 0; /* result is zero */\r | |
| 1056 | return;\r | |
| 1057 | }\r | |
| 1058 | ah = (a >> 16) & WMASK; /* split operands */\r | |
| 1059 | bh = (b >> 16) & WMASK; /* into 16b chunks */\r | |
| 1060 | al = a & WMASK;\r | |
| 1061 | bl = b & WMASK;\r | |
| 1062 | rhi = ah * bh; /* high result */\r | |
| 1063 | rmid1 = ah * bl;\r | |
| 1064 | rmid2 = al * bh;\r | |
| 1065 | rlo = al * bl;\r | |
| 1066 | rhi = rhi + ((rmid1 >> 16) & WMASK) + ((rmid2 >> 16) & WMASK);\r | |
| 1067 | rmid1 = (rlo + (rmid1 << 16)) & LMASK; /* add mid1 to lo */\r | |
| 1068 | if (rmid1 < rlo) rhi = rhi + 1; /* carry? incr hi */\r | |
| 1069 | rmid2 = (rmid1 + (rmid2 << 16)) & LMASK; /* add mid2 to to */\r | |
| 1070 | if (rmid2 < rmid1) rhi = rhi + 1; /* carry? incr hi */\r | |
| 1071 | r->hi = rhi & LMASK; /* mask result */\r | |
| 1072 | r->lo = rmid2;\r | |
| 1073 | return;\r | |
| 1074 | }\r | |
| 1075 | \r | |
| 1076 | void dp_neg (UDP *r)\r | |
| 1077 | {\r | |
| 1078 | r->lo = NEG (r->lo);\r | |
| 1079 | r->hi = (~r->hi + (r->lo == 0)) & LMASK;\r | |
| 1080 | return;\r | |
| 1081 | }\r | |
| 1082 | \r | |
| 1083 | /* Support routines */\r | |
| 1084 | \r | |
| 1085 | void unpackf (uint32 hi, UFP *r)\r | |
| 1086 | {\r | |
| 1087 | r->sign = hi & FPSIGN; /* get sign */\r | |
| 1088 | r->exp = FD_GETEXP (hi); /* get exponent */\r | |
| 1089 | if (r->exp == 0) { /* exp = 0? */\r | |
| 1090 | if (r->sign) RSVD_OPND_FAULT; /* if -, rsvd op */\r | |
| 1091 | r->frac.hi = r->frac.lo = 0; /* else 0 */\r | |
| 1092 | return;\r | |
| 1093 | }\r | |
| 1094 | r->frac.hi = WORDSWAP ((hi & ~(FPSIGN | FD_EXP)) | FD_HB);\r | |
| 1095 | r->frac.lo = 0;\r | |
| 1096 | dp_lsh (&r->frac, FD_GUARD);\r | |
| 1097 | return;\r | |
| 1098 | }\r | |
| 1099 | \r | |
| 1100 | void unpackd (uint32 hi, uint32 lo, UFP *r)\r | |
| 1101 | {\r | |
| 1102 | r->sign = hi & FPSIGN; /* get sign */\r | |
| 1103 | r->exp = FD_GETEXP (hi); /* get exponent */\r | |
| 1104 | if (r->exp == 0) { /* exp = 0? */\r | |
| 1105 | if (r->sign) RSVD_OPND_FAULT; /* if -, rsvd op */\r | |
| 1106 | r->frac.hi = r->frac.lo = 0; /* else 0 */\r | |
| 1107 | return;\r | |
| 1108 | }\r | |
| 1109 | r->frac.hi = WORDSWAP ((hi & ~(FPSIGN | FD_EXP)) | FD_HB);\r | |
| 1110 | r->frac.lo = WORDSWAP (lo);\r | |
| 1111 | dp_lsh (&r->frac, FD_GUARD);\r | |
| 1112 | return;\r | |
| 1113 | }\r | |
| 1114 | \r | |
| 1115 | void unpackg (uint32 hi, uint32 lo, UFP *r)\r | |
| 1116 | {\r | |
| 1117 | r->sign = hi & FPSIGN; /* get sign */\r | |
| 1118 | r->exp = G_GETEXP (hi); /* get exponent */\r | |
| 1119 | if (r->exp == 0) { /* exp = 0? */\r | |
| 1120 | if (r->sign) RSVD_OPND_FAULT; /* if -, rsvd op */\r | |
| 1121 | r->frac.hi = r->frac.lo = 0; /* else 0 */\r | |
| 1122 | return;\r | |
| 1123 | }\r | |
| 1124 | r->frac.hi = WORDSWAP ((hi & ~(FPSIGN | G_EXP)) | G_HB);\r | |
| 1125 | r->frac.lo = WORDSWAP (lo);\r | |
| 1126 | dp_lsh (&r->frac, G_GUARD);\r | |
| 1127 | return;\r | |
| 1128 | }\r | |
| 1129 | \r | |
| 1130 | void norm (UFP *r)\r | |
| 1131 | {\r | |
| 1132 | int32 i;\r | |
| 1133 | static uint32 normmask[5] = {\r | |
| 1134 | 0xc0000000, 0xf0000000, 0xff000000, 0xffff0000, 0xffffffff\r | |
| 1135 | };\r | |
| 1136 | static int32 normtab[6] = { 1, 2, 4, 8, 16, 32};\r | |
| 1137 | \r | |
| 1138 | if ((r->frac.hi == 0) && (r->frac.lo == 0)) { /* if fraction = 0 */\r | |
| 1139 | r->sign = r->exp = 0; /* result is 0 */\r | |
| 1140 | return;\r | |
| 1141 | }\r | |
| 1142 | while ((r->frac.hi & UF_NM_H) == 0) { /* normalized? */\r | |
| 1143 | for (i = 0; i < 5; i++) { /* find first 1 */\r | |
| 1144 | if (r->frac.hi & normmask[i]) break;\r | |
| 1145 | }\r | |
| 1146 | dp_lsh (&r->frac, normtab[i]); /* shift frac */\r | |
| 1147 | r->exp = r->exp - normtab[i]; /* decr exp */\r | |
| 1148 | }\r | |
| 1149 | return;\r | |
| 1150 | }\r | |
| 1151 | \r | |
| 1152 | int32 rpackfd (UFP *r, int32 *rh)\r | |
| 1153 | {\r | |
| 1154 | static UDP f_round = { UF_FRND_L, UF_FRND_H };\r | |
| 1155 | static UDP d_round = { UF_DRND_L, UF_DRND_H };\r | |
| 1156 | \r | |
| 1157 | if (rh) *rh = 0; /* assume 0 */\r | |
| 1158 | if ((r->frac.hi == 0) && (r->frac.lo == 0)) return 0; /* result 0? */\r | |
| 1159 | if (rh) dp_add (&r->frac, &d_round); /* round */\r | |
| 1160 | else dp_add (&r->frac, &f_round);\r | |
| 1161 | if ((r->frac.hi & UF_NM_H) == 0) { /* carry out? */\r | |
| 1162 | dp_rsh (&r->frac, 1); /* renormalize */\r | |
| 1163 | r->exp = r->exp + 1;\r | |
| 1164 | }\r | |
| 1165 | if (r->exp > (int32) FD_M_EXP) FLT_OVFL_FAULT; /* ovflo? fault */\r | |
| 1166 | if (r->exp <= 0) { /* underflow? */\r | |
| 1167 | if (PSL & PSW_FU) FLT_UNFL_FAULT; /* fault if fu */\r | |
| 1168 | return 0; /* else 0 */\r | |
| 1169 | }\r | |
| 1170 | dp_rsh (&r->frac, FD_GUARD); /* remove guard */\r | |
| 1171 | if (rh) *rh = WORDSWAP (r->frac.lo); /* get low */\r | |
| 1172 | return r->sign | (r->exp << FD_V_EXP) |\r | |
| 1173 | (WORDSWAP (r->frac.hi) & ~(FD_HB | FPSIGN | FD_EXP));\r | |
| 1174 | }\r | |
| 1175 | \r | |
| 1176 | int32 rpackg (UFP *r, int32 *rh)\r | |
| 1177 | {\r | |
| 1178 | static UDP g_round = { UF_GRND_L, UF_GRND_H };\r | |
| 1179 | \r | |
| 1180 | *rh = 0; /* assume 0 */\r | |
| 1181 | if ((r->frac.hi == 0) && (r->frac.lo == 0)) return 0; /* result 0? */\r | |
| 1182 | dp_add (&r->frac, &g_round); /* round */\r | |
| 1183 | if ((r->frac.hi & UF_NM_H) == 0) { /* carry out? */\r | |
| 1184 | dp_rsh (&r->frac, 1); /* renormalize */\r | |
| 1185 | r->exp = r->exp + 1;\r | |
| 1186 | }\r | |
| 1187 | if (r->exp > (int32) G_M_EXP) FLT_OVFL_FAULT; /* ovflo? fault */\r | |
| 1188 | if (r->exp <= 0) { /* underflow? */\r | |
| 1189 | if (PSL & PSW_FU) FLT_UNFL_FAULT; /* fault if fu */\r | |
| 1190 | return 0; /* else 0 */\r | |
| 1191 | }\r | |
| 1192 | dp_rsh (&r->frac, G_GUARD); /* remove guard */\r | |
| 1193 | *rh = WORDSWAP (r->frac.lo); /* get low */\r | |
| 1194 | return r->sign | (r->exp << G_V_EXP) |\r | |
| 1195 | (WORDSWAP (r->frac.hi) & ~(G_HB | FPSIGN | G_EXP));\r | |
| 1196 | }\r | |
| 1197 | \r | |
| 1198 | #endif\r | |
| 1199 | \r | |
| 1200 | /* Floating point instructions */\r | |
| 1201 | \r | |
| 1202 | /* Move/test/move negated floating\r | |
| 1203 | \r | |
| 1204 | Note that only the high 32b is processed.\r | |
| 1205 | If the high 32b is not zero, it is unchanged.\r | |
| 1206 | */\r | |
| 1207 | \r | |
| 1208 | int32 op_movfd (int32 val)\r | |
| 1209 | {\r | |
| 1210 | if (val & FD_EXP) return val;\r | |
| 1211 | if (val & FPSIGN) RSVD_OPND_FAULT;\r | |
| 1212 | return 0;\r | |
| 1213 | }\r | |
| 1214 | \r | |
| 1215 | int32 op_mnegfd (int32 val)\r | |
| 1216 | {\r | |
| 1217 | if (val & FD_EXP) return (val ^ FPSIGN);\r | |
| 1218 | if (val & FPSIGN) RSVD_OPND_FAULT;\r | |
| 1219 | return 0;\r | |
| 1220 | }\r | |
| 1221 | \r | |
| 1222 | int32 op_movg (int32 val)\r | |
| 1223 | {\r | |
| 1224 | if (val & G_EXP) return val;\r | |
| 1225 | if (val & FPSIGN) RSVD_OPND_FAULT;\r | |
| 1226 | return 0;\r | |
| 1227 | }\r | |
| 1228 | \r | |
| 1229 | int32 op_mnegg (int32 val)\r | |
| 1230 | {\r | |
| 1231 | if (val & G_EXP) return (val ^ FPSIGN);\r | |
| 1232 | if (val & FPSIGN) RSVD_OPND_FAULT;\r | |
| 1233 | return 0;\r | |
| 1234 | }\r | |
| 1235 | \r | |
| 1236 | /* Floating to floating convert - F to D is essentially done with MOVFD */\r | |
| 1237 | \r | |
| 1238 | int32 op_cvtdf (int32 *opnd)\r | |
| 1239 | {\r | |
| 1240 | UFP a;\r | |
| 1241 | \r | |
| 1242 | unpackd (opnd[0], opnd[1], &a);\r | |
| 1243 | return rpackfd (&a, NULL);\r | |
| 1244 | }\r | |
| 1245 | \r | |
| 1246 | int32 op_cvtfg (int32 *opnd, int32 *rh)\r | |
| 1247 | {\r | |
| 1248 | UFP a;\r | |
| 1249 | \r | |
| 1250 | unpackf (opnd[0], &a);\r | |
| 1251 | a.exp = a.exp - FD_BIAS + G_BIAS;\r | |
| 1252 | return rpackg (&a, rh);\r | |
| 1253 | }\r | |
| 1254 | \r | |
| 1255 | int32 op_cvtgf (int32 *opnd)\r | |
| 1256 | {\r | |
| 1257 | UFP a;\r | |
| 1258 | \r | |
| 1259 | unpackg (opnd[0], opnd[1], &a);\r | |
| 1260 | a.exp = a.exp - G_BIAS + FD_BIAS;\r | |
| 1261 | return rpackfd (&a, NULL);\r | |
| 1262 | }\r | |
| 1263 | \r | |
| 1264 | /* Floating add and subtract */\r | |
| 1265 | \r | |
| 1266 | int32 op_addf (int32 *opnd, t_bool sub)\r | |
| 1267 | {\r | |
| 1268 | UFP a, b;\r | |
| 1269 | \r | |
| 1270 | unpackf (opnd[0], &a); /* F format */\r | |
| 1271 | unpackf (opnd[1], &b);\r | |
| 1272 | if (sub) a.sign = a.sign ^ FPSIGN; /* sub? -s1 */\r | |
| 1273 | vax_fadd (&a, &b); /* add fractions */\r | |
| 1274 | return rpackfd (&a, NULL);\r | |
| 1275 | }\r | |
| 1276 | \r | |
| 1277 | int32 op_addd (int32 *opnd, int32 *rh, t_bool sub)\r | |
| 1278 | {\r | |
| 1279 | UFP a, b;\r | |
| 1280 | \r | |
| 1281 | unpackd (opnd[0], opnd[1], &a);\r | |
| 1282 | unpackd (opnd[2], opnd[3], &b);\r | |
| 1283 | if (sub) a.sign = a.sign ^ FPSIGN; /* sub? -s1 */\r | |
| 1284 | vax_fadd (&a, &b); /* add fractions */\r | |
| 1285 | return rpackfd (&a, rh);\r | |
| 1286 | }\r | |
| 1287 | \r | |
| 1288 | int32 op_addg (int32 *opnd, int32 *rh, t_bool sub)\r | |
| 1289 | {\r | |
| 1290 | UFP a, b;\r | |
| 1291 | \r | |
| 1292 | unpackg (opnd[0], opnd[1], &a);\r | |
| 1293 | unpackg (opnd[2], opnd[3], &b);\r | |
| 1294 | if (sub) a.sign = a.sign ^ FPSIGN; /* sub? -s1 */\r | |
| 1295 | vax_fadd (&a, &b); /* add fractions */\r | |
| 1296 | return rpackg (&a, rh); /* round and pack */\r | |
| 1297 | }\r | |
| 1298 | \r | |
| 1299 | /* Floating multiply */\r | |
| 1300 | \r | |
| 1301 | int32 op_mulf (int32 *opnd)\r | |
| 1302 | {\r | |
| 1303 | UFP a, b;\r | |
| 1304 | \r | |
| 1305 | unpackf (opnd[0], &a); /* F format */\r | |
| 1306 | unpackf (opnd[1], &b);\r | |
| 1307 | vax_fmul (&a, &b, 0, FD_BIAS, 0, 0); /* do multiply */\r | |
| 1308 | return rpackfd (&a, NULL); /* round and pack */\r | |
| 1309 | }\r | |
| 1310 | \r | |
| 1311 | int32 op_muld (int32 *opnd, int32 *rh)\r | |
| 1312 | {\r | |
| 1313 | UFP a, b;\r | |
| 1314 | \r | |
| 1315 | unpackd (opnd[0], opnd[1], &a); /* D format */\r | |
| 1316 | unpackd (opnd[2], opnd[3], &b);\r | |
| 1317 | vax_fmul (&a, &b, 1, FD_BIAS, 0, 0); /* do multiply */\r | |
| 1318 | return rpackfd (&a, rh); /* round and pack */\r | |
| 1319 | }\r | |
| 1320 | \r | |
| 1321 | int32 op_mulg (int32 *opnd, int32 *rh)\r | |
| 1322 | {\r | |
| 1323 | UFP a, b;\r | |
| 1324 | \r | |
| 1325 | unpackg (opnd[0], opnd[1], &a); /* G format */\r | |
| 1326 | unpackg (opnd[2], opnd[3], &b);\r | |
| 1327 | vax_fmul (&a, &b, 1, G_BIAS, 0, 0); /* do multiply */\r | |
| 1328 | return rpackg (&a, rh); /* round and pack */\r | |
| 1329 | }\r | |
| 1330 | \r | |
| 1331 | /* Floating divide */\r | |
| 1332 | \r | |
| 1333 | int32 op_divf (int32 *opnd)\r | |
| 1334 | {\r | |
| 1335 | UFP a, b;\r | |
| 1336 | \r | |
| 1337 | unpackf (opnd[0], &a); /* F format */\r | |
| 1338 | unpackf (opnd[1], &b);\r | |
| 1339 | vax_fdiv (&a, &b, 26, FD_BIAS); /* do divide */\r | |
| 1340 | return rpackfd (&b, NULL); /* round and pack */\r | |
| 1341 | }\r | |
| 1342 | \r | |
| 1343 | int32 op_divd (int32 *opnd, int32 *rh)\r | |
| 1344 | {\r | |
| 1345 | UFP a, b;\r | |
| 1346 | \r | |
| 1347 | unpackd (opnd[0], opnd[1], &a); /* D format */\r | |
| 1348 | unpackd (opnd[2], opnd[3], &b);\r | |
| 1349 | vax_fdiv (&a, &b, 58, FD_BIAS); /* do divide */\r | |
| 1350 | return rpackfd (&b, rh); /* round and pack */\r | |
| 1351 | }\r | |
| 1352 | \r | |
| 1353 | int32 op_divg (int32 *opnd, int32 *rh)\r | |
| 1354 | {\r | |
| 1355 | UFP a, b;\r | |
| 1356 | \r | |
| 1357 | unpackg (opnd[0], opnd[1], &a); /* G format */\r | |
| 1358 | unpackg (opnd[2], opnd[3], &b);\r | |
| 1359 | vax_fdiv (&a, &b, 55, G_BIAS); /* do divide */\r | |
| 1360 | return rpackg (&b, rh); /* round and pack */\r | |
| 1361 | }\r | |
| 1362 | \r | |
| 1363 | /* Polynomial evaluation\r | |
| 1364 | The most mis-implemented instruction in the VAX (probably here too).\r | |
| 1365 | POLY requires a precise combination of masking versus normalizing\r | |
| 1366 | to achieve the desired answer. In particular, the multiply step\r | |
| 1367 | is masked prior to normalization. In addition, negative small\r | |
| 1368 | fractions must not be treated as 0 during denorm.\r | |
| 1369 | */\r | |
| 1370 | \r | |
| 1371 | void op_polyf (int32 *opnd, int32 acc)\r | |
| 1372 | {\r | |
| 1373 | UFP r, a, c;\r | |
| 1374 | int32 deg = opnd[1];\r | |
| 1375 | int32 ptr = opnd[2];\r | |
| 1376 | int32 i, wd, res;\r | |
| 1377 | \r | |
| 1378 | if (deg > 31) RSVD_OPND_FAULT; /* degree > 31? fault */\r | |
| 1379 | unpackf (opnd[0], &a); /* unpack arg */\r | |
| 1380 | wd = Read (ptr, L_LONG, RD); /* get C0 */\r | |
| 1381 | ptr = ptr + 4;\r | |
| 1382 | unpackf (wd, &r); /* unpack C0 */\r | |
| 1383 | res = rpackfd (&r, NULL); /* first result */\r | |
| 1384 | for (i = 0; i < deg; i++) { /* loop */\r | |
| 1385 | unpackf (res, &r); /* unpack result */\r | |
| 1386 | vax_fmul (&r, &a, 0, FD_BIAS, 1, LMASK); /* r = r * arg, mask */\r | |
| 1387 | wd = Read (ptr, L_LONG, RD); /* get Cnext */\r | |
| 1388 | ptr = ptr + 4;\r | |
| 1389 | unpackf (wd, &c); /* unpack Cnext */\r | |
| 1390 | vax_fadd (&r, &c); /* r = r + Cnext */\r | |
| 1391 | res = rpackfd (&r, NULL); /* round and pack */\r | |
| 1392 | }\r | |
| 1393 | R[0] = res;\r | |
| 1394 | R[1] = R[2] = 0;\r | |
| 1395 | R[3] = ptr;\r | |
| 1396 | return;\r | |
| 1397 | }\r | |
| 1398 | \r | |
| 1399 | void op_polyd (int32 *opnd, int32 acc)\r | |
| 1400 | {\r | |
| 1401 | UFP r, a, c;\r | |
| 1402 | int32 deg = opnd[2];\r | |
| 1403 | int32 ptr = opnd[3];\r | |
| 1404 | int32 i, wd, wd1, res, resh;\r | |
| 1405 | \r | |
| 1406 | if (deg > 31) RSVD_OPND_FAULT; /* degree > 31? fault */\r | |
| 1407 | unpackd (opnd[0], opnd[1], &a); /* unpack arg */\r | |
| 1408 | wd = Read (ptr, L_LONG, RD); /* get C0 */\r | |
| 1409 | wd1 = Read (ptr + 4, L_LONG, RD);\r | |
| 1410 | ptr = ptr + 8;\r | |
| 1411 | unpackd (wd, wd1, &r); /* unpack C0 */\r | |
| 1412 | res = rpackfd (&r, &resh); /* first result */\r | |
| 1413 | for (i = 0; i < deg; i++) { /* loop */\r | |
| 1414 | unpackd (res, resh, &r); /* unpack result */\r | |
| 1415 | vax_fmul (&r, &a, 1, FD_BIAS, 0, 1); /* r = r * arg, mask */\r | |
| 1416 | wd = Read (ptr, L_LONG, RD); /* get Cnext */\r | |
| 1417 | wd1 = Read (ptr + 4, L_LONG, RD);\r | |
| 1418 | ptr = ptr + 8;\r | |
| 1419 | unpackd (wd, wd1, &c); /* unpack Cnext */\r | |
| 1420 | vax_fadd (&r, &c); /* r = r + Cnext */\r | |
| 1421 | res = rpackfd (&r, &resh); /* round and pack */\r | |
| 1422 | }\r | |
| 1423 | R[0] = res;\r | |
| 1424 | R[1] = resh;\r | |
| 1425 | R[2] = 0;\r | |
| 1426 | R[3] = ptr;\r | |
| 1427 | R[4] = 0;\r | |
| 1428 | R[5] = 0;\r | |
| 1429 | return;\r | |
| 1430 | }\r | |
| 1431 | \r | |
| 1432 | void op_polyg (int32 *opnd, int32 acc)\r | |
| 1433 | {\r | |
| 1434 | UFP r, a, c;\r | |
| 1435 | int32 deg = opnd[2];\r | |
| 1436 | int32 ptr = opnd[3];\r | |
| 1437 | int32 i, wd, wd1, res, resh;\r | |
| 1438 | \r | |
| 1439 | if (deg > 31) RSVD_OPND_FAULT; /* degree > 31? fault */\r | |
| 1440 | unpackg (opnd[0], opnd[1], &a); /* unpack arg */\r | |
| 1441 | wd = Read (ptr, L_LONG, RD); /* get C0 */\r | |
| 1442 | wd1 = Read (ptr + 4, L_LONG, RD);\r | |
| 1443 | ptr = ptr + 8;\r | |
| 1444 | unpackg (wd, wd1, &r); /* unpack C0 */\r | |
| 1445 | res = rpackg (&r, &resh); /* first result */\r | |
| 1446 | for (i = 0; i < deg; i++) { /* loop */\r | |
| 1447 | unpackg (res, resh, &r); /* unpack result */\r | |
| 1448 | vax_fmul (&r, &a, 1, G_BIAS, 0, 1); /* r = r * arg */\r | |
| 1449 | wd = Read (ptr, L_LONG, RD); /* get Cnext */\r | |
| 1450 | wd1 = Read (ptr + 4, L_LONG, RD);\r | |
| 1451 | ptr = ptr + 8;\r | |
| 1452 | unpackg (wd, wd1, &c); /* unpack Cnext */\r | |
| 1453 | vax_fadd (&r, &c); /* r = r + Cnext */\r | |
| 1454 | res = rpackg (&r, &resh); /* round and pack */\r | |
| 1455 | }\r | |
| 1456 | R[0] = res;\r | |
| 1457 | R[1] = resh;\r | |
| 1458 | R[2] = 0;\r | |
| 1459 | R[3] = ptr;\r | |
| 1460 | R[4] = 0;\r | |
| 1461 | R[5] = 0;\r | |
| 1462 | return;\r | |
| 1463 | }\r |