AltairZ80/insns.h

   1 /* insns.h   header file for insns.c
   2  * $Id: insns.h,v 1.1 2004/02/11 19:01:38 perrin Exp $
   3  *
   4  * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
   5  * Julian Hall. All rights reserved. The software is
   6  * redistributable under the licence given in the file "Licence"
   7  * distributed in the NASM archive.
   8  */
   9
  10 #ifndef NASM_INSNS_H
  11 #define NASM_INSNS_H
  12
  13 /* This file is auto-generated from insns.dat by insns.pl - don't edit it */
  14
  15 /* This file in included by nasm.h */
  16
  17 /* Instruction names */
  18 enum {
  19     I_AAA,
  20     I_AAD,
  21     I_AAM,
  22     I_AAS,
  23     I_ADC,
  24     I_ADD,
  25     I_ADDPD,
  26     I_ADDPS,
  27     I_ADDSD,
  28     I_ADDSS,
  29     I_ADDSUBPD,
  30     I_ADDSUBPS,
  31     I_AND,
  32     I_ANDNPD,
  33     I_ANDNPS,
  34     I_ANDPD,
  35     I_ANDPS,
  36     I_ARPL,
  37     I_BOUND,
  38     I_BSF,
  39     I_BSR,
  40     I_BSWAP,
  41     I_BT,
  42     I_BTC,
  43     I_BTR,
  44     I_BTS,
  45     I_CALL,
  46     I_CBW,
  47     I_CDQ,
  48     I_CLC,
  49     I_CLD,
  50     I_CLFLUSH,
  51     I_CLI,
  52     I_CLTS,
  53     I_CMC,
  54     I_CMP,
  55     I_CMPEQPD,
  56     I_CMPEQPS,
  57     I_CMPEQSD,
  58     I_CMPEQSS,
  59     I_CMPLEPD,
  60     I_CMPLEPS,
  61     I_CMPLESD,
  62     I_CMPLESS,
  63     I_CMPLTPD,
  64     I_CMPLTPS,
  65     I_CMPLTSD,
  66     I_CMPLTSS,
  67     I_CMPNEQPD,
  68     I_CMPNEQPS,
  69     I_CMPNEQSD,
  70     I_CMPNEQSS,
  71     I_CMPNLEPD,
  72     I_CMPNLEPS,
  73     I_CMPNLESD,
  74     I_CMPNLESS,
  75     I_CMPNLTPD,
  76     I_CMPNLTPS,
  77     I_CMPNLTSD,
  78     I_CMPNLTSS,
  79     I_CMPORDPD,
  80     I_CMPORDPS,
  81     I_CMPORDSD,
  82     I_CMPORDSS,
  83     I_CMPPD,
  84     I_CMPPS,
  85     I_CMPSB,
  86     I_CMPSD,
  87     I_CMPSS,
  88     I_CMPSW,
  89     I_CMPUNORDPD,
  90     I_CMPUNORDPS,
  91     I_CMPUNORDSD,
  92     I_CMPUNORDSS,
  93     I_CMPXCHG,
  94     I_CMPXCHG486,
  95     I_CMPXCHG8B,
  96     I_COMISD,
  97     I_COMISS,
  98     I_CPUID,
  99     I_CVTDQ2PD,
 100     I_CVTDQ2PS,
 101     I_CVTPD2DQ,
 102     I_CVTPD2PI,
 103     I_CVTPD2PS,
 104     I_CVTPI2PD,
 105     I_CVTPI2PS,
 106     I_CVTPS2DQ,
 107     I_CVTPS2PD,
 108     I_CVTPS2PI,
 109     I_CVTSD2SI,
 110     I_CVTSD2SS,
 111     I_CVTSI2SD,
 112     I_CVTSI2SS,
 113     I_CVTSS2SD,
 114     I_CVTSS2SI,
 115     I_CVTTPD2DQ,
 116     I_CVTTPD2PI,
 117     I_CVTTPS2DQ,
 118     I_CVTTPS2PI,
 119     I_CVTTSD2SI,
 120     I_CVTTSS2SI,
 121     I_CWD,
 122     I_CWDE,
 123     I_DAA,
 124     I_DAS,
 125     I_DB,
 126     I_DD,
 127     I_DEC,
 128     I_DIV,
 129     I_DIVPD,
 130     I_DIVPS,
 131     I_DIVSD,
 132     I_DIVSS,
 133     I_DQ,
 134     I_DT,
 135     I_DW,
 136     I_EMMS,
 137     I_ENTER,
 138     I_EQU,
 139     I_F2XM1,
 140     I_FABS,
 141     I_FADD,
 142     I_FADDP,
 143     I_FBLD,
 144     I_FBSTP,
 145     I_FCHS,
 146     I_FCLEX,
 147     I_FCMOVB,
 148     I_FCMOVBE,
 149     I_FCMOVE,
 150     I_FCMOVNB,
 151     I_FCMOVNBE,
 152     I_FCMOVNE,
 153     I_FCMOVNU,
 154     I_FCMOVU,
 155     I_FCOM,
 156     I_FCOMI,
 157     I_FCOMIP,
 158     I_FCOMP,
 159     I_FCOMPP,
 160     I_FCOS,
 161     I_FDECSTP,
 162     I_FDISI,
 163     I_FDIV,
 164     I_FDIVP,
 165     I_FDIVR,
 166     I_FDIVRP,
 167     I_FEMMS,
 168     I_FENI,
 169     I_FFREE,
 170     I_FFREEP,
 171     I_FIADD,
 172     I_FICOM,
 173     I_FICOMP,
 174     I_FIDIV,
 175     I_FIDIVR,
 176     I_FILD,
 177     I_FIMUL,
 178     I_FINCSTP,
 179     I_FINIT,
 180     I_FIST,
 181     I_FISTP,
 182     I_FISTTP,
 183     I_FISUB,
 184     I_FISUBR,
 185     I_FLD,
 186     I_FLD1,
 187     I_FLDCW,
 188     I_FLDENV,
 189     I_FLDL2E,
 190     I_FLDL2T,
 191     I_FLDLG2,
 192     I_FLDLN2,
 193     I_FLDPI,
 194     I_FLDZ,
 195     I_FMUL,
 196     I_FMULP,
 197     I_FNCLEX,
 198     I_FNDISI,
 199     I_FNENI,
 200     I_FNINIT,
 201     I_FNOP,
 202     I_FNSAVE,
 203     I_FNSTCW,
 204     I_FNSTENV,
 205     I_FNSTSW,
 206     I_FPATAN,
 207     I_FPREM,
 208     I_FPREM1,
 209     I_FPTAN,
 210     I_FRNDINT,
 211     I_FRSTOR,
 212     I_FSAVE,
 213     I_FSCALE,
 214     I_FSETPM,
 215     I_FSIN,
 216     I_FSINCOS,
 217     I_FSQRT,
 218     I_FST,
 219     I_FSTCW,
 220     I_FSTENV,
 221     I_FSTP,
 222     I_FSTSW,
 223     I_FSUB,
 224     I_FSUBP,
 225     I_FSUBR,
 226     I_FSUBRP,
 227     I_FTST,
 228     I_FUCOM,
 229     I_FUCOMI,
 230     I_FUCOMIP,
 231     I_FUCOMP,
 232     I_FUCOMPP,
 233     I_FWAIT,
 234     I_FXAM,
 235     I_FXCH,
 236     I_FXRSTOR,
 237     I_FXSAVE,
 238     I_FXTRACT,
 239     I_FYL2X,
 240     I_FYL2XP1,
 241     I_HADDPD,
 242     I_HADDPS,
 243     I_HLT,
 244     I_HSUBPD,
 245     I_HSUBPS,
 246     I_IBTS,
 247     I_ICEBP,
 248     I_IDIV,
 249     I_IMUL,
 250     I_IN,
 251     I_INC,
 252     I_INCBIN,
 253     I_INSB,
 254     I_INSD,
 255     I_INSW,
 256     I_INT,
 257     I_INT01,
 258     I_INT03,
 259     I_INT1,
 260     I_INT3,
 261     I_INTO,
 262     I_INVD,
 263     I_INVLPG,
 264     I_IRET,
 265     I_IRETD,
 266     I_IRETW,
 267     I_JCXZ,
 268     I_JECXZ,
 269     I_JMP,
 270     I_JMPE,
 271     I_LAHF,
 272     I_LAR,
 273     I_LDDQU,
 274     I_LDMXCSR,
 275     I_LDS,
 276     I_LEA,
 277     I_LEAVE,
 278     I_LES,
 279     I_LFENCE,
 280     I_LFS,
 281     I_LGDT,
 282     I_LGS,
 283     I_LIDT,
 284     I_LLDT,
 285     I_LMSW,
 286     I_LOADALL,
 287     I_LOADALL286,
 288     I_LODSB,
 289     I_LODSD,
 290     I_LODSW,
 291     I_LOOP,
 292     I_LOOPE,
 293     I_LOOPNE,
 294     I_LOOPNZ,
 295     I_LOOPZ,
 296     I_LSL,
 297     I_LSS,
 298     I_LTR,
 299     I_MASKMOVDQU,
 300     I_MASKMOVQ,
 301     I_MAXPD,
 302     I_MAXPS,
 303     I_MAXSD,
 304     I_MAXSS,
 305     I_MFENCE,
 306     I_MINPD,
 307     I_MINPS,
 308     I_MINSD,
 309     I_MINSS,
 310     I_MONITOR,
 311     I_MOV,
 312     I_MOVAPD,
 313     I_MOVAPS,
 314     I_MOVD,
 315     I_MOVDDUP,
 316     I_MOVDQ2Q,
 317     I_MOVDQA,
 318     I_MOVDQU,
 319     I_MOVHLPS,
 320     I_MOVHPD,
 321     I_MOVHPS,
 322     I_MOVLHPS,
 323     I_MOVLPD,
 324     I_MOVLPS,
 325     I_MOVMSKPD,
 326     I_MOVMSKPS,
 327     I_MOVNTDQ,
 328     I_MOVNTI,
 329     I_MOVNTPD,
 330     I_MOVNTPS,
 331     I_MOVNTQ,
 332     I_MOVQ,
 333     I_MOVQ2DQ,
 334     I_MOVSB,
 335     I_MOVSD,
 336     I_MOVSHDUP,
 337     I_MOVSLDUP,
 338     I_MOVSS,
 339     I_MOVSW,
 340     I_MOVSX,
 341     I_MOVUPD,
 342     I_MOVUPS,
 343     I_MOVZX,
 344     I_MUL,
 345     I_MULPD,
 346     I_MULPS,
 347     I_MULSD,
 348     I_MULSS,
 349     I_MWAIT,
 350     I_NEG,
 351     I_NOP,
 352     I_NOT,
 353     I_OR,
 354     I_ORPD,
 355     I_ORPS,
 356     I_OUT,
 357     I_OUTSB,
 358     I_OUTSD,
 359     I_OUTSW,
 360     I_PACKSSDW,
 361     I_PACKSSWB,
 362     I_PACKUSWB,
 363     I_PADDB,
 364     I_PADDD,
 365     I_PADDQ,
 366     I_PADDSB,
 367     I_PADDSIW,
 368     I_PADDSW,
 369     I_PADDUSB,
 370     I_PADDUSW,
 371     I_PADDW,
 372     I_PAND,
 373     I_PANDN,
 374     I_PAUSE,
 375     I_PAVEB,
 376     I_PAVGB,
 377     I_PAVGUSB,
 378     I_PAVGW,
 379     I_PCMPEQB,
 380     I_PCMPEQD,
 381     I_PCMPEQW,
 382     I_PCMPGTB,
 383     I_PCMPGTD,
 384     I_PCMPGTW,
 385     I_PDISTIB,
 386     I_PEXTRW,
 387     I_PF2ID,
 388     I_PF2IW,
 389     I_PFACC,
 390     I_PFADD,
 391     I_PFCMPEQ,
 392     I_PFCMPGE,
 393     I_PFCMPGT,
 394     I_PFMAX,
 395     I_PFMIN,
 396     I_PFMUL,
 397     I_PFNACC,
 398     I_PFPNACC,
 399     I_PFRCP,
 400     I_PFRCPIT1,
 401     I_PFRCPIT2,
 402     I_PFRSQIT1,
 403     I_PFRSQRT,
 404     I_PFSUB,
 405     I_PFSUBR,
 406     I_PI2FD,
 407     I_PI2FW,
 408     I_PINSRW,
 409     I_PMACHRIW,
 410     I_PMADDWD,
 411     I_PMAGW,
 412     I_PMAXSW,
 413     I_PMAXUB,
 414     I_PMINSW,
 415     I_PMINUB,
 416     I_PMOVMSKB,
 417     I_PMULHRIW,
 418     I_PMULHRWA,
 419     I_PMULHRWC,
 420     I_PMULHUW,
 421     I_PMULHW,
 422     I_PMULLW,
 423     I_PMULUDQ,
 424     I_PMVGEZB,
 425     I_PMVLZB,
 426     I_PMVNZB,
 427     I_PMVZB,
 428     I_POP,
 429     I_POPA,
 430     I_POPAD,
 431     I_POPAW,
 432     I_POPF,
 433     I_POPFD,
 434     I_POPFW,
 435     I_POR,
 436     I_PREFETCH,
 437     I_PREFETCHNTA,
 438     I_PREFETCHT0,
 439     I_PREFETCHT1,
 440     I_PREFETCHT2,
 441     I_PREFETCHW,
 442     I_PSADBW,
 443     I_PSHUFD,
 444     I_PSHUFHW,
 445     I_PSHUFLW,
 446     I_PSHUFW,
 447     I_PSLLD,
 448     I_PSLLDQ,
 449     I_PSLLQ,
 450     I_PSLLW,
 451     I_PSRAD,
 452     I_PSRAW,
 453     I_PSRLD,
 454     I_PSRLDQ,
 455     I_PSRLQ,
 456     I_PSRLW,
 457     I_PSUBB,
 458     I_PSUBD,
 459     I_PSUBQ,
 460     I_PSUBSB,
 461     I_PSUBSIW,
 462     I_PSUBSW,
 463     I_PSUBUSB,
 464     I_PSUBUSW,
 465     I_PSUBW,
 466     I_PSWAPD,
 467     I_PUNPCKHBW,
 468     I_PUNPCKHDQ,
 469     I_PUNPCKHQDQ,
 470     I_PUNPCKHWD,
 471     I_PUNPCKLBW,
 472     I_PUNPCKLDQ,
 473     I_PUNPCKLQDQ,
 474     I_PUNPCKLWD,
 475     I_PUSH,
 476     I_PUSHA,
 477     I_PUSHAD,
 478     I_PUSHAW,
 479     I_PUSHF,
 480     I_PUSHFD,
 481     I_PUSHFW,
 482     I_PXOR,
 483     I_RCL,
 484     I_RCPPS,
 485     I_RCPSS,
 486     I_RCR,
 487     I_RDMSR,
 488     I_RDPMC,
 489     I_RDSHR,
 490     I_RDTSC,
 491     I_RESB,
 492     I_RESD,
 493     I_RESQ,
 494     I_REST,
 495     I_RESW,
 496     I_RET,
 497     I_RETF,
 498     I_RETN,
 499     I_ROL,
 500     I_ROR,
 501     I_RSDC,
 502     I_RSLDT,
 503     I_RSM,
 504     I_RSQRTPS,
 505     I_RSQRTSS,
 506     I_RSTS,
 507     I_SAHF,
 508     I_SAL,
 509     I_SALC,
 510     I_SAR,
 511     I_SBB,
 512     I_SCASB,
 513     I_SCASD,
 514     I_SCASW,
 515     I_SFENCE,
 516     I_SGDT,
 517     I_SHL,
 518     I_SHLD,
 519     I_SHR,
 520     I_SHRD,
 521     I_SHUFPD,
 522     I_SHUFPS,
 523     I_SIDT,
 524     I_SLDT,
 525     I_SMI,
 526     I_SMINT,
 527     I_SMINTOLD,
 528     I_SMSW,
 529     I_SQRTPD,
 530     I_SQRTPS,
 531     I_SQRTSD,
 532     I_SQRTSS,
 533     I_STC,
 534     I_STD,
 535     I_STI,
 536     I_STMXCSR,
 537     I_STOSB,
 538     I_STOSD,
 539     I_STOSW,
 540     I_STR,
 541     I_SUB,
 542     I_SUBPD,
 543     I_SUBPS,
 544     I_SUBSD,
 545     I_SUBSS,
 546     I_SVDC,
 547     I_SVLDT,
 548     I_SVTS,
 549     I_SYSCALL,
 550     I_SYSENTER,
 551     I_SYSEXIT,
 552     I_SYSRET,
 553     I_TEST,
 554     I_UCOMISD,
 555     I_UCOMISS,
 556     I_UD0,
 557     I_UD1,
 558     I_UD2,
 559     I_UMOV,
 560     I_UNPCKHPD,
 561     I_UNPCKHPS,
 562     I_UNPCKLPD,
 563     I_UNPCKLPS,
 564     I_VERR,
 565     I_VERW,
 566     I_WAIT,
 567     I_WBINVD,
 568     I_WRMSR,
 569     I_WRSHR,
 570     I_XADD,
 571     I_XBTS,
 572     I_XCHG,
 573     I_XLAT,
 574     I_XLATB,
 575     I_XOR,
 576     I_XORPD,
 577     I_XORPS,
 578     I_XSTORE,
 579     I_CMOVcc,
 580     I_Jcc,
 581     I_SETcc
 582 };
 583
 584 #define MAX_INSLEN 11
 585
 586 /* max length of any instruction, register name etc. */
 587 #if MAX_INSLEN > 9      /* MAX_INSLEN defined in insnsi.h */
 588 #define MAX_KEYWORD MAX_INSLEN
 589 #else
 590 #define MAX_KEYWORD 9
 591 #endif
 592
 593 struct itemplate {
 594     int opcode;                /* the token, passed from "parser.c" */
 595     int operands;              /* number of operands */
 596     long opd[3];               /* bit flags for operand types */
 597     const char *code;          /* the code it assembles to */
 598     unsigned long flags;           /* some flags */
 599 };
 600
 601 /*
 602  * this define is used to signify the end of an itemplate
 603  */
 604 #define ITEMPLATE_END {-1,-1,{-1,-1,-1},NULL,0}
 605
 606 /*
 607  * Instruction template flags. These specify which processor
 608  * targets the instruction is eligible for, whether it is
 609  * privileged or undocumented, and also specify extra error
 610  * checking on the matching of the instruction.
 611  *
 612  * IF_SM stands for Size Match: any operand whose size is not
 613  * explicitly specified by the template is `really' intended to be
 614  * the same size as the first size-specified operand.
 615  * Non-specification is tolerated in the input instruction, but
 616  * _wrong_ specification is not.
 617  *
 618  * IF_SM2 invokes Size Match on only the first _two_ operands, for
 619  * three-operand instructions such as SHLD: it implies that the
 620  * first two operands must match in size, but that the third is
 621  * required to be _unspecified_.
 622  *
 623  * IF_SB invokes Size Byte: operands with unspecified size in the
 624  * template are really bytes, and so no non-byte specification in
 625  * the input instruction will be tolerated. IF_SW similarly invokes
 626  * Size Word, and IF_SD invokes Size Doubleword.
 627  *
 628  * (The default state if neither IF_SM nor IF_SM2 is specified is
 629  * that any operand with unspecified size in the template is
 630  * required to have unspecified size in the instruction too...)
 631  */
 632
 633 #define IF_SM     0x00000001UL         /* size match */
 634 #define IF_SM2    0x00000002UL         /* size match first two operands */
 635 #define IF_SB     0x00000004UL         /* unsized operands can't be non-byte */
 636 #define IF_SW     0x00000008UL         /* unsized operands can't be non-word */
 637 #define IF_SD     0x00000010UL         /* unsized operands can't be nondword */
 638 #define IF_AR0    0x00000020UL         /* SB, SW, SD applies to argument 0 */
 639 #define IF_AR1    0x00000040UL         /* SB, SW, SD applies to argument 1 */
 640 #define IF_AR2    0x00000060UL         /* SB, SW, SD applies to argument 2 */
 641 #define IF_ARMASK 0x00000060UL         /* mask for unsized argument spec */
 642 #define IF_PRIV   0x00000100UL         /* it's a privileged instruction */
 643 #define IF_SMM    0x00000200UL         /* it's only valid in SMM */
 644 #define IF_PROT   0x00000400UL         /* it's protected mode only */
 645 #define IF_UNDOC  0x00001000UL         /* it's an undocumented instruction */
 646 #define IF_FPU    0x00002000UL         /* it's an FPU instruction */
 647 #define IF_MMX    0x00004000UL         /* it's an MMX instruction */
 648 #define IF_3DNOW  0x00008000UL         /* it's a 3DNow! instruction */
 649 #define IF_SSE    0x00010000UL         /* it's a SSE (KNI, MMX2) instruction */
 650 #define IF_SSE2   0x00020000UL         /* it's a SSE2 instruction */
 651 #define IF_SSE3   0x00040000UL         /* it's a SSE3 (PNI) instruction */
 652 #define IF_PMASK  0xFF000000UL         /* the mask for processor types */
 653 #define IF_PLEVEL 0x0F000000UL         /* the mask for processor instr. level */
 654                     /* also the highest possible processor */
 655 #define IF_PFMASK 0xF001FF00UL         /* the mask for disassembly "prefer" */
 656 #define IF_8086   0x00000000UL         /* 8086 instruction */
 657 #define IF_186    0x01000000UL         /* 186+ instruction */
 658 #define IF_286    0x02000000UL         /* 286+ instruction */
 659 #define IF_386    0x03000000UL         /* 386+ instruction */
 660 #define IF_486    0x04000000UL         /* 486+ instruction */
 661 #define IF_PENT   0x05000000UL         /* Pentium instruction */
 662 #define IF_P6     0x06000000UL         /* P6 instruction */
 663 #define IF_KATMAI 0x07000000UL         /* Katmai instructions */
 664 #define IF_WILLAMETTE 0x08000000UL         /* Willamette instructions */
 665 #define IF_PRESCOTT   0x09000000UL     /* Prescott instructions */
 666 #define IF_IA64   0x0F000000UL         /* IA64 instructions */
 667 #define IF_CYRIX  0x10000000UL         /* Cyrix-specific instruction */
 668 #define IF_AMD    0x20000000UL         /* AMD-specific instruction */
 669
 670 #endif