AltairZ80/s100_ss1.c

   1 /*************************************************************************
   2  *                                                                       *
   3  * $Id: s100_ss1.c 1773 2008-01-11 05:46:19Z hharte $                    *
   4  *                                                                       *
   5  * Copyright (c) 2007-2008 Howard M. Harte.                              *
   6  * http://www.hartetec.com                                               *
   7  *                                                                       *
   8  * Permission is hereby granted, free of charge, to any person obtaining *
   9  * a copy of this software and associated documentation files (the       *
  10  * "Software"), to deal in the Software without restriction, including   *
  11  * without limitation the rights to use, copy, modify, merge, publish,   *
  12  * distribute, sublicense, and/or sell copies of the Software, and to    *
  13  * permit persons to whom the Software is furnished to do so, subject to *
  14  * the following conditions:                                             *
  15  *                                                                       *
  16  * The above copyright notice and this permission notice shall be        *
  17  * included in all copies or substantial portions of the Software.       *
  18  *                                                                       *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,       *
  20  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF    *
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND                 *
  22  * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY  *
  23  * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,  *
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE     *
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                *
  26  *                                                                       *
  27  * Except as contained in this notice, the name of Howard M. Harte shall *
  28  * not be used in advertising or otherwise to promote the sale, use or   *
  29  * other dealings in this Software without prior written authorization   *
  30  * Howard M. Harte.                                                      *
  31  *                                                                       *
  32  * SIMH Interface based on altairz80_hdsk.c, by Peter Schorn.            *
  33  *                                                                       *
  34  * Module Description:                                                   *
  35  *     CompuPro System Support 1 module for SIMH.                        *
  36  * Note this does not include the Boot ROM on the System Support 1 Card  *
  37  *                                                                       *
  38  * Environment:                                                          *
  39  *     User mode only                                                    *
  40  *                                                                       *
  41  *************************************************************************/
  42
  43 /*#define DBG_MSG */
  44
  45 #include "altairz80_defs.h"
  46
  47 #if defined (_WIN32)
  48 #include <windows.h>
  49 #endif
  50
  51 #ifdef DBG_MSG
  52 #define DBG_PRINT(args) printf args
  53 #else
  54 #define DBG_PRINT(args)
  55 #endif
  56
  57 #define TRACE_MSG   0x01
  58 #define DMA_MSG     0x02
  59
  60 #define SS1_MAX_DRIVES    1
  61
  62 #define UNIT_V_SS1_VERBOSE     (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages   */
  63 #define UNIT_SS1_VERBOSE       (1 << UNIT_V_SS1_VERBOSE)
  64
  65 typedef struct {
  66     PNP_INFO    pnp;    /* Plug and Play */
  67 } SS1_INFO;
  68
  69 static SS1_INFO ss1_info_data = { { 0x0, 0, 0x50, 12 } };
  70 /* static SS1_INFO *ss1_info = &ss1_info_data;*/
  71
  72 extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);
  73 extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);
  74 extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
  75         int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
  76 extern uint32 PCX;
  77 extern REG *sim_PC;
  78
  79 /* These are needed for DMA.  PIO Mode has not been implemented yet. */
  80 extern void PutBYTEWrapper(const uint32 Addr, const uint32 Value);
  81 extern uint8 GetBYTEWrapper(const uint32 Addr);
  82
  83 static t_stat ss1_reset(DEVICE *ss1_dev);
  84 static uint8 SS1_Read(const uint32 Addr);
  85 static uint8 SS1_Write(const uint32 Addr, uint8 cData);
  86
  87
  88 static int32 ss1dev(const int32 port, const int32 io, const int32 data);
  89
  90 static int32 trace_level    = 0x00;     /* Disable all tracing by default */
  91
  92 static UNIT ss1_unit[] = {
  93     { UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }
  94 };
  95
  96 static REG ss1_reg[] = {
  97     { HRDATA (TRACELEVEL,   trace_level,           16), },
  98     { NULL }
  99 };
 100
 101 static MTAB ss1_mod[] = {
 102     { MTAB_XTD|MTAB_VDV,    0,              "IOBASE",   "IOBASE",   &set_iobase, &show_iobase, NULL },
 103     /* quiet, no warning messages       */
 104     { UNIT_SS1_VERBOSE, 0,                  "QUIET",    "QUIET",    NULL },
 105     /* verbose, show warning messages   */
 106     { UNIT_SS1_VERBOSE, UNIT_SS1_VERBOSE,   "VERBOSE",  "VERBOSE",  NULL },
 107     { 0 }
 108 };
 109
 110 DEVICE ss1_dev = {
 111     "SS1", ss1_unit, ss1_reg, ss1_mod,
 112     SS1_MAX_DRIVES, 10, 31, 1, SS1_MAX_DRIVES, SS1_MAX_DRIVES,
 113     NULL, NULL, &ss1_reset,
 114     NULL, NULL, NULL,
 115     &ss1_info_data, (DEV_DISABLE | DEV_DIS), 0,
 116     NULL, NULL, NULL
 117 };
 118
 119 /* Reset routine */
 120 static t_stat ss1_reset(DEVICE *dptr)
 121 {
 122     PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
 123
 124     if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
 125         sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, TRUE);
 126     } else {
 127         /* Connect SS1 at base address */
 128         if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, FALSE) != 0) {
 129             printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
 130             return SCPE_ARG;
 131         }
 132     }
 133     return SCPE_OK;
 134 }
 135
 136 static int32 ss1dev(const int32 port, const int32 io, const int32 data)
 137 {
 138     DBG_PRINT(("SS1: IO %s, Port %02x\n", io ? "WR" : "RD", port));
 139     if(io) {
 140         SS1_Write(port, data);
 141         return 0;
 142     } else {
 143         return(SS1_Read(port));
 144     }
 145 }
 146
 147 #define SS1_M8259_L     0x00
 148 #define SS1_M8259_H     0x01
 149 #define SS1_S8259_L     0x02
 150 #define SS1_S8259_H     0x03
 151 #define SS1_8253_TC0    0x04
 152 #define SS1_8253_TC1    0x05
 153 #define SS1_8253_TC2    0x06
 154 #define SS1_8253_CTL    0x07
 155 #define SS1_9511A_DATA  0x08
 156 #define SS1_9511A_CMD   0x09
 157 #define SS1_RTC_CMD     0x0A
 158 #define SS1_RTC_DATA    0x0B
 159 #define SS1_UART_DATA   0x0C
 160 #define SS1_UART_STAT   0x0D
 161 #define SS1_UART_MODE   0x0E
 162 #define SS1_UART_CMD    0x0F
 163
 164 extern int32 sio0d(const int32 port, const int32 io, const int32 data);
 165 extern int32 sio0s(const int32 port, const int32 io, const int32 data);
 166
 167 static uint8 SS1_Read(const uint32 Addr)
 168 {
 169     uint8 cData = 0x00;
 170
 171     switch(Addr & 0x0F) {
 172         case SS1_M8259_L:
 173         case SS1_M8259_H:
 174         case SS1_S8259_L:
 175         case SS1_S8259_H:
 176             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Interrupt Controller not Implemented." NLP, PCX));
 177             break;
 178         case SS1_8253_TC0:
 179         case SS1_8253_TC1:
 180         case SS1_8253_TC2:
 181         case SS1_8253_CTL:
 182             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Timer not Implemented." NLP, PCX));
 183             break;
 184         case SS1_9511A_DATA:
 185         case SS1_9511A_CMD:
 186             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Math Coprocessor not Implemented." NLP, PCX));
 187             break;
 188         case SS1_RTC_CMD:
 189         case SS1_RTC_DATA:
 190             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: RTC not Implemented." NLP, PCX));
 191             break;
 192         case SS1_UART_DATA:
 193             cData = sio0d(Addr, 0, 0);
 194             break;
 195         case SS1_UART_STAT:
 196             cData = sio0s(Addr, 0, 0);
 197             break;
 198         case SS1_UART_MODE:
 199         case SS1_UART_CMD:
 200             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: UART not Implemented." NLP, PCX));
 201             break;
 202     }
 203
 204     return (cData);
 205
 206 }
 207
 208 static uint8 SS1_Write(const uint32 Addr, uint8 cData)
 209 {
 210
 211     switch(Addr & 0x0F) {
 212         case SS1_M8259_L:
 213         case SS1_M8259_H:
 214         case SS1_S8259_L:
 215         case SS1_S8259_H:
 216             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Interrupt Controller not Implemented." NLP, PCX));
 217             break;
 218         case SS1_8253_TC0:
 219         case SS1_8253_TC1:
 220         case SS1_8253_TC2:
 221         case SS1_8253_CTL:
 222             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Timer not Implemented." NLP, PCX));
 223             break;
 224         case SS1_9511A_DATA:
 225         case SS1_9511A_CMD:
 226             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Math Coprocessor not Implemented." NLP, PCX));
 227             break;
 228         case SS1_RTC_CMD:
 229         case SS1_RTC_DATA:
 230             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: RTC not Implemented." NLP, PCX));
 231             break;
 232         case SS1_UART_DATA:
 233             sio0d(Addr, 1, cData);
 234             break;
 235         case SS1_UART_STAT:
 236             sio0s(Addr, 1, cData);
 237             break;
 238         case SS1_UART_MODE:
 239         case SS1_UART_CMD:
 240             TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: UART not Implemented." NLP, PCX));
 241             break;
 242     }
 243
 244     return(0);
 245 }
 246