HP2100/hp2100_cpu1.h

   1 /* hp2100_cpu1.h: HP 2100/1000 firmware dispatcher definitions
   2
   3    Copyright (c) 2006-2008, J. David Bryan
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of the author shall not
  23    be used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from the author.
  25
  26    30-Apr-08    JDB     Corrected OP_AFF to OP_AAFF for SIGNAL/1000
  27                         Removed unused operand patterns
  28    23-Feb-08    HV      Added more OP_* for SIGNAL/1000 and VIS
  29    28-Nov-07    JDB     Added fprint_ops, fprint_regs for debug printouts
  30    19-Oct-07    JDB     Revised OP_KKKAKK operand profile to OP_CCCACC for $LOC
  31    16-Oct-06    JDB     Generalized operands for F-Series FP types
  32    26-Sep-06    JDB     Split from hp2100_cpu1.c
  33 */
  34
  35 #ifndef _HP2100_CPU1_H_
  36 #define _HP2100_CPU1_H_
  37
  38
  39 /* Register print encoding. */
  40
  41 #define REG_COUNT       9                               /* count of print flags */
  42
  43 #define REG_CIR         (1 << 0)                        /* print central interrupt register */
  44 #define REG_A           (1 << 1)                        /* print A register */
  45 #define REG_B           (1 << 2)                        /* print B register */
  46 #define REG_E           (1 << 3)                        /* print E register */
  47 #define REG_X           (1 << 4)                        /* print X register */
  48 #define REG_Y           (1 << 5)                        /* print Y register */
  49 #define REG_O           (1 << 6)                        /* print O register */
  50 #define REG_P           (1 << 7)                        /* print P register */
  51 #define REG_P_REL       (1 << 8)                        /* print P register as relative */
  52
  53
  54 /* Operand processing encoding. */
  55
  56 /* Base operand types.  Note that all address encodings must be grouped together
  57    after OP_ADR. */
  58
  59 #define OP_NUL          0                               /* no operand */
  60 #define OP_IAR          1                               /* 1-word int in A reg */
  61 #define OP_JAB          2                               /* 2-word int in A/B regs */
  62 #define OP_FAB          3                               /* 2-word FP const in A/B regs */
  63 #define OP_CON          4                               /* inline 1-word constant */
  64 #define OP_VAR          5                               /* inline 1-word variable */
  65
  66 #define OP_ADR          6                               /* inline address */
  67 #define OP_ADK          7                               /* addr of 1-word int const */
  68 #define OP_ADD          8                               /* addr of 2-word int const */
  69 #define OP_ADF          9                               /* addr of 2-word FP const */
  70 #define OP_ADX         10                               /* addr of 3-word FP const */
  71 #define OP_ADT         11                               /* addr of 4-word FP const */
  72 #define OP_ADE         12                               /* addr of 5-word FP const */
  73
  74 #define OP_N_FLAGS      4                               /* number of bits needed for flags */
  75 #define OP_M_FLAGS      ((1 << OP_N_FLAGS) - 1)         /* mask for flag bits */
  76
  77 #define OP_N_F          (8 * sizeof (uint32) / OP_N_FLAGS)  /* max number of op fields */
  78
  79 #define OP_V_F1         (0 * OP_N_FLAGS)                /* 1st operand field */
  80 #define OP_V_F2         (1 * OP_N_FLAGS)                /* 2nd operand field */
  81 #define OP_V_F3         (2 * OP_N_FLAGS)                /* 3rd operand field */
  82 #define OP_V_F4         (3 * OP_N_FLAGS)                /* 4th operand field */
  83 #define OP_V_F5         (4 * OP_N_FLAGS)                /* 5th operand field */
  84 #define OP_V_F6         (5 * OP_N_FLAGS)                /* 6th operand field */
  85 #define OP_V_F7         (6 * OP_N_FLAGS)                /* 7th operand field */
  86 #define OP_V_F8         (7 * OP_N_FLAGS)                /* 8th operand field */
  87
  88 /* Operand processing patterns. */
  89
  90 #define OP_N            (OP_NUL << OP_V_F1)
  91 #define OP_I            (OP_IAR << OP_V_F1)
  92 #define OP_J            (OP_JAB << OP_V_F1)
  93 #define OP_R            (OP_FAB << OP_V_F1)
  94 #define OP_C            (OP_CON << OP_V_F1)
  95 #define OP_V            (OP_VAR << OP_V_F1)
  96 #define OP_A            (OP_ADR << OP_V_F1)
  97 #define OP_K            (OP_ADK << OP_V_F1)
  98 #define OP_D            (OP_ADD << OP_V_F1)
  99 #define OP_X            (OP_ADX << OP_V_F1)
 100 #define OP_T            (OP_ADT << OP_V_F1)
 101 #define OP_E            (OP_ADE << OP_V_F1)
 102
 103 #define OP_IA           ((OP_IAR << OP_V_F1) | (OP_ADR << OP_V_F2))
 104 #define OP_JA           ((OP_JAB << OP_V_F1) | (OP_ADR << OP_V_F2))
 105 #define OP_JD           ((OP_JAB << OP_V_F1) | (OP_ADD << OP_V_F2))
 106 #define OP_RC           ((OP_FAB << OP_V_F1) | (OP_CON << OP_V_F2))
 107 #define OP_RK           ((OP_FAB << OP_V_F1) | (OP_ADK << OP_V_F2))
 108 #define OP_RF           ((OP_FAB << OP_V_F1) | (OP_ADF << OP_V_F2))
 109 #define OP_CV           ((OP_CON << OP_V_F1) | (OP_VAR << OP_V_F2))
 110 #define OP_AC           ((OP_ADR << OP_V_F1) | (OP_CON << OP_V_F2))
 111 #define OP_AA           ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2))
 112 #define OP_AK           ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2))
 113 #define OP_AX           ((OP_ADR << OP_V_F1) | (OP_ADX << OP_V_F2))
 114 #define OP_AT           ((OP_ADR << OP_V_F1) | (OP_ADT << OP_V_F2))
 115 #define OP_KV           ((OP_ADK << OP_V_F1) | (OP_VAR << OP_V_F2))
 116 #define OP_KA           ((OP_ADK << OP_V_F1) | (OP_ADR << OP_V_F2))
 117 #define OP_KK           ((OP_ADK << OP_V_F1) | (OP_ADK << OP_V_F2))
 118
 119 #define OP_IIF          ((OP_IAR << OP_V_F1) | (OP_IAR << OP_V_F2) | \
 120                          (OP_ADF << OP_V_F3))
 121
 122 #define OP_IAT          ((OP_IAR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 123                          (OP_ADT << OP_V_F3))
 124
 125 #define OP_CVA          ((OP_CON << OP_V_F1) | (OP_VAR << OP_V_F2) | \
 126                          (OP_ADR << OP_V_F3))
 127
 128 #define OP_AAA          ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 129                          (OP_ADR << OP_V_F3))
 130
 131 #define OP_AAF          ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 132                          (OP_ADF << OP_V_F3))
 133
 134 #define OP_AAX          ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 135                          (OP_ADX << OP_V_F3))
 136
 137 #define OP_AAT          ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 138                          (OP_ADT << OP_V_F3))
 139
 140 #define OP_AKA          ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
 141                          (OP_ADR << OP_V_F3))
 142
 143 #define OP_AKK          ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
 144                          (OP_ADK << OP_V_F3))
 145
 146 #define OP_AXX          ((OP_ADR << OP_V_F1) | (OP_ADX << OP_V_F2) | \
 147                          (OP_ADX << OP_V_F3))
 148
 149 #define OP_ATT          ((OP_ADR << OP_V_F1) | (OP_ADT << OP_V_F2) | \
 150                          (OP_ADT << OP_V_F3))
 151
 152 #define OP_AEE          ((OP_ADR << OP_V_F1) | (OP_ADE << OP_V_F2) | \
 153                          (OP_ADE << OP_V_F3))
 154
 155 #define OP_AAXX         ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 156                          (OP_ADX << OP_V_F3) | (OP_ADX << OP_V_F4))
 157
 158 #define OP_AAFF         ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 159                          (OP_ADF << OP_V_F3) | (OP_ADF << OP_V_F4))
 160
 161 #define OP_AAKK         ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 162                          (OP_ADK << OP_V_F3) | (OP_ADK << OP_V_F4))
 163
 164 #define OP_KKKK         ((OP_ADK << OP_V_F1) | (OP_ADK << OP_V_F2) | \
 165                          (OP_ADK << OP_V_F3) | (OP_ADK << OP_V_F4))
 166
 167 #define OP_AAAKK        ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 168                          (OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \
 169                          (OP_ADK << OP_V_F5))
 170
 171 #define OP_AKAKK        ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
 172                          (OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \
 173                          (OP_ADK << OP_V_F5))
 174
 175 #define OP_AAACCC       ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 176                          (OP_ADR << OP_V_F3) | (OP_CON << OP_V_F4) | \
 177                          (OP_CON << OP_V_F5) | (OP_CON << OP_V_F6))
 178
 179 #define OP_AAFFKK       ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 180                          (OP_ADF << OP_V_F3) | (OP_ADF << OP_V_F4) | \
 181                          (OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))
 182
 183 #define OP_AAKAKK       ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 184                          (OP_ADK << OP_V_F3) | (OP_ADR << OP_V_F4) | \
 185                          (OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))
 186
 187 #define OP_CATAKK       ((OP_CON << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 188                          (OP_ADT << OP_V_F3) | (OP_ADR << OP_V_F4) | \
 189                          (OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))
 190
 191 #define OP_CCCACC       ((OP_CON << OP_V_F1) | (OP_CON << OP_V_F2) | \
 192                          (OP_CON << OP_V_F3) | (OP_ADR << OP_V_F4) | \
 193                          (OP_CON << OP_V_F5) | (OP_CON << OP_V_F6))
 194
 195 #define OP_AAAFFKK      ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 196                          (OP_ADR << OP_V_F3) | (OP_ADF << OP_V_F4) | \
 197                          (OP_ADF << OP_V_F5) | (OP_ADK << OP_V_F6) | \
 198                          (OP_ADK << OP_V_F7))
 199
 200 #define OP_AKAKAKK      ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
 201                          (OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \
 202                          (OP_ADR << OP_V_F5) | (OP_ADK << OP_V_F6) | \
 203                          (OP_ADK << OP_V_F7))
 204
 205 #define OP_AAKAKAKK     ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
 206                          (OP_ADK << OP_V_F3) | (OP_ADR << OP_V_F4) | \
 207                          (OP_ADK << OP_V_F5) | (OP_ADR << OP_V_F6) | \
 208                          (OP_ADK << OP_V_F7) | (OP_ADK << OP_V_F8))
 209
 210 #define OP_CCACACCA     ((OP_CON << OP_V_F1) | (OP_CON << OP_V_F2) | \
 211                          (OP_ADR << OP_V_F3) | (OP_CON << OP_V_F4) | \
 212                          (OP_ADR << OP_V_F5) | (OP_CON << OP_V_F6) | \
 213                          (OP_CON << OP_V_F7) | (OP_ADR << OP_V_F8))
 214
 215
 216 /* Operand precisions (compatible with F-Series FPP):
 217
 218     - S = 1-word integer
 219     - D = 2-word integer
 220     - F = 2-word single-precision floating-point
 221     - X = 3-word extended-precision floating-point
 222     - T = 4-word double-precision floating-point
 223     - E = 5-word expanded-exponent floating-point
 224     - A = null operand (operand is in FPP accumulator)
 225
 226    5-word floating-point numbers are supported by the F-Series Floating-Point
 227    Processor hardware, but the instruction codes are not documented.
 228
 229    Note that ordering is important, as we depend on the "fp" type codes to
 230    reflect the number of words needed.
 231 */
 232
 233 typedef enum { in_s, in_d, fp_f, fp_x, fp_t, fp_e, fp_a } OPSIZE;
 234
 235
 236 /* Conversion from operand size to word count. */
 237
 238 #define TO_COUNT(s)     ((s == fp_a) ? 0 : (uint32) (s + (s < fp_f)))
 239
 240
 241 /* HP in-memory representation of a packed floating-point number.
 242    Actual value will use two, three, four, or five words, as needed. */
 243
 244 typedef uint16 FPK[5];
 245
 246
 247 /* Operand processing types.
 248
 249    NOTE: Microsoft VC++ 6.0 does not support the C99 standard, so we cannot
 250    initialize unions by arbitrary variant ("designated initializers").
 251    Therefore, we follow the C90 form of initializing via the first named
 252    variant.  The FPK variant must appear first in the OP structure, as we define
 253    a number of FPK constants in other modules.
 254 */
 255
 256 typedef union {                                         /* general operand */
 257     FPK fpk;                                            /* floating-point value */
 258     uint16 word;                                        /* 16-bit integer */
 259     uint32 dword;                                       /* 32-bit integer */
 260     } OP;
 261
 262 typedef OP OPS[OP_N_F];                                 /* operand array */
 263
 264 typedef uint32 OP_PAT;                                  /* operand pattern */
 265
 266
 267 /* Microcode dispatcher functions. */
 268
 269 t_stat cpu_eau   (uint32 IR, uint32 intrq);                 /* EAU group simulator */
 270 t_stat cpu_uig_0 (uint32 IR, uint32 intrq, uint32 iotrap);  /* UIG group 0 dispatcher */
 271 t_stat cpu_uig_1 (uint32 IR, uint32 intrq, uint32 iotrap);  /* UIG group 1 dispatcher */
 272
 273 /* Microcode helper functions. */
 274
 275 OP     ReadOp  (uint32 va, OPSIZE precision);               /* generalized operand read */
 276 void   WriteOp (uint32 va, OP operand, OPSIZE precision);   /* generalized operand write */
 277 t_stat cpu_ops (OP_PAT pattern, OPS op, uint32 irq);        /* operand processor */
 278
 279 void fprint_ops (OP_PAT pattern, OPS op);                   /* debug print operands */
 280 void fprint_regs (char *caption, uint32 regs, uint32 base); /* debug print CPU registers */
 281
 282 #endif