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First Commit of my working state
[simh.git] / HP2100 / hp2100_cpu2.c
1 /* hp2100_cpu2.c: HP 2100/1000 FP/DMS/EIG/IOP instructions
2
3 Copyright (c) 2005-2006, Robert M. Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 CPU2 Floating-point, dynamic mapping, extended, and I/O processor
27 instructions
28
29 19-Dec-06 JDB DMS self-test now executes as NOP on 1000-M
30 01-Dec-06 JDB Substitutes FPP for firmware FP if HAVE_INT64
31 26-Sep-06 JDB Moved from hp2100_cpu1.c to simplify extensions
32 22-Feb-05 JDB Fixed missing MPCK on JRS target
33 21-Jan-05 JDB Reorganized CPU option and operand processing flags
34 Split code along microcode modules
35 15-Jan-05 RMS Cloned from hp2100_cpu.c
36
37 Primary references:
38 - HP 1000 M/E/F-Series Computers Technical Reference Handbook
39 (5955-0282, Mar-1980)
40 - HP 1000 M/E/F-Series Computers Engineering and Reference Documentation
41 (92851-90001, Mar-1981)
42 - Macro/1000 Reference Manual (92059-90001, Dec-1992)
43
44 Additional references are listed with the associated firmware
45 implementations, as are the HP option model numbers pertaining to the
46 applicable CPUs.
47 */
48
49 #include "hp2100_defs.h"
50 #include "hp2100_cpu.h"
51 #include "hp2100_cpu1.h"
52
53 #if !defined (HAVE_INT64) /* int64 support unavailable */
54
55 #include "hp2100_fp.h"
56
57 t_stat cpu_fp (uint32 IR, uint32 intrq); /* Firmware Floating Point */
58
59 #endif /* int64 support unavailable */
60
61 t_stat cpu_dms (uint32 IR, uint32 intrq); /* Dynamic mapping system */
62 t_stat cpu_eig (uint32 IR, uint32 intrq); /* Extended instruction group */
63 t_stat cpu_iop (uint32 IR, uint32 intrq); /* 2000 I/O Processor */
64
65
66 #if !defined (HAVE_INT64) /* int64 support unavailable */
67
68 /* Single-Precision Floating Point Instructions
69
70 The 2100 and 1000 CPUs share the single-precision (two word) floating-point
71 instruction codes. Floating-point firmware was an option on the 2100 and was
72 standard on the 1000-M and E. The 1000-F had a standard hardware Floating
73 Point Processor that executed these six instructions and added extended- and
74 double-precision floating- point instructions, as well as double-integer
75 instructions (the FPP is simulated separately).
76
77 Option implementation by CPU was as follows:
78
79 2114 2115 2116 2100 1000-M 1000-E 1000-F
80 ------ ------ ------ ------ ------ ------ ------
81 N/A N/A N/A 12901A std std N/A
82
83 The instruction codes for the 2100 and 1000-M/E systems are mapped to
84 routines as follows:
85
86 Instr. 2100/1000-M/E Description
87 ------ ------------- -----------------------------------
88 105000 FAD Single real add
89 105020 FSB Single real subtract
90 105040 FMP Single real multiply
91 105060 FDV Single real divide
92 105100 FIX Single integer to single real fix
93 105120 FLT Single real to single integer float
94
95 Bits 3-0 are not decoded by these instructions, so FAD (e.g.) would be
96 executed by any instruction in the range 105000-105017.
97
98 Implementation note: rather than have two simulators that each executes the
99 single-precision FP instruction set, we compile conditionally, based on the
100 availability of 64-bit integer support in the host compiler. 64-bit integers
101 are required for the FPP, so if they are available, then the FPP is used to
102 handle the six single-precision instructions for the 2100 and M/E-Series, and
103 this function is omitted. If support is unavailable, this function is used
104 instead.
105
106 Implementation note: the operands to FAD, etc. are floating-point values, so
107 OP_F would normally be used. However, the firmware FP support routines want
108 floating-point operands as 32-bit integer values, so OP_D is used to achieve
109 this.
110 */
111
112 static const OP_PAT op_fp[8] = {
113 OP_D, OP_D, OP_D, OP_D, /* FAD FSB FMP FDV */
114 OP_N, OP_N, OP_N, OP_N /* FIX FLT --- --- */
115 };
116
117 t_stat cpu_fp (uint32 IR, uint32 intrq)
118 {
119 t_stat reason = SCPE_OK;
120 OPS op;
121 uint32 entry;
122
123 if ((cpu_unit.flags & UNIT_FP) == 0) /* FP option installed? */
124 return stop_inst;
125
126 entry = (IR >> 4) & 017; /* mask to entry point */
127
128 if (op_fp[entry] != OP_N)
129 if (reason = cpu_ops (op_fp[entry], op, intrq)) /* get instruction operands */
130 return reason;
131
132 switch (entry) { /* decode IR<7:4> */
133
134 case 000: /* FAD 105000 (OP_D) */
135 O = f_as (op[0].dword, 0); /* add, upd ovflo */
136 break;
137
138 case 001: /* FSB 105020 (OP_D) */
139 O = f_as (op[0].dword, 1); /* sub, upd ovflo */
140 break;
141
142 case 002: /* FMP 105040 (OP_D) */
143 O = f_mul (op[0].dword); /* mul, upd ovflo */
144 break;
145
146 case 003: /* FDV 105060 (OP_D) */
147 O = f_div (op[0].dword); /* div, upd ovflo */
148 break;
149
150 case 004: /* FIX 105100 (OP_N) */
151 O = f_fix (); /* fix, upd ovflo */
152 break;
153
154 case 005: /* FLT 105120 (OP_N) */
155 O = f_flt (); /* float, upd ovflo */
156 break;
157
158 default: /* should be impossible */
159 return SCPE_IERR;
160 }
161
162 return reason;
163 }
164
165 #endif /* int64 support unavailable */
166
167
168 /* Dynamic Mapping System
169
170 The 1000 Dynamic Mapping System (DMS) consisted of the 12731A Memory
171 Expansion Module (MEM) card and 38 instructions to expand the basic 32K
172 logical address space to a 1024K physical space. The MEM provided four maps
173 of 32 mapping registers each: a system map, a user map, and two DCPC maps.
174 DMS worked in conjunction with memory protect to provide a "protected mode"
175 in which memory read and write violations could be trapped, and that
176 inhibited "privileged" instruction execution that attempted to alter the
177 memory mapping.
178
179 Option implementation by CPU was as follows:
180
181 2114 2115 2116 2100 1000-M 1000-E 1000-F
182 ------ ------ ------ ------ ------ ------ ------
183 N/A N/A N/A N/A 12976B 13307B std
184
185 The instruction codes are mapped to routines as follows:
186
187 Instr. 1000-M 1000-E/F Instr. 1000-M 1000-E/F
188 ------ ------ -------- ------ ------ --------
189 10x700 [xmm] [xmm] 10x720 XMM XMM
190 10x701 [nop] [test] 10x721 XMS XMS
191 10x702 MBI MBI 10x722 XM* XM*
192 10x703 MBF MBF 10x723 [nop] [nop]
193 10x704 MBW MBW 10x724 XL* XL*
194 10x705 MWI MWI 10x725 XS* XS*
195 10x706 MWF MWF 10x726 XC* XC*
196 10x707 MWW MWW 10x727 LF* LF*
197 10x710 SY* SY* 10x730 RS* RS*
198
199 10x711 US* US* 10x731 RV* RV*
200 10x712 PA* PA* 10x732 DJP DJP
201 10x713 PB* PB* 10x733 DJS DJS
202 10x714 SSM SSM 10x734 SJP SJP
203 10x715 JRS JRS 10x735 SJS SJS
204 10x716 [nop] [nop] 10x736 UJP UJP
205 10x717 [nop] [nop] 10x737 UJS UJS
206
207 Instructions that use IR bit 9 to select the A or B register are designated
208 with a * above (e.g., 101710 is SYA, and 105710 is SYB). For those that do
209 not use this feature, either the 101xxx or 105xxx code will execute the
210 corresponding instruction, although the 105xxx form is the documented
211 instruction code.
212
213 Notes:
214
215 1. Instruction code 10x700 will execute the XMM instruction, although
216 10x720 is the documented instruction value.
217
218 2. Instruction code 10x701 will complement the A or B register, as
219 indicated, on 1000-E and F-Series machines. This instruction is a NOP
220 on M-Series machines.
221
222 3. The DMS privilege violation rules are:
223 - load map and CTL5 set (XMM, XMS, XM*, SY*, US*, PA*, PB*)
224 - load state or fence and UMAP set (JRS, DJP, DJS, SJP, SJS, UJP, UJS, LF*)
225
226 4. The 1000 manual is incorrect in stating that M*I, M*W, XS* are
227 privileged.
228 */
229
230 static const OP_PAT op_dms[32] = {
231 OP_N, OP_N, OP_N, OP_N, /* [xmm] [test] MBI MBF */
232 OP_N, OP_N, OP_N, OP_N, /* MBW MWI MWF MWW */
233 OP_N, OP_N, OP_N, OP_N, /* SYA/B USA/B PAA/B PBA/B */
234 OP_A, OP_KA, OP_N, OP_N, /* SSM JRS nop nop */
235 OP_N, OP_N, OP_N, OP_N, /* XMM XMS XMA/B nop */
236 OP_A, OP_A, OP_A, OP_N, /* XLA/B XSA/B XCA/B LFA/B */
237 OP_N, OP_N, OP_A, OP_A, /* RSA/B RVA/B DJP DJS */
238 OP_A, OP_A, OP_A, OP_A /* SJP SJS UJP UJS */
239 };
240
241 t_stat cpu_dms (uint32 IR, uint32 intrq)
242 {
243 t_stat reason = SCPE_OK;
244 OPS op;
245 uint32 entry, absel;
246 uint32 i, t, mapi, mapj;
247
248 if ((cpu_unit.flags & UNIT_DMS) == 0) /* DMS option installed? */
249 return stop_inst;
250
251 absel = (IR & I_AB)? 1: 0; /* get A/B select */
252 entry = IR & 037; /* mask to entry point */
253
254 if (op_dms[entry] != OP_N)
255 if (reason = cpu_ops (op_dms[entry], op, intrq)) /* get instruction operands */
256 return reason;
257
258 switch (entry) { /* decode IR<3:0> */
259
260 /* DMS module 1 */
261
262 case 000: /* [undefined] 105700 (OP_N) */
263 goto XMM; /* decodes as XMM */
264
265 case 001: /* [self test] 105701 (OP_N) */
266 if (UNIT_CPU_MODEL != UNIT_1000_M) /* executes as NOP on 1000-M */
267 ABREG[absel] = ~ABREG[absel]; /* CMA or CMB */
268 break;
269
270 case 002: /* MBI 105702 (OP_N) */
271 AR = AR & ~1; /* force A, B even */
272 BR = BR & ~1;
273 while (XR != 0) { /* loop */
274 t = ReadB (AR); /* read curr */
275 WriteBA (BR, t); /* write alt */
276 AR = (AR + 1) & DMASK; /* incr ptrs */
277 BR = (BR + 1) & DMASK;
278 XR = (XR - 1) & DMASK;
279 if (XR && intrq && !(AR & 1)) { /* more, int, even? */
280 PC = err_PC; /* stop for now */
281 break;
282 }
283 }
284 break;
285
286 case 003: /* MBF 105703 (OP_N) */
287 AR = AR & ~1; /* force A, B even */
288 BR = BR & ~1;
289 while (XR != 0) { /* loop */
290 t = ReadBA (AR); /* read alt */
291 WriteB (BR, t); /* write curr */
292 AR = (AR + 1) & DMASK; /* incr ptrs */
293 BR = (BR + 1) & DMASK;
294 XR = (XR - 1) & DMASK;
295 if (XR && intrq && !(AR & 1)) { /* more, int, even? */
296 PC = err_PC; /* stop for now */
297 break;
298 }
299 }
300 break;
301
302 case 004: /* MBW 105704 (OP_N) */
303 AR = AR & ~1; /* force A, B even */
304 BR = BR & ~1;
305 while (XR != 0) { /* loop */
306 t = ReadBA (AR); /* read alt */
307 WriteBA (BR, t); /* write alt */
308 AR = (AR + 1) & DMASK; /* incr ptrs */
309 BR = (BR + 1) & DMASK;
310 XR = (XR - 1) & DMASK;
311 if (XR && intrq && !(AR & 1)) { /* more, int, even? */
312 PC = err_PC; /* stop for now */
313 break;
314 }
315 }
316 break;
317
318 case 005: /* MWI 105705 (OP_N) */
319 while (XR != 0) { /* loop */
320 t = ReadW (AR & VAMASK); /* read curr */
321 WriteWA (BR & VAMASK, t); /* write alt */
322 AR = (AR + 1) & DMASK; /* incr ptrs */
323 BR = (BR + 1) & DMASK;
324 XR = (XR - 1) & DMASK;
325 if (XR && intrq) { /* more and intr? */
326 PC = err_PC; /* stop for now */
327 break;
328 }
329 }
330 break;
331
332 case 006: /* MWF 105706 (OP_N) */
333 while (XR != 0) { /* loop */
334 t = ReadWA (AR & VAMASK); /* read alt */
335 WriteW (BR & VAMASK, t); /* write curr */
336 AR = (AR + 1) & DMASK; /* incr ptrs */
337 BR = (BR + 1) & DMASK;
338 XR = (XR - 1) & DMASK;
339 if (XR && intrq) { /* more and intr? */
340 PC = err_PC; /* stop for now */
341 break;
342 }
343 }
344 break;
345
346 case 007: /* MWW 105707 (OP_N) */
347 while (XR != 0) { /* loop */
348 t = ReadWA (AR & VAMASK); /* read alt */
349 WriteWA (BR & VAMASK, t); /* write alt */
350 AR = (AR + 1) & DMASK; /* incr ptrs */
351 BR = (BR + 1) & DMASK;
352 XR = (XR - 1) & DMASK;
353 if (XR && intrq) { /* more and intr? */
354 PC = err_PC; /* stop for now */
355 break;
356 }
357 }
358 break;
359
360 case 010: /* SYA, SYB 10x710 (OP_N) */
361 case 011: /* USA, USB 10x711 (OP_N) */
362 case 012: /* PAA, PAB 10x712 (OP_N) */
363 case 013: /* PBA, PBB 10x713 (OP_N) */
364 mapi = (IR & 03) << VA_N_PAG; /* map base */
365 if (ABREG[absel] & SIGN) { /* store? */
366 for (i = 0; i < MAP_LNT; i++) {
367 t = dms_rmap (mapi + i); /* map to memory */
368 WriteW ((ABREG[absel] + i) & VAMASK, t);
369 }
370 }
371 else { /* load */
372 dms_viol (err_PC, MVI_PRV); /* priv if PRO */
373 for (i = 0; i < MAP_LNT; i++) {
374 t = ReadW ((ABREG[absel] + i) & VAMASK);
375 dms_wmap (mapi + i, t); /* mem to map */
376 }
377 }
378 ABREG[absel] = (ABREG[absel] + MAP_LNT) & DMASK;
379 break;
380
381 case 014: /* SSM 105714 (OP_A) */
382 WriteW (op[0].word, dms_upd_sr ()); /* store stat */
383 break;
384
385 case 015: /* JRS 105715 (OP_KA) */
386 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
387 dms_enb = 0; /* assume off */
388 dms_ump = SMAP;
389 if (op[0].word & 0100000) { /* set enable? */
390 dms_enb = 1;
391 if (op[0].word & 0040000) dms_ump = UMAP; /* set/clr usr */
392 }
393 mp_dms_jmp (op[1].word); /* mpck jmp target */
394 PCQ_ENTRY; /* save old PC */
395 PC = op[1].word; /* jump */
396 ion_defer = 1; /* defer intr */
397 break;
398
399 /* DMS module 2 */
400
401 case 020: /* XMM 105720 (OP_N) */
402 XMM:
403 if (XR == 0) break; /* nop? */
404 while (XR != 0) { /* loop */
405 if (XR & SIGN) { /* store? */
406 t = dms_rmap (AR); /* map to mem */
407 WriteW (BR & VAMASK, t);
408 XR = (XR + 1) & DMASK;
409 }
410 else { /* load */
411 dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
412 t = ReadW (BR & VAMASK); /* mem to map */
413 dms_wmap (AR, t);
414 XR = (XR - 1) & DMASK;
415 }
416 AR = (AR + 1) & DMASK;
417 BR = (BR + 1) & DMASK;
418 if (intrq && ((XR & 017) == 017)) { /* intr, grp of 16? */
419 PC = err_PC; /* stop for now */
420 break;
421 }
422 }
423 break;
424
425 case 021: /* XMS 105721 (OP_N) */
426 if ((XR & SIGN) || (XR == 0)) break; /* nop? */
427 dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
428 while (XR != 0) {
429 dms_wmap (AR, BR); /* AR to map */
430 XR = (XR - 1) & DMASK;
431 AR = (AR + 1) & DMASK;
432 BR = (BR + 1) & DMASK;
433 if (intrq && ((XR & 017) == 017)) { /* intr, grp of 16? */
434 PC = err_PC;
435 break;
436 }
437 }
438 break;
439
440 case 022: /* XMA, XMB 10x722 (OP_N) */
441 dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
442 if (ABREG[absel] & 0100000) mapi = UMAP;
443 else mapi = SMAP;
444 if (ABREG[absel] & 0000001) mapj = PBMAP;
445 else mapj = PAMAP;
446 for (i = 0; i < MAP_LNT; i++) {
447 t = dms_rmap (mapi + i); /* read map */
448 dms_wmap (mapj + i, t); /* write map */
449 }
450 break;
451
452 case 024: /* XLA, XLB 10x724 (OP_A) */
453 ABREG[absel] = ReadWA (op[0].word); /* load alt */
454 break;
455
456 case 025: /* XSA, XSB 10x725 (OP_A) */
457 WriteWA (op[0].word, ABREG[absel]); /* store alt */
458 break;
459
460 case 026: /* XCA, XCB 10x726 (OP_A) */
461 if (ABREG[absel] != ReadWA (op[0].word)) /* compare alt */
462 PC = (PC + 1) & VAMASK;
463 break;
464
465 case 027: /* LFA, LFB 10x727 (OP_N) */
466 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
467 dms_sr = (dms_sr & ~(MST_FLT | MST_FENCE)) |
468 (ABREG[absel] & (MST_FLT | MST_FENCE));
469 break;
470
471 case 030: /* RSA, RSB 10x730 (OP_N) */
472 ABREG[absel] = dms_upd_sr (); /* save stat */
473 break;
474
475 case 031: /* RVA, RVB 10x731 (OP_N) */
476 ABREG[absel] = dms_vr; /* save viol */
477 break;
478
479 case 032: /* DJP 105732 (OP_A) */
480 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
481 mp_dms_jmp (op[0].word); /* validate jump addr */
482 PCQ_ENTRY; /* save curr PC */
483 PC = op[0].word; /* new PC */
484 dms_enb = 0; /* disable map */
485 dms_ump = SMAP;
486 ion_defer = 1;
487 break;
488
489 case 033: /* DJS 105733 (OP_A) */
490 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
491 WriteW (op[0].word, PC); /* store ret addr */
492 PCQ_ENTRY; /* save curr PC */
493 PC = (op[0].word + 1) & VAMASK; /* new PC */
494 dms_enb = 0; /* disable map */
495 dms_ump = SMAP;
496 ion_defer = 1; /* defer intr */
497 break;
498
499 case 034: /* SJP 105734 (OP_A) */
500 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
501 mp_dms_jmp (op[0].word); /* validate jump addr */
502 PCQ_ENTRY; /* save curr PC */
503 PC = op[0].word; /* jump */
504 dms_enb = 1; /* enable system */
505 dms_ump = SMAP;
506 ion_defer = 1; /* defer intr */
507 break;
508
509 case 035: /* SJS 105735 (OP_A) */
510 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
511 t = PC; /* save retn addr */
512 PCQ_ENTRY; /* save curr PC */
513 PC = (op[0].word + 1) & VAMASK; /* new PC */
514 dms_enb = 1; /* enable system */
515 dms_ump = SMAP;
516 WriteW (op[0].word, t); /* store ret addr */
517 ion_defer = 1; /* defer intr */
518 break;
519
520 case 036: /* UJP 105736 (OP_A) */
521 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
522 mp_dms_jmp (op[0].word); /* validate jump addr */
523 PCQ_ENTRY; /* save curr PC */
524 PC = op[0].word; /* jump */
525 dms_enb = 1; /* enable user */
526 dms_ump = UMAP;
527 ion_defer = 1; /* defer intr */
528 break;
529
530 case 037: /* UJS 105737 (OP_A) */
531 if (dms_ump) dms_viol (err_PC, MVI_PRV); /* priv viol if prot */
532 t = PC; /* save retn addr */
533 PCQ_ENTRY; /* save curr PC */
534 PC = (op[0].word + 1) & VAMASK; /* new PC */
535 dms_enb = 1; /* enable user */
536 dms_ump = UMAP;
537 WriteW (op[0].word, t); /* store ret addr */
538 ion_defer = 1; /* defer intr */
539 break;
540
541 default: /* others NOP */
542 break;
543 }
544
545 return reason;
546 }
547
548
549 /* Extended Instruction Group
550
551 The Extended Instruction Group (EIG) adds 32 index and 10 bit/byte/word
552 manipulation instructions to the 1000 base set. These instructions
553 use the new X and Y index registers that were added to the 1000.
554
555 Option implementation by CPU was as follows:
556
557 2114 2115 2116 2100 1000-M 1000-E 1000-F
558 ------ ------ ------ ------ ------ ------ ------
559 N/A N/A N/A N/A std std std
560
561 The instruction codes are mapped to routines as follows:
562
563 Instr. 1000-M/E/F Instr. 1000-M/E/F
564 ------ ---------- ------ ----------
565 10x740 S*X 10x760 ISX
566 10x741 C*X 10x761 DSX
567 10x742 L*X 10x762 JLY
568 10x743 STX 10x763 LBT
569 10x744 CX* 10x764 SBT
570 10x745 LDX 10x765 MBT
571 10x746 ADX 10x766 CBT
572 10x747 X*X 10x767 SFB
573
574 10x750 S*Y 10x770 ISY
575 10x751 C*Y 10x771 DSY
576 10x752 L*Y 10x772 JPY
577 10x753 STY 10x773 SBS
578 10x754 CY* 10x774 CBS
579 10x755 LDY 10x775 TBS
580 10x756 ADY 10x776 CMW
581 10x757 X*Y 10x777 MVW
582
583 Instructions that use IR bit 9 to select the A or B register are designated
584 with a * above (e.g., 101740 is SAX, and 105740 is SBX). For those that do
585 not use this feature, either the 101xxx or 105xxx code will execute the
586 corresponding instruction, although the 105xxx form is the documented
587 instruction code.
588
589 Notes:
590
591 1. The LBT, SBT, MBT, and MVW instructions are used as part of the 2100 IOP
592 implementation. When so called, the MBT and MVW instructions have the
593 additional restriction that the count must be positive.
594 */
595
596 static const OP_PAT op_eig[32] = {
597 OP_A, OP_N, OP_A, OP_A, /* S*X C*X L*X STX */
598 OP_N, OP_K, OP_K, OP_N, /* CX* LDX ADX X*X */
599 OP_A, OP_N, OP_A, OP_A, /* S*Y C*Y L*Y STY */
600 OP_N, OP_K, OP_K, OP_N, /* CY* LDY ADY X*Y */
601 OP_N, OP_N, OP_A, OP_N, /* ISX DSX JLY LBT */
602 OP_N, OP_KV, OP_KV, OP_N, /* SBT MBT CBT SFB */
603 OP_N, OP_N, OP_C, OP_KA, /* ISY DSY JPY SBS */
604 OP_KA, OP_KK, OP_KV, OP_KV /* CBS TBS CMW MVW */
605 };
606
607 t_stat cpu_eig (uint32 IR, uint32 intrq)
608 {
609 t_stat reason = SCPE_OK;
610 OPS op;
611 uint32 entry, absel;
612 uint32 t, v1, v2, wc;
613 int32 sop1, sop2;
614
615 absel = (IR & I_AB)? 1: 0; /* get A/B select */
616 entry = IR & 037; /* mask to entry point */
617
618 if (op_eig[entry] != OP_N)
619 if (reason = cpu_ops (op_eig[entry], op, intrq)) /* get instruction operands */
620 return reason;
621
622 switch (entry) { /* decode IR<4:0> */
623
624 /* EIG module 1 */
625
626 case 000: /* SAX, SBX 10x740 (OP_A) */
627 op[0].word = (op[0].word + XR) & VAMASK; /* indexed addr */
628 WriteW (op[0].word, ABREG[absel]); /* store */
629 break;
630
631 case 001: /* CAX, CBX 10x741 (OP_N) */
632 XR = ABREG[absel]; /* copy to XR */
633 break;
634
635 case 002: /* LAX, LBX 10x742 (OP_A) */
636 op[0].word = (op[0].word + XR) & VAMASK; /* indexed addr */
637 ABREG[absel] = ReadW (op[0].word); /* load */
638 break;
639
640 case 003: /* STX 105743 (OP_A) */
641 WriteW (op[0].word, XR); /* store XR */
642 break;
643
644 case 004: /* CXA, CXB 10x744 (OP_N) */
645 ABREG[absel] = XR; /* copy from XR */
646 break;
647
648 case 005: /* LDX 105745 (OP_K)*/
649 XR = op[0].word; /* load XR */
650 break;
651
652 case 006: /* ADX 105746 (OP_K) */
653 t = XR + op[0].word; /* add to XR */
654 if (t > DMASK) E = 1; /* set E, O */
655 if (((~XR ^ op[0].word) & (XR ^ t)) & SIGN) O = 1;
656 XR = t & DMASK;
657 break;
658
659 case 007: /* XAX, XBX 10x747 (OP_N) */
660 t = XR; /* exchange XR */
661 XR = ABREG[absel];
662 ABREG[absel] = t;
663 break;
664
665 case 010: /* SAY, SBY 10x750 (OP_A) */
666 op[0].word = (op[0].word + YR) & VAMASK; /* indexed addr */
667 WriteW (op[0].word, ABREG[absel]); /* store */
668 break;
669
670 case 011: /* CAY, CBY 10x751 (OP_N) */
671 YR = ABREG[absel]; /* copy to YR */
672 break;
673
674 case 012: /* LAY, LBY 10x752 (OP_A) */
675 op[0].word = (op[0].word + YR) & VAMASK; /* indexed addr */
676 ABREG[absel] = ReadW (op[0].word); /* load */
677 break;
678
679 case 013: /* STY 105753 (OP_A) */
680 WriteW (op[0].word, YR); /* store YR */
681 break;
682
683 case 014: /* CYA, CYB 10x754 (OP_N) */
684 ABREG[absel] = YR; /* copy from YR */
685 break;
686
687 case 015: /* LDY 105755 (OP_K) */
688 YR = op[0].word; /* load YR */
689 break;
690
691 case 016: /* ADY 105756 (OP_K) */
692 t = YR + op[0].word; /* add to YR */
693 if (t > DMASK) E = 1; /* set E, O */
694 if (((~YR ^ op[0].word) & (YR ^ t)) & SIGN) O = 1;
695 YR = t & DMASK;
696 break;
697
698 case 017: /* XAY, XBY 10x757 (OP_N) */
699 t = YR; /* exchange YR */
700 YR = ABREG[absel];
701 ABREG[absel] = t;
702 break;
703
704 /* EIG module 2 */
705
706 case 020: /* ISX 105760 (OP_N) */
707 XR = (XR + 1) & DMASK; /* incr XR */
708 if (XR == 0) PC = (PC + 1) & VAMASK; /* skip if zero */
709 break;
710
711 case 021: /* DSX 105761 (OP_N) */
712 XR = (XR - 1) & DMASK; /* decr XR */
713 if (XR == 0) PC = (PC + 1) & VAMASK; /* skip if zero */
714 break;
715
716 case 022: /* JLY 105762 (OP_A) */
717 mp_dms_jmp (op[0].word); /* validate jump addr */
718 PCQ_ENTRY;
719 YR = PC; /* ret addr to YR */
720 PC = op[0].word; /* jump */
721 break;
722
723 case 023: /* LBT 105763 (OP_N) */
724 AR = ReadB (BR); /* load byte */
725 BR = (BR + 1) & DMASK; /* incr ptr */
726 break;
727
728 case 024: /* SBT 105764 (OP_N) */
729 WriteB (BR, AR); /* store byte */
730 BR = (BR + 1) & DMASK; /* incr ptr */
731 break;
732
733 case 025: /* MBT 105765 (OP_KV) */
734 wc = ReadW (op[1].word); /* get continuation count */
735 if (wc == 0) wc = op[0].word; /* none? get initiation count */
736 if ((wc & SIGN) &&
737 (UNIT_CPU_TYPE == UNIT_TYPE_2100))
738 break; /* < 0 is NOP for 2100 IOP */
739 while (wc != 0) { /* while count */
740 WriteW (op[1].word, wc); /* for MP abort */
741 t = ReadB (AR); /* move byte */
742 WriteB (BR, t);
743 AR = (AR + 1) & DMASK; /* incr src */
744 BR = (BR + 1) & DMASK; /* incr dst */
745 wc = (wc - 1) & DMASK; /* decr cnt */
746 if (intrq && wc) { /* intr, more to do? */
747 PC = err_PC; /* back up PC */
748 break;
749 }
750 }
751 WriteW (op[1].word, wc); /* clean up inline */
752 break;
753
754 case 026: /* CBT 105766 (OP_KV) */
755 wc = ReadW (op[1].word); /* get continuation count */
756 if (wc == 0) wc = op[0].word; /* none? get initiation count */
757 while (wc != 0) { /* while count */
758 WriteW (op[1].word, wc); /* for MP abort */
759 v1 = ReadB (AR); /* get src1 */
760 v2 = ReadB (BR); /* get src2 */
761 if (v1 != v2) { /* compare */
762 PC = (PC + 1 + (v1 > v2)) & VAMASK;
763 BR = (BR + wc) & DMASK; /* update BR */
764 wc = 0; /* clr interim */
765 break;
766 }
767 AR = (AR + 1) & DMASK; /* incr src1 */
768 BR = (BR + 1) & DMASK; /* incr src2 */
769 wc = (wc - 1) & DMASK; /* decr cnt */
770 if (intrq && wc) { /* intr, more to do? */
771 PC = err_PC; /* back up PC */
772 break;
773 }
774 }
775 WriteW (op[1].word, wc); /* clean up inline */
776 break;
777
778 case 027: /* SFB 105767 (OP_N) */
779 v1 = AR & 0377; /* test byte */
780 v2 = (AR >> 8) & 0377; /* term byte */
781 for (;;) { /* scan */
782 t = ReadB (BR); /* read byte */
783 if (t == v1) break; /* test match? */
784 BR = (BR + 1) & DMASK;
785 if (t == v2) { /* term match? */
786 PC = (PC + 1) & VAMASK;
787 break;
788 }
789 if (intrq) { /* int pending? */
790 PC = err_PC; /* back up PC */
791 break;
792 }
793 }
794 break;
795
796 case 030: /* ISY 105770 (OP_N) */
797 YR = (YR + 1) & DMASK; /* incr YR */
798 if (YR == 0) PC = (PC + 1) & VAMASK; /* skip if zero */
799 break;
800
801 case 031: /* DSY 105771 (OP_N) */
802 YR = (YR - 1) & DMASK; /* decr YR */
803 if (YR == 0) PC = (PC + 1) & VAMASK; /* skip if zero */
804 break;
805
806 case 032: /* JPY 105772 (OP_C) */
807 op[0].word = (op[0].word + YR) & VAMASK; /* index, no indir */
808 mp_dms_jmp (op[0].word); /* validate jump addr */
809 PCQ_ENTRY;
810 PC = op[0].word; /* jump */
811 break;
812
813 case 033: /* SBS 105773 (OP_KA) */
814 WriteW (op[1].word, /* set bits */
815 ReadW (op[1].word) | op[0].word);
816 break;
817
818 case 034: /* CBS 105774 (OP_KA) */
819 WriteW (op[1].word, /* clear bits */
820 ReadW (op[1].word) & ~op[0].word);
821 break;
822
823 case 035: /* TBS 105775 (OP_KK) */
824 if ((op[1].word & op[0].word) != op[0].word) /* test bits */
825 PC = (PC + 1) & VAMASK;
826 break;
827
828 case 036: /* CMW 105776 (OP_KV) */
829 wc = ReadW (op[1].word); /* get continuation count */
830 if (wc == 0) wc = op[0].word; /* none? get initiation count */
831 while (wc != 0) { /* while count */
832 WriteW (op[1].word, wc); /* for abort */
833 v1 = ReadW (AR & VAMASK); /* first op */
834 v2 = ReadW (BR & VAMASK); /* second op */
835 sop1 = (int32) SEXT (v1); /* signed */
836 sop2 = (int32) SEXT (v2);
837 if (sop1 != sop2) { /* compare */
838 PC = (PC + 1 + (sop1 > sop2)) & VAMASK;
839 BR = (BR + wc) & DMASK; /* update BR */
840 wc = 0; /* clr interim */
841 break;
842 }
843 AR = (AR + 1) & DMASK; /* incr src1 */
844 BR = (BR + 1) & DMASK; /* incr src2 */
845 wc = (wc - 1) & DMASK; /* decr cnt */
846 if (intrq && wc) { /* intr, more to do? */
847 PC = err_PC; /* back up PC */
848 break;
849 }
850 }
851 WriteW (op[1].word, wc); /* clean up inline */
852 break;
853
854 case 037: /* MVW 105777 (OP_KV) */
855 wc = ReadW (op[1].word); /* get continuation count */
856 if (wc == 0) wc = op[0].word; /* none? get initiation count */
857 if ((wc & SIGN) &&
858 (UNIT_CPU_TYPE == UNIT_TYPE_2100))
859 break; /* < 0 is NOP for 2100 IOP */
860 while (wc != 0) { /* while count */
861 WriteW (op[1].word, wc); /* for abort */
862 t = ReadW (AR & VAMASK); /* move word */
863 WriteW (BR & VAMASK, t);
864 AR = (AR + 1) & DMASK; /* incr src */
865 BR = (BR + 1) & DMASK; /* incr dst */
866 wc = (wc - 1) & DMASK; /* decr cnt */
867 if (intrq && wc) { /* intr, more to do? */
868 PC = err_PC; /* back up PC */
869 break;
870 }
871 }
872 WriteW (op[1].word, wc); /* clean up inline */
873 break;
874
875 }
876
877 return reason;
878 }
879
880
881 /* 2000 I/O Processor
882
883 The IOP accelerates certain operations of the HP 2000 Time-Share BASIC system
884 I/O processor. Most 2000 systems were delivered with 2100 CPUs, although IOP
885 microcode was developed for the 1000-M and 1000-E. As the I/O processors
886 were specific to the 2000 system, general compatibility with other CPU
887 microcode options was unnecessary, and indeed no other options were possible
888 for the 2100.
889
890 Option implementation by CPU was as follows:
891
892 2114 2115 2116 2100 1000-M 1000-E 1000-F
893 ------ ------ ------ ------ ------ ------ ------
894 N/A N/A N/A 13206A 13207A 22702A N/A
895
896 The routines are mapped to instruction codes as follows:
897
898 Instr. 2100 1000-M/E Description
899 ------ ---------- ---------- --------------------------------------------
900 SAI 105060-117 101400-037 Store A indexed by B (+/- offset in IR<4:0>)
901 LAI 105020-057 105400-037 Load A indexed by B (+/- offset in IR<4:0>)
902 CRC 105150 105460 Generate CRC
903 REST 105340 105461 Restore registers from stack
904 READF 105220 105462 Read F register (stack pointer)
905 INS -- 105463 Initialize F register (stack pointer)
906 ENQ 105240 105464 Enqueue
907 PENQ 105257 105465 Priority enqueue
908 DEQ 105260 105466 Dequeue
909 TRSLT 105160 105467 Translate character
910 ILIST 105000 105470 Indirect address list (similar to $SETP)
911 PRFEI 105222 105471 Power fail exit with I/O
912 PRFEX 105223 105472 Power fail exit
913 PRFIO 105221 105473 Power fail I/O
914 SAVE 105362 105474 Save registers to stack
915
916 MBYTE 105120 105765 Move bytes (MBT)
917 MWORD 105200 105777 Move words (MVW)
918 SBYTE 105300 105764 Store byte (SBT)
919 LBYTE 105320 105763 Load byte (LBT)
920
921 The INS instruction was not required in the 2100 implementation because the
922 stack pointer was actually the memory protect fence register and so could be
923 loaded directly with an OTA/B 05. Also, the 1000 implementation did not
924 offer the MBYTE, MWORD, SBYTE, and LBYTE instructions because the equivalent
925 instructions from the standard Extended Instruction Group were used instead.
926 Note that the 2100 MBYTE and MWORD instructions operate slightly differently
927 from the 1000 MBT and MVW instructions. Specifically, the move count is
928 signed on the 2100 and unsigned on the 1000. A negative count on the 2100
929 results in a NOP.
930
931 The simulator remaps the 2100 instructions to the 1000 codes. The four EIG equivalents
932 are dispatched to the EIG simulator. The rest are handled here. Note that the MBT and
933 MVW instructions operate slightly differently on the 2100; they are
934
935 Additional reference:
936 - HP 2000 Computer System Sources and Listings Documentation
937 (22687-90020, undated), section 3, pages 2-74 through 2-91.
938 */
939
940 static const OP_PAT op_iop[16] = {
941 OP_V, OP_N, OP_N, OP_N, /* CRC RESTR READF INS */
942 OP_N, OP_N, OP_N, OP_V, /* ENQ PENQ DEQ TRSLT */
943 OP_AC, OP_CVA, OP_A, OP_CV, /* ILIST PRFEI PRFEX PRFIO */
944 OP_N, OP_N, OP_N, OP_N /* SAVE --- --- --- */
945 };
946
947 t_stat cpu_iop (uint32 IR, uint32 intrq)
948 {
949 t_stat reason = SCPE_OK;
950 OPS op;
951 uint32 entry;
952 uint32 hp, tp, i, t, wc, MA;
953
954 if ((cpu_unit.flags & UNIT_IOP) == 0) /* IOP option installed? */
955 return stop_inst;
956
957 if (UNIT_CPU_TYPE == UNIT_TYPE_2100) { /* 2100 IOP? */
958 if ((IR >= 0105020) && (IR <= 0105057)) /* remap LAI */
959 IR = 0105400 | (IR - 0105020);
960 else if ((IR >= 0105060) && (IR <= 0105117)) /* remap SAI */
961 IR = 0101400 | (IR - 0105060);
962 else {
963 switch (IR) { /* remap others */
964 case 0105000: IR = 0105470; break; /* ILIST */
965 case 0105120: return cpu_eig (0105765, intrq); /* MBYTE (maps to MBT) */
966 case 0105150: IR = 0105460; break; /* CRC */
967 case 0105160: IR = 0105467; break; /* TRSLT */
968 case 0105200: return cpu_eig (0105777, intrq); /* MWORD (maps to MVW) */
969 case 0105220: IR = 0105462; break; /* READF */
970 case 0105221: IR = 0105473; break; /* PRFIO */
971 case 0105222: IR = 0105471; break; /* PRFEI */
972 case 0105223: IR = 0105472; break; /* PRFEX */
973 case 0105240: IR = 0105464; break; /* ENQ */
974 case 0105257: IR = 0105465; break; /* PENQ */
975 case 0105260: IR = 0105466; break; /* DEQ */
976 case 0105300: return cpu_eig (0105764, intrq); /* SBYTE (maps to SBT) */
977 case 0105320: return cpu_eig (0105763, intrq); /* LBYTE (maps to LBT) */
978 case 0105340: IR = 0105461; break; /* REST */
979 case 0105362: IR = 0105474; break; /* SAVE */
980
981 default: /* all others invalid */
982 return stop_inst;
983 }
984 }
985 }
986
987 entry = IR & 077; /* mask to entry point */
988
989 if (entry <= 037) { /* LAI/SAI 10x400-437 */
990 MA = ((entry - 020) + BR) & VAMASK; /* +/- offset */
991 if (IR & I_AB) AR = ReadW (MA); /* AB = 1 -> LAI */
992 else WriteW (MA, AR); /* AB = 0 -> SAI */
993 return reason;
994 }
995 else if (entry <= 057) /* IR = 10x440-457? */
996 return stop_inst; /* not part of IOP */
997
998 entry = entry - 060; /* offset 10x460-477 */
999
1000 if (op_iop[entry] != OP_N)
1001 if (reason = cpu_ops (op_iop[entry], op, intrq)) /* get instruction operands */
1002 return reason;
1003
1004 switch (entry) { /* decode IR<5:0> */
1005
1006 case 000: /* CRC 105460 (OP_V) */
1007 t = ReadW (op[0].word) ^ (AR & 0377); /* xor prev CRC and char */
1008 for (i = 0; i < 8; i++) { /* apply polynomial */
1009 t = (t >> 1) | ((t & 1) << 15); /* rotate right */
1010 if (t & SIGN) t = t ^ 020001; /* old t<0>? xor */
1011 }
1012 WriteW (op[0].word, t); /* rewrite CRC */
1013 break;
1014
1015 case 001: /* RESTR 105461 (OP_N) */
1016 iop_sp = (iop_sp - 1) & VAMASK; /* decr stack ptr */
1017 t = ReadW (iop_sp); /* get E and O */
1018 O = ((t >> 1) ^ 1) & 1; /* restore O */
1019 E = t & 1; /* restore E */
1020 iop_sp = (iop_sp - 1) & VAMASK; /* decr sp */
1021 BR = ReadW (iop_sp); /* restore B */
1022 iop_sp = (iop_sp - 1) & VAMASK; /* decr sp */
1023 AR = ReadW (iop_sp); /* restore A */
1024 if (UNIT_CPU_MODEL == UNIT_2100)
1025 mp_fence = iop_sp; /* 2100 keeps sp in MP FR */
1026 break;
1027
1028 case 002: /* READF 105462 (OP_N) */
1029 AR = iop_sp; /* copy stk ptr */
1030 break;
1031
1032 case 003: /* INS 105463 (OP_N) */
1033 iop_sp = AR; /* init stk ptr */
1034 break;
1035
1036 case 004: /* ENQ 105464 (OP_N) */
1037 hp = ReadW (AR & VAMASK); /* addr of head */
1038 tp = ReadW ((AR + 1) & VAMASK); /* addr of tail */
1039 WriteW ((BR - 1) & VAMASK, 0); /* entry link */
1040 WriteW ((tp - 1) & VAMASK, BR); /* tail link */
1041 WriteW ((AR + 1) & VAMASK, BR); /* queue tail */
1042 if (hp != 0) PC = (PC + 1) & VAMASK; /* q not empty? skip */
1043 break;
1044
1045 case 005: /* PENQ 105465 (OP_N) */
1046 hp = ReadW (AR & VAMASK); /* addr of head */
1047 WriteW ((BR - 1) & VAMASK, hp); /* becomes entry link */
1048 WriteW (AR & VAMASK, BR); /* queue head */
1049 if (hp == 0) /* q empty? */
1050 WriteW ((AR + 1) & VAMASK, BR); /* queue tail */
1051 else PC = (PC + 1) & VAMASK; /* skip */
1052 break;
1053
1054 case 006: /* DEQ 105466 (OP_N) */
1055 BR = ReadW (AR & VAMASK); /* addr of head */
1056 if (BR) { /* queue not empty? */
1057 hp = ReadW ((BR - 1) & VAMASK); /* read hd entry link */
1058 WriteW (AR & VAMASK, hp); /* becomes queue head */
1059 if (hp == 0) /* q now empty? */
1060 WriteW ((AR + 1) & VAMASK, (AR + 1) & DMASK);
1061 PC = (PC + 1) & VAMASK; /* skip */
1062 }
1063 break;
1064
1065 case 007: /* TRSLT 105467 (OP_V) */
1066 wc = ReadW (op[0].word); /* get count */
1067 if (wc & SIGN) break; /* cnt < 0? */
1068 while (wc != 0) { /* loop */
1069 MA = (AR + AR + ReadB (BR)) & VAMASK;
1070 t = ReadB (MA); /* xlate */
1071 WriteB (BR, t); /* store char */
1072 BR = (BR + 1) & DMASK; /* incr ptr */
1073 wc = (wc - 1) & DMASK; /* decr cnt */
1074 if (wc && intrq) { /* more and intr? */
1075 WriteW (op[0].word, wc); /* save count */
1076 PC = err_PC; /* stop for now */
1077 break;
1078 }
1079 }
1080 break;
1081
1082 case 010: /* ILIST 105470 (OP_AC) */
1083 do { /* for count */
1084 WriteW (op[0].word, AR); /* write AR to mem */
1085 AR = (AR + 1) & DMASK; /* incr AR */
1086 op[0].word = (op[0].word + 1) & VAMASK; /* incr MA */
1087 op[1].word = (op[1].word - 1) & DMASK; /* decr count */
1088 }
1089 while (op[1].word != 0);
1090 break;
1091
1092 case 011: /* PRFEI 105471 (OP_CVA) */
1093 WriteW (op[1].word, 1); /* set flag */
1094 reason = iogrp (op[0].word, 0); /* execute I/O instr */
1095 op[0].word = op[2].word; /* set rtn and fall through */
1096
1097 case 012: /* PRFEX 105472 (OP_A) */
1098 PCQ_ENTRY;
1099 PC = ReadW (op[0].word) & VAMASK; /* jump indirect */
1100 WriteW (op[0].word, 0); /* clear exit */
1101 break;
1102
1103 case 013: /* PRFIO 105473 (OP_CV) */
1104 WriteW (op[1].word, 1); /* set flag */
1105 reason = iogrp (op[0].word, 0); /* execute instr */
1106 break;
1107
1108 case 014: /* SAVE 105474 (OP_N) */
1109 WriteW (iop_sp, AR); /* save A */
1110 iop_sp = (iop_sp + 1) & VAMASK; /* incr stack ptr */
1111 WriteW (iop_sp, BR); /* save B */
1112 iop_sp = (iop_sp + 1) & VAMASK; /* incr stack ptr */
1113 t = ((O ^ 1) << 1) | E; /* merge E and O */
1114 WriteW (iop_sp, t); /* save E and O */
1115 iop_sp = (iop_sp + 1) & VAMASK; /* incr stack ptr */
1116 if (UNIT_CPU_TYPE == UNIT_TYPE_2100)
1117 mp_fence = iop_sp; /* 2100 keeps sp in MP FR */
1118 break;
1119
1120 default: /* instruction undefined */
1121 return stop_inst;
1122 }
1123
1124 return reason;
1125 }
Magically enhanced SIMH