I7094/i7094_clk.c

   1 /* i7094_clk.c: IBM 7094 clock
   2
   3    Copyright (c) 2003-2006, Robert M. Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    clk          RPQ F89349 interval timer
  27                 Chronolog calendar clock
  28 */
  29
  30 #include "i7094_defs.h"
  31 #include <time.h>
  32
  33 uint32 chtr_clk = 0;
  34 extern t_uint64 *M;
  35
  36 t_stat clk_svc (UNIT *uptr);
  37 t_stat clk_reset (DEVICE *dptr);
  38 uint8 bcd_2d (uint32 n, uint8 *b2);
  39
  40 /* CLK data structures
  41
  42    clk_dev      CLK device descriptor
  43    clk_unit     CLK unit
  44    clk_reg      CLK register list
  45 */
  46
  47 UNIT clk_unit = { UDATA (&clk_svc, 0, 0), 16000 };
  48
  49 REG clk_reg[] = {
  50     { FLDATA (TRAP, chtr_clk, 0) },
  51     { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
  52     { NULL }
  53     };
  54
  55 DEVICE clk_dev = {
  56     "CLK", &clk_unit, clk_reg, NULL,
  57     1, 0, 0, 0, 0, 0,
  58     NULL, NULL, &clk_reset,
  59     NULL, NULL, NULL,
  60     NULL, DEV_DISABLE+DEV_DIS
  61     };
  62
  63 /* Clock unit service */
  64
  65 t_stat clk_svc (UNIT *uptr)
  66 {
  67 t_uint64 ctr;
  68
  69 if ((clk_dev.flags & DEV_DIS) == 0) {                   /* clock enabled? */
  70     ctr = ReadP (CLK_CTR);
  71     ctr = (ctr + 1) & DMASK;                            /* increment */
  72     WriteP (CLK_CTR, ctr);
  73     if ((ctr & MMASK) == 0) chtr_clk = 1;               /* overflow? req trap */
  74     sim_activate (uptr, sim_rtcn_calb (CLK_TPS, TMR_CLK)); /* reactivate unit */
  75     }
  76 return SCPE_OK;
  77 }
  78
  79 /* Chronolog clock */
  80
  81 uint32 chrono_rd (uint8 *buf, uint32 bufsiz)
  82 {
  83 time_t curtim;
  84 t_uint64 ctr;
  85 struct tm *tptr;
  86
  87 if (bufsiz < 12) return 0;
  88 curtim = time (NULL);                                   /* get time */
  89 tptr = localtime (&curtim);                             /* decompose */
  90 if (tptr == NULL) return 0;                             /* error? */
  91
  92 buf[0] = bcd_2d (tptr->tm_mon + 1, buf + 1);
  93 buf[2] = bcd_2d (tptr->tm_mday, buf + 3);
  94 buf[4] = bcd_2d (tptr->tm_hour, buf + 5);
  95 buf[6] = bcd_2d (tptr->tm_min, buf + 7);
  96 buf[8] = bcd_2d (tptr->tm_sec, buf + 9);
  97 ctr = ReadP (CLK_CTR);
  98 buf[10] = bcd_2d ((uint32) (ctr % 60), buf + 11);
  99 return 12;
 100 }
 101
 102 /* Convert number (0-99) to BCD */
 103
 104 uint8 bcd_2d (uint32 n, uint8 *b2)
 105 {
 106 uint8 d1, d2;
 107
 108 d1 = n / 10;
 109 d2 = n % 10;
 110 if (d1 == 0) d1 = BCD_ZERO;
 111 if (d2 == 0) d2 = BCD_ZERO;
 112 if (b2 != NULL) *b2 = d2;
 113 return d1;
 114 }
 115
 116 /* Reset routine */
 117
 118 t_stat clk_reset (DEVICE *dptr)
 119 {
 120 chtr_clk = 0;
 121 if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit);
 122 else sim_activate (&clk_unit, sim_rtcn_init (clk_unit.wait, TMR_CLK));
 123 return SCPE_OK;
 124 }