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First Commit of my working state
[simh.git] / Interdata / id_idc.c
1 /* id_idc.c: Interdata MSM/IDC disk controller simulator
2
3 Copyright (c) 2001-2006, Robert M. Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 idc MSM/IDC disk controller
27
28 03-Apr-06 RMS Fixed WD/WH handling (found by Davis Johnson)
29 30-Mar-06 RMS Fixed bug, nop command should be ignored (found by Davis Johnson)
30 25-Apr-03 RMS Revised for extended file support
31 16-Feb-03 RMS Fixed read to test transfer ok before selch operation
32
33 Note: define flag ID_IDC to enable the extra functions of the intelligent
34 disk controller
35 */
36
37 #include "id_defs.h"
38
39 #define IDC_NUMBY 256 /* bytes/sector */
40 #define IDC_NUMSC 64 /* sectors/track */
41
42 #define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
43 #define UNIT_V_DTYPE (UNIT_V_UF + 1) /* disk type */
44 #define UNIT_M_DTYPE 0x7
45 #define UNIT_V_AUTO (UNIT_V_UF + 4) /* autosize */
46 #define UNIT_WLK (1 << UNIT_V_WLK)
47 #define UNIT_DTYPE (UNIT_M_DTYPE << UNIT_V_DTYPE)
48 #define UNIT_AUTO (1 << UNIT_V_AUTO)
49 #define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE)
50
51 #define CYL u3 /* current cylinder */
52 #define HD u4 /* current head */
53 #define STD buf /* drive status */
54 #define FNC wait /* function */
55 #define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
56
57 #define IDC_DRVMASK ((1 << ID_NUMDR) - 1) /* drive bit mask */
58 #define IDC_DIRMASK (IDC_DRVMASK << (i_IDC + 1)) /* drive irq mask */
59
60 /* Controller status */
61
62 #define STC_WRP 0x80 /* write protected */
63 #define STC_ACF 0x40 /* addr cmp fail */
64 #define STC_DEF 0x20 /* def track NI */
65 #define STC_CYO 0x10 /* cylinder ovflo */
66 #define STC_IDL 0x02 /* ctrl idle */
67 #define STC_DTE 0x01 /* xfer error */
68 #define SETC_EX (STC_WRP|STC_ACF|STC_DEF|STC_CYO)
69 #define STC_MASK (STC_WRP|STC_ACF|STC_DEF|STC_CYO|STA_BSY|STC_IDL|STC_DTE)
70
71 /* Controller command */
72
73 #define CMC_MASK 0x3F
74 #define CMC_CLR 0x08 /* reset */
75 #define CMC_RD 0x01 /* read */
76 #define CMC_WR 0x02 /* write */
77 #define CMC_RCHK 0x03 /* read check */
78 #define CMC_FCHK 0x04 /* format check NI */
79 #define CMC_RFMT 0x05 /* read fmt NI */
80 #define CMC_WFMT 0x06 /* write fmt NI */
81 #define CMC_WFTK 0x07 /* write fmt track NI */
82
83 /* IDC only functions */
84
85 #define CMC_RRAM 0x10 /* read RAM */
86 #define CMC_WRAM 0x11 /* write RAM */
87 #define CMC_EXP0 0x12 /* read page 0 NI */
88 #define CMC_RUNC 0x21 /* read uncorr */
89 #define CMC_STST 0x30 /* self test */
90 #define CMC_WLNG 0x32 /* write long NI */
91 #define CMC_LAMP 0x37 /* lamp test */
92
93 #define CMC_DRV 0x100 /* drive func */
94 #define CMC_DRV1 0x200 /* drive func, part 2 */
95
96 /* Drive status, ^ = dynamic, * = in unit status */
97
98 #define STD_WRP 0x80 /* ^write prot */
99 /* 0x40 /* unused */
100 #define STD_ACH 0x20 /* alt chan busy NI */
101 #define STD_UNS 0x10 /* *unsafe */
102 #define STD_NRDY 0x08 /* ^not ready */
103 #define STD_SKI 0x02 /* *seek incomplete */
104 #define STD_OFFL 0x01 /* ^offline */
105 #define STD_UST (STD_UNS | STD_SKI) /* set from unit */
106 #define SETD_EX (STD_WRP | STD_UNS) /* set examine */
107
108 /* Drive command */
109
110 #define CMDF_SHD 0x20 /* set head */
111 #define CMDF_SCY 0x10 /* set cylinder */
112 #define CMD_SK 0x02 /* seek */
113 #define CMD_RST 0x01 /* restore */
114
115 #define CMDX_MASK 0x30 /* ext cmd bits */
116 #define CMDX_RLS 0x80 /* release */
117 #define CMDX_CLF 0x40 /* clear fault */
118 #define CMDX_SVP 0x08 /* servo + */
119 #define CMDX_SVM 0x04 /* servo - */
120 #define CMDX_DSP 0x02 /* strobe + */
121 #define CMDX_DSM 0x01 /* strobe - */
122
123 /* Geometry masks */
124
125 #define CY_MASK 0xFFF /* cylinder */
126 #define HD_MASK 0x1F /* head mask */
127 #define SC_MASK 0x3F /* sector mask */
128 #define HCYL_V_HD 10 /* head/cyl word */
129 #define HCYL_V_CYL 0
130
131 #define GET_SA(cy,sf,sc,t) \
132 (((((cy)*drv_tab[t].surf)+(sf))*IDC_NUMSC)+(sc))
133
134 /* The MSM (IDC) controller supports (two) six different disk drive types:
135
136 type #sectors/ #surfaces/ #cylinders/
137 surface cylinder drive
138
139 MCCDD16 64 1 823 IDC
140 MCCDD48 64 3 823 IDC
141 MCCDD80 64 5 823 IDC
142 MSM80 64 5 823 MSM
143 MSM300 64 19 823 MSM
144 MSM330F 64 16 1024 IDC
145
146 In theory, each drive can be a different type. The size field in
147 each unit selects the drive capacity for each drive and thus the
148 drive type. DISKS MUST BE DECLARED IN ASCENDING SIZE AND MUST HAVE
149 THE SAME SECTORS/TRACK.
150 */
151
152 #define TYPE_MCCDD16 0
153 #define SURF_MCCDD16 1
154 #define CYL_MCCDD16 823
155 #define SIZE_MCCDD16 (IDC_NUMSC * SURF_MCCDD16 * CYL_MCCDD16 * IDC_NUMBY)
156
157 #define TYPE_MCCDD48 1
158 #define SURF_MCCDD48 3
159 #define CYL_MCCDD48 823
160 #define SIZE_MCCDD48 (IDC_NUMSC * SURF_MCCDD48 * CYL_MCCDD48 * IDC_NUMBY)
161
162 #define TYPE_MCCDD80 2
163 #define SURF_MCCDD80 5
164 #define CYL_MCCDD80 823
165 #define SIZE_MCCDD80 (IDC_NUMSC * SURF_MCCDD80 * CYL_MCCDD80 * IDC_NUMBY)
166
167 #define TYPE_MSM80 3
168 #define SURF_MSM80 5
169 #define CYL_MSM80 823
170 #define SIZE_MSM80 (IDC_NUMSC * SURF_MSM80 * CYL_MSM80 * IDC_NUMBY)
171
172 #define TYPE_MSM300 4
173 #define SURF_MSM300 19
174 #define CYL_MSM300 823
175 #define SIZE_MSM300 (IDC_NUMSC * SURF_MSM300 * CYL_MSM300 * IDC_NUMBY)
176
177 #define TYPE_MSM330F 5
178 #define SURF_MSM330F 16
179 #define CYL_MSM330F 1024
180 #define SIZE_MSM330F (IDC_NUMSC * SURF_MSM330F * CYL_MSM330F * IDC_NUMBY)
181
182
183 struct drvtyp {
184 uint32 surf; /* surfaces */
185 uint32 cyl; /* cylinders */
186 uint32 size; /* #blocks */
187 uint32 msmf; /* MSM drive */
188 };
189
190 static struct drvtyp drv_tab[] = {
191 { SURF_MCCDD16, CYL_MCCDD16, SIZE_MCCDD16, 0 },
192 { SURF_MCCDD48, CYL_MCCDD48, SIZE_MCCDD48, 0 },
193 { SURF_MCCDD80, CYL_MCCDD80, SIZE_MCCDD80, 0 },
194 { SURF_MSM80, CYL_MSM80, SIZE_MSM80, 1 },
195 { SURF_MSM300, CYL_MSM300, SIZE_MSM300, 1 },
196 { SURF_MSM330F, CYL_MSM330F, SIZE_MSM330F, 0 },
197 { 0 }
198 };
199
200 extern uint32 int_req[INTSZ], int_enb[INTSZ];
201
202 uint8 idcxb[IDC_NUMBY * 3]; /* xfer buffer */
203 uint32 idc_bptr = 0; /* buffer ptr */
204 uint32 idc_wdptr = 0; /* ctrl write data ptr */
205 uint32 idc_db = 0; /* ctrl buffer */
206 uint32 idc_sta = 0; /* ctrl status */
207 uint32 idc_sec = 0; /* sector */
208 uint32 idc_hcyl = 0; /* head/cyl */
209 uint32 idc_svun = 0; /* most recent unit */
210 uint32 idc_1st = 0; /* first byte */
211 uint32 idc_arm = 0; /* ctrl armed */
212 uint32 idd_db = 0; /* drive buffer */
213 uint32 idd_wdptr = 0; /* drive write data ptr */
214 uint32 idd_arm[ID_NUMDR] = { 0 }; /* drives armed */
215 uint16 idd_dcy[ID_NUMDR] = { 0 }; /* desired cyl */
216 uint32 idd_sirq = 0; /* drive saved irq */
217 int32 idc_stime = 100; /* seek latency */
218 int32 idc_rtime = 100; /* rotate latency */
219 int32 idc_ctime = 5; /* command latency */
220 uint8 idc_tplte[] = { 0, 1, 2, 3, 4, TPL_END }; /* ctrl + drive */
221
222 DEVICE idc_dev;
223 uint32 id (uint32 dev, uint32 op, uint32 dat);
224 t_stat idc_svc (UNIT *uptr);
225 t_stat idc_reset (DEVICE *dptr);
226 t_stat idc_attach (UNIT *uptr, char *cptr);
227 t_stat idc_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
228 void idc_wd_byte (uint32 dat);
229 t_stat idc_rds (UNIT *uptr);
230 t_stat idc_wds (UNIT *uptr);
231 t_bool idc_dter (UNIT *uptr, uint32 first);
232 void idc_done (uint32 flg);
233
234 extern t_stat id_dboot (int32 u, DEVICE *dptr);
235
236 /* DP data structures
237
238 idc_dev DP device descriptor
239 idc_unit DP unit list
240 idc_reg DP register list
241 idc_mod DP modifier list
242 */
243
244 DIB idc_dib = { d_IDC, 0, v_IDC, idc_tplte, &id, NULL };
245
246 UNIT idc_unit[] = {
247 { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
248 UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) },
249 { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
250 UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) },
251 { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
252 UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) },
253 { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
254 UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) }
255 };
256
257 REG idc_reg[] = {
258 { HRDATA (STA, idc_sta, 8) },
259 { HRDATA (BUF, idc_db, 8) },
260 { HRDATA (SEC, idc_sec, 8) },
261 { HRDATA (HCYL, idc_hcyl, 16) },
262 { HRDATA (BUF, idd_db, 8) },
263 { HRDATA (SVUN, idc_svun, 2), REG_HIDDEN },
264 { BRDATA (DBUF, idcxb, 16, 8, IDC_NUMBY * 3) },
265 { HRDATA (DBPTR, idc_bptr, 10), REG_RO },
266 { FLDATA (FIRST, idc_1st, 0) },
267 { HRDATA (CWDPTR, idc_wdptr, 2) },
268 { HRDATA (DWDPTR, idc_wdptr, 1) },
269 { GRDATA (IREQ, int_req[l_IDC], 16, ID_NUMDR + 1, i_IDC) },
270 { GRDATA (IENB, int_enb[l_IDC], 16, ID_NUMDR + 1, i_IDC) },
271 { GRDATA (SIREQ, idd_sirq, 16, ID_NUMDR, i_IDC + 1), REG_RO },
272 { FLDATA (ICARM, idc_arm, 0) },
273 { BRDATA (IDARM, idd_arm, 16, 1, ID_NUMDR) },
274 { DRDATA (RTIME, idc_rtime, 24), PV_LEFT | REG_NZ },
275 { DRDATA (STIME, idc_stime, 24), PV_LEFT | REG_NZ },
276 { DRDATA (CTIME, idc_ctime, 24), PV_LEFT | REG_NZ },
277 { BRDATA (CYL, idd_dcy, 16, 16, ID_NUMDR) },
278 { URDATA (UCYL, idc_unit[0].CYL, 16, 12, 0,
279 ID_NUMDR, REG_RO) },
280 { URDATA (UHD, idc_unit[0].HD, 16, 5, 0,
281 ID_NUMDR, REG_RO) },
282 { URDATA (UFNC, idc_unit[0].FNC, 16, 10, 0,
283 ID_NUMDR, REG_HRO) },
284 { URDATA (UST, idc_unit[0].STD, 16, 8, 0,
285 ID_NUMDR, REG_RO) },
286 { URDATA (CAPAC, idc_unit[0].capac, 10, T_ADDR_W, 0,
287 ID_NUMDR, PV_LEFT | REG_HRO) },
288 { HRDATA (DEVNO, idc_dib.dno, 8), REG_HRO },
289 { HRDATA (SELCH, idc_dib.sch, 2), REG_HRO },
290 { BRDATA (TPLTE, idc_tplte, 16, 8, ID_NUMDR + 1), REG_HRO },
291 { NULL }
292 };
293
294 MTAB idc_mod[] = {
295 { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
296 { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
297 { (UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD16 << UNIT_V_DTYPE) + UNIT_ATT,
298 "MCCDD16", NULL, NULL },
299 { (UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD48 << UNIT_V_DTYPE) + UNIT_ATT,
300 "MCCDD48", NULL, NULL },
301 { (UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD80 << UNIT_V_DTYPE) + UNIT_ATT,
302 "MCCDD80", NULL, NULL },
303 { (UNIT_DTYPE+UNIT_ATT), (TYPE_MSM330F << UNIT_V_DTYPE) + UNIT_ATT,
304 "MSM330F", NULL, NULL },
305 { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD16 << UNIT_V_DTYPE),
306 "MCCDD16", NULL, NULL },
307 { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD48 << UNIT_V_DTYPE),
308 "MCCDD48", NULL, NULL },
309 { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD80 << UNIT_V_DTYPE),
310 "MCCDD80", NULL, NULL },
311 { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MSM330F << UNIT_V_DTYPE),
312 "MSM330F", NULL, NULL },
313 { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MCCDD16 << UNIT_V_DTYPE),
314 NULL, "MCCDD16", &idc_set_size },
315 { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MCCDD48 << UNIT_V_DTYPE),
316 NULL, "MCCDD48", &idc_set_size },
317 { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MCCDD80 << UNIT_V_DTYPE),
318 NULL, "MCCDD80", &idc_set_size },
319 { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MSM330F << UNIT_V_DTYPE),
320 NULL, "MSM330F", &idc_set_size },
321 { (UNIT_DTYPE+UNIT_ATT), (TYPE_MSM80 << UNIT_V_DTYPE) + UNIT_ATT,
322 "MSM80", NULL, NULL },
323 { (UNIT_DTYPE+UNIT_ATT), (TYPE_MSM300 << UNIT_V_DTYPE) + UNIT_ATT,
324 "MSM300", NULL, NULL },
325 { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MSM80 << UNIT_V_DTYPE),
326 "MSM80", NULL, NULL },
327 { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MSM300 << UNIT_V_DTYPE),
328 "MSM300", NULL, NULL },
329 { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MSM80 << UNIT_V_DTYPE),
330 NULL, "MSM80", &idc_set_size },
331 { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MSM300 << UNIT_V_DTYPE),
332 NULL, "MSM300", &idc_set_size },
333 { (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
334 { UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
335 { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
336 &set_dev, &show_dev, NULL },
337 { MTAB_XTD|MTAB_VDV, 0, "SELCH", "SELCH",
338 &set_sch, &show_sch, NULL },
339 { 0 }
340 };
341
342 DEVICE idc_dev = {
343 "DM", idc_unit, idc_reg, idc_mod,
344 ID_NUMDR, 16, 29, 1, 16, 8,
345 NULL, NULL, &idc_reset,
346 &id_dboot, &idc_attach, NULL,
347 &idc_dib, DEV_DISABLE
348 };
349
350 /* Controller: IO routine */
351
352 uint32 idc (uint32 dev, uint32 op, uint32 dat)
353 {
354 uint32 f, t;
355 UNIT *uptr;
356
357 switch (op) { /* case IO op */
358
359 case IO_ADR: /* select */
360 sch_adr (idc_dib.sch, dev); /* inform sel ch */
361 return HW; /* halfwords */
362
363 case IO_RD: /* read data */
364 case IO_RH: /* read halfword */
365 return 0; /* return data */
366
367 case IO_WD: /* write data */
368 idc_wd_byte (dat); /* one byte only */
369 break;
370
371 case IO_WH: /* write halfword */
372 idc_wd_byte (dat >> 8); /* high byte */
373 idc_wd_byte (dat); /* low byte */
374 break;
375
376 case IO_SS: /* status */
377 t = idc_sta & STC_MASK; /* get status */
378 if (t & SETC_EX) t = t | STA_EX; /* test for EX */
379 return t;
380
381 case IO_OC: /* command */
382 idc_arm = int_chg (v_IDC, dat, idc_arm); /* upd int ctrl */
383 idc_wdptr = 0; /* init ptr */
384 f = dat & CMC_MASK; /* get cmd */
385 uptr = idc_dev.units + idc_svun; /* get unit */
386 if (f & CMC_CLR) { /* clear? */
387 idc_reset (&idc_dev); /* reset world */
388 break;
389 }
390 if ((f == 0) || /* if nop, */
391 (f == CMC_EXP0) || /* expg, */
392 !(idc_sta & STC_IDL) || /* !idle, */
393 sim_is_active (uptr)) break; /* unit busy, ignore */
394 idc_sta = STA_BSY; /* bsy=1,idl,err=0 */
395 idc_1st = 1; /* xfr not started */
396 idc_bptr = 0; /* buffer empty */
397 uptr->FNC = f; /* save cmd */
398 sim_activate (uptr, idc_rtime); /* schedule */
399 idd_sirq = int_req[l_IDC] & IDC_DIRMASK; /* save drv ints */
400 int_req[l_IDC] = int_req[l_IDC] & ~IDC_DIRMASK; /* clr drv ints */
401 break;
402 }
403
404 return 0;
405 }
406
407 /* Process WD/WH data */
408
409 void idc_wd_byte (uint32 dat)
410 {
411 dat = dat & 0xFF;
412 switch (idc_wdptr) {
413
414 case 0: /* byte 0 = sector */
415 idc_sec = dat;
416 idc_wdptr++;
417 break;
418
419 case 1: /* byte 1 = high hd/cyl */
420 idc_hcyl = (idc_hcyl & 0xFF) | (dat << 8);
421 idc_wdptr++;
422 break;
423
424 case 2: /* byte 2 = low hd/cyl */
425 idc_hcyl = (idc_hcyl & 0xFF00) | dat;
426 idc_wdptr = 0;
427 break;
428 }
429
430 return;
431 }
432
433 /* Drives: IO routine */
434
435 uint32 id (uint32 dev, uint32 op, uint32 dat)
436 {
437 uint32 t, u, f;
438 UNIT *uptr;
439
440 if (dev == idc_dib.dno) return idc (dev, op, dat); /* controller? */
441 u = (dev - idc_dib.dno - o_ID0) / o_ID0; /* get unit num */
442 uptr = idc_dev.units + u; /* get unit ptr */
443 switch (op) { /* case IO op */
444
445 case IO_ADR: /* select */
446 if (idc_sta & STC_IDL) idc_svun = u; /* idle? save unit */
447 return BY; /* byte only */
448
449 case IO_RD: /* read data */
450 case IO_RH:
451 return 0;
452
453 case IO_WD: /* write data */
454 if (idd_wdptr & 1) /* low byte? */
455 idd_db = (idd_db & 0xFF00) | dat;
456 else idd_db = (idd_db & 0xFF) | (dat << 8); /* no, high */
457 idd_wdptr = idd_wdptr ^ 1; /* other byte */
458 break;
459
460 case IO_SS: /* status */
461 if (uptr->flags & UNIT_ATT) t =
462 ((uptr->flags & UNIT_WPRT)? STD_WRP: 0) |
463 (sim_is_active (uptr)? STD_NRDY: 0) |
464 (uptr->STD & STD_UST);
465 else t = STD_NRDY | STD_OFFL; /* off = X'09' */
466 if (t & SETD_EX) t = t | STA_EX; /* test for ex */
467 return t;
468
469 case IO_OC: /* command */
470 idd_arm[u] = int_chg (v_IDC + u + 1, dat, idd_arm[u]);
471 idd_wdptr = 0; /* init ptr */
472 if (idd_arm[u] == 0) /* disarmed? */
473 idd_sirq &= ~(1 << (v_IDC + u + 1)); /* clr saved req */
474 f = dat & CMC_MASK; /* get cmd */
475 if ((f == 0) || /* if nop, */
476 (f == CMDX_MASK) || /* 0x30, */
477 !(idc_sta & STC_IDL) || /* !idle, */
478 sim_is_active (uptr)) break; /* unit busy, ignore */
479 uptr->FNC = f | CMC_DRV; /* save cmd */
480 idc_sta = idc_sta & ~STC_IDL; /* clr idle */
481 sim_activate (uptr, idc_ctime); /* schedule */
482 break;
483 }
484
485 return 0;
486 }
487
488 /* Unit service
489
490 If drive command, process; if an interrupt is needed (positioning
491 command), schedule second part
492
493 If data transfer command, process; must use selector channel
494 */
495
496 t_stat idc_svc (UNIT *uptr)
497 {
498 int32 diff;
499 uint32 f, u = uptr - idc_dev.units; /* get unit number */
500 uint32 dtype = GET_DTYPE (uptr->flags); /* get drive type */
501 uint32 t;
502 t_stat r;
503
504 if (uptr->FNC & CMC_DRV) { /* drive cmd? */
505 f = uptr->FNC & CMC_MASK; /* get cmd */
506 if (uptr->FNC & CMC_DRV1) { /* part 2? */
507 if (idd_arm[u]) { /* drv int armed? */
508 if (idc_sta & STC_IDL) /* ctrl idle? */
509 SET_INT (v_IDC + u + 1); /* req intr */
510 else idd_sirq |= (1 << (v_IDC + u + 1)); /* def intr */
511 }
512 if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK;
513 if (((f & CMDX_MASK) == 0) && /* seek? */
514 (f & (CMD_SK | CMD_RST))) {
515 if (idd_dcy[u] >= drv_tab[dtype].cyl) /* bad cylinder? */
516 uptr->STD = uptr->STD | STD_SKI; /* error */
517 uptr->CYL = idd_dcy[u]; /* put on cyl */
518 }
519 } /* end if p2 */
520 else { /* part 1 */
521 idc_sta = idc_sta | STC_IDL; /* set idle */
522 uptr->FNC = uptr->FNC | CMC_DRV1; /* set part 2 */
523 if (f >= CMDX_MASK) { /* extended? */
524 if (f & CMDX_CLF) /* clr fault? */
525 uptr->STD = uptr->STD & ~STD_UNS; /* clr unsafe */
526 if (f & (CMDX_RLS | CMDX_SVP | CMDX_SVM)) /* intr expected? */
527 sim_activate (uptr, idc_ctime);
528 }
529 else if (f >= CMDF_SCY) { /* tag? */
530 if (f & CMDF_SHD) uptr->HD = idd_db & HD_MASK;
531 else if (f & CMDF_SCY) {
532 if (idd_db >= drv_tab[dtype].cyl) /* bad cylinder? */
533 uptr->STD = uptr->STD | STD_SKI; /* set seek inc */
534 idd_dcy[u] = idd_db & CY_MASK;
535 }
536 }
537 else if (f & (CMD_SK | CMD_RST)) { /* seek? */
538 if (f == CMD_RST) idd_dcy[u] = 0; /* restore? */
539 if (idd_dcy[u] >= drv_tab[dtype].cyl) { /* bad cylinder? */
540 uptr->STD = uptr->STD | STD_SKI; /* set seek inc */
541 idd_dcy[u] = uptr->CYL; /* no motion */
542 sim_activate (uptr, 0); /* finish asap */
543 }
544 else { /* cylinder ok */
545 uptr->STD = uptr->STD & ~STD_SKI; /* clr seek inc */
546 diff = idd_dcy[u] - uptr->CYL;
547 if (diff < 0) diff = -diff; /* ABS cyl diff */
548 else if (diff == 0) diff = 1; /* must be nz */
549 sim_activate (uptr, diff * idc_stime);
550 }
551 }
552 } /* end else p1 */
553 return SCPE_OK; /* end if drv */
554 }
555
556 switch (uptr->FNC & CMC_MASK) { /* case on func */
557
558 case CMC_RCHK: /* read check */
559 idc_dter (uptr, 1); /* check xfr err */
560 break;
561
562 #if defined (ID_IDC)
563 case CMC_RUNC: /* read uncorr */
564 #endif
565 case CMC_RD: /* read */
566 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */
567 if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */
568 if (r = idc_rds (uptr)) return r; /* read sec, err? */
569 idc_1st = 0;
570 t = sch_wrmem (idc_dib.sch, idcxb, IDC_NUMBY); /* write mem */
571 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */
572 sim_activate (uptr, idc_rtime); /* reschedule */
573 return SCPE_OK;
574 }
575 break; /* no, set done */
576 }
577 idc_sta = idc_sta | STC_DTE; /* cant work */
578 break;
579
580 case CMC_WR: /* write */
581 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */
582 if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */
583 idc_bptr = sch_rdmem (idc_dib.sch, idcxb, IDC_NUMBY); /* read mem */
584 idc_db = idcxb[idc_bptr - 1]; /* last byte */
585 if (r = idc_wds (uptr)) return r; /* write sec, err? */
586 idc_1st = 0;
587 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */
588 sim_activate (uptr, idc_rtime); /* reschedule */
589 return SCPE_OK;
590 }
591 break; /* no, set done */
592 }
593 idc_sta = idc_sta | STC_DTE; /* cant work */
594 break;
595
596 case CMC_FCHK: case CMC_RFMT: case CMC_WFMT: case CMC_WFTK:
597 idc_dter (uptr, 1);
598 idc_sta = idc_sta | STC_WRP;
599 break;
600
601 #if defined (ID_IDC)
602 case CMC_RRAM: /* read RAM */
603 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */
604 sch_wrmem (idc_dib.sch, idcxb, IDC_NUMBY * 3);
605 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */
606 sim_activate (uptr, idc_rtime); /* reschedule */
607 return SCPE_OK;
608 }
609 break; /* no, set done */
610 }
611 idc_sta = idc_sta | STC_DTE; /* cant work */
612 break;
613
614 case CMC_WRAM: /* write RAM */
615 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */
616 sch_rdmem (idc_dib.sch, idcxb, IDC_NUMBY * 3); /* read from mem */
617 if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */
618 sim_activate (uptr, idc_rtime); /* reschedule */
619 return SCPE_OK;
620 }
621 break; /* no, set done */
622 }
623 idc_sta = idc_sta | STC_DTE; /* cant work */
624 break;
625
626 case CMC_STST: case CMC_LAMP: /* tests */
627 break;
628 #endif
629
630 default:
631 idc_sta = idc_sta | STC_DTE;
632 break;
633 }
634
635 idc_done (0); /* done */
636 return SCPE_OK;
637 }
638
639 /* Read data sector */
640
641 t_stat idc_rds (UNIT *uptr)
642 {
643 uint32 i;
644
645 i = fxread (idcxb, sizeof (uint8), IDC_NUMBY, uptr->fileref);
646 if (ferror (uptr->fileref)) { /* error? */
647 perror ("IDC I/O error");
648 clearerr (uptr->fileref);
649 idc_done (STC_DTE);
650 return SCPE_IOERR;
651 }
652 for ( ; i < IDC_NUMBY; i++) idcxb[i] = 0; /* fill with 0's */
653 return SCPE_OK;
654 }
655
656 /* Write data sector */
657
658 t_bool idc_wds (UNIT *uptr)
659 {
660 for ( ; idc_bptr < IDC_NUMBY; idc_bptr++)
661 idcxb[idc_bptr] = idc_db; /* fill with last */
662 fxwrite (idcxb, sizeof (uint8), IDC_NUMBY, uptr->fileref);
663 if (ferror (uptr->fileref)) { /* error? */
664 perror ("IDC I/O error");
665 clearerr (uptr->fileref);
666 idc_done (STC_DTE);
667 return SCPE_IOERR;
668 }
669 return FALSE;
670 }
671
672 /* Data transfer error test routine */
673
674 t_bool idc_dter (UNIT *uptr, uint32 first)
675 {
676 uint32 cy;
677 uint32 hd, sc, sa;
678 uint32 dtype = GET_DTYPE (uptr->flags); /* get drive type */
679
680 if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
681 idc_done (STC_DTE); /* error, done */
682 return TRUE;
683 }
684 if ((uptr->flags & UNIT_WPRT) && (uptr->FNC == CMC_WR)) {
685 idc_done (STC_WRP); /* error, done */
686 return TRUE;
687 }
688 cy = uptr->CYL; /* get cylinder */
689 hd = uptr->HD; /* get head */
690 sc = idc_sec & SC_MASK; /* get sector */
691 if (cy >= drv_tab[dtype].cyl) { /* bad cylinder? */
692 uptr->STD = uptr->STD | STD_SKI; /* error */
693 idc_done (STC_DTE); /* error, done */
694 return TRUE;
695 }
696 if (hd >= drv_tab[dtype].surf) { /* bad head? */
697 if (first) { /* 1st xfer? */
698 uptr->STD = uptr->STD | STD_UNS; /* drive unsafe */
699 idc_done (STC_ACF);
700 }
701 else idc_done (STC_CYO); /* no, cyl ovf */
702 return TRUE;
703 }
704 sa = GET_SA (cy, hd, sc, dtype); /* curr disk addr */
705 fseek (uptr->fileref, sa * IDC_NUMBY, SEEK_SET); /* seek to pos */
706 idc_sec = (idc_sec + 1) & SC_MASK; /* incr disk addr */
707 if (idc_sec == 0) uptr->HD = uptr->HD + 1;
708 return FALSE;
709 }
710
711 /* Data transfer done routine */
712
713 void idc_done (uint32 flg)
714 {
715 idc_sta = (idc_sta | STC_IDL | flg) & ~STA_BSY; /* set flag, idle */
716 if (idc_arm) SET_INT (v_IDC); /* if armed, intr */
717 int_req[l_IDC] = int_req[l_IDC] | idd_sirq; /* restore drv ints */
718 idd_sirq = 0; /* clear saved */
719 if (flg) sch_stop (idc_dib.sch); /* if err, stop sch */
720 return;
721 }
722
723 /* Reset routine */
724
725 t_stat idc_reset (DEVICE *dptr)
726 {
727 uint32 u;
728 UNIT *uptr;
729
730 idc_sta = STC_IDL | STA_BSY; /* idle, busy */
731 idc_wdptr = 0;
732 idd_wdptr = 0;
733 idc_1st = 0; /* clear flag */
734 idc_svun = idc_db = 0; /* clear unit, buf */
735 idc_sec = 0; /* clear addr */
736 idc_hcyl = 0;
737 CLR_INT (v_IDC); /* clear ctrl int */
738 CLR_ENB (v_IDC); /* clear ctrl enb */
739 idc_arm = 0; /* clear ctrl arm */
740 idd_sirq = 0;
741 for (u = 0; u < ID_NUMDR; u++) { /* loop thru units */
742 uptr = idc_dev.units + u;
743 uptr->CYL = uptr->STD = 0;
744 uptr->HD = uptr->FNC = 0;
745 idd_dcy[u] = 0;
746 CLR_INT (v_IDC + u + 1); /* clear intr */
747 CLR_ENB (v_IDC + u + 1); /* clear enable */
748 idd_arm[u] = 0; /* clear arm */
749 sim_cancel (uptr); /* cancel activity */
750 }
751 return SCPE_OK;
752 }
753
754 /* Attach routine (with optional autosizing) */
755
756 t_stat idc_attach (UNIT *uptr, char *cptr)
757 {
758 uint32 i, p;
759 t_stat r;
760
761 uptr->capac = drv_tab[GET_DTYPE (uptr->flags)].size;
762 r = attach_unit (uptr, cptr); /* attach unit */
763 if (r != SCPE_OK) return r; /* error? */
764 uptr->CYL = 0;
765 if ((uptr->flags & UNIT_AUTO) == 0) return SCPE_OK; /* autosize? */
766 if ((p = ftell (uptr->fileref)) == 0) return SCPE_OK;
767 for (i = 0; drv_tab[i].surf != 0; i++) {
768 if (p <= drv_tab[i].size) {
769 uptr->flags = (uptr->flags & ~UNIT_DTYPE) | (i << UNIT_V_DTYPE);
770 uptr->capac = drv_tab[i].size;
771 return SCPE_OK;
772 }
773 }
774 return SCPE_OK;
775 }
776
777 /* Set size command validation routine */
778
779 t_stat idc_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
780 {
781 if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
782 uptr->capac = drv_tab[GET_DTYPE (val)].size;
783 return SCPE_OK;
784 }
Magically enhanced SIMH