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First Commit of my working state
[simh.git] / LGP / lgp_cpu.c
1 /* lgp_cpu.c: LGP CPU simulator
2
3 Copyright (c) 2004-2005, Robert M. Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 cpu LGP-30 [LGP-21] CPU
27
28 22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
29 04-Sep-05 RMS Fixed missing returns (found by Peter Schorn)
30 04-Jan-05 RMS Modified VM pointer setup
31
32 The system state for the LGP-30 [LGP-21] is:
33
34 A<0:31> accumulator
35 C<0:11> counter (PC)
36 OVF overflow flag [LGP-21 only]
37
38 The LGP-30 [LGP-21] has just one instruction format:
39
40 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
41 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
42 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
43 |S| |opcode | | operand address | |
44 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
45
46 LGP-30 instructions:
47
48 <0,12:15> operation
49
50 0 stop
51 1 A <- M[ea]
52 2 M[ea]<addr> <- A<addr>
53 3 M[ea]<addr> <- C + 1
54 4 input
55 5 A <- A / M[ea]
56 6 A <- A * M[ea], low result
57 7 A <- A * M[ea], high result
58 8 output
59 9 A <- A & M[ea]
60 A C <- ea
61 B C <- ea if A < 0
62 -B C <- ea if (A < 0) || T-switch set
63 C M[ea] <- A
64 D M[ea] <- A, A <- 0
65 E A <- A + M[ea]
66 F A <- A - M[ea]
67
68 LGP-21 instructions:
69
70 <0,12:15> operation
71
72 0 stop; sense and skip
73 -0 stop; sense overflow and skip
74 1 A <- M[ea]
75 2 M[ea]<addr> <- A<addr>
76 3 M[ea]<addr> <- C + 1
77 4 6b input
78 -4 4b input
79 5 A <- A / M[ea]
80 6 A <- A * M[ea], low result
81 7 A <- A * M[ea], high result
82 8 6b output
83 -8 4b output
84 9 A <- A & M[ea]
85 A C <- ea
86 B C <- ea if A < 0
87 -B C <- ea if (A < 0) || T-switch set
88 C M[ea] <- A
89 D M[ea] <- A, A <- 0
90 E A <- A + M[ea]
91 F A <- A - M[ea]
92
93 The LGP-30 [LGP-21] has 4096 32b words of memory. The low order
94 bit is always read and stored as 0. The LGP-30 uses a drum for
95 memory, with 64 tracks of 64 words. The LGP-21 uses a disk for
96 memory, with 32 tracks of 128 words.
97
98 This routine is the instruction decode routine for the LGP-30
99 [LGP-21]. It is called from the simulator control program to
100 execute instructions in simulated memory, starting at the simulated
101 PC. It runs until 'reason' is set non-zero.
102
103 General notes:
104
105 1. Reasons to stop. The simulator can be stopped by:
106
107 STOP instruction
108 breakpoint encountered
109 overflow [LGP-30]
110 I/O error in I/O simulator
111
112 2. Interrupts. There are no interrupts.
113
114 3. Non-existent memory. All of memory always exists.
115
116 4. Adding I/O devices. The LGP-30 could not support additional
117 I/O devices. The LGP-21 could but none are known.
118 */
119
120 #include "lgp_defs.h"
121
122 #define PCQ_SIZE 64 /* must be 2**n */
123 #define PCQ_MASK (PCQ_SIZE - 1)
124 #define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = (PC - 1) & AMASK;
125 #define M16 0xFFFF
126 #define M32 0xFFFFFFFF
127 #define NEG(x) ((~(x) + 1) & DMASK)
128 #define ABS(x) (((x) & SIGN)? NEG (x): (x))
129
130 uint32 M[MEMSIZE] = { 0 }; /* memory */
131 uint32 PC = 0; /* counter */
132 uint32 A = 0; /* accumulator */
133 uint32 IR = 0; /* instr register */
134 uint32 OVF = 0; /* overflow indicator */
135 uint32 t_switch = 0; /* transfer switch */
136 uint32 bp32 = 0; /* BP32 switch */
137 uint32 bp16 = 0; /* BP16 switch */
138 uint32 bp8 = 0; /* BP8 switch */
139 uint32 bp4 = 0; /* BP4 switch */
140 uint32 inp_strt = 0; /* input started */
141 uint32 inp_done = 0; /* input done */
142 uint32 out_strt = 0; /* output started */
143 uint32 out_done = 0; /* output done */
144 uint32 lgp21_sov = 0; /* LGP-21 sense pending */
145 int32 delay = 0;
146 int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
147 int32 pcq_p = 0; /* PC queue ptr */
148 REG *pcq_r = NULL; /* PC queue reg ptr */
149
150 extern int32 sim_interval;
151 extern int32 sim_int_char;
152 extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
153 extern int32 sim_step;
154
155 t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
156 t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
157 t_stat cpu_reset (DEVICE *dptr);
158 t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc);
159 t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc);
160 t_stat cpu_set_30opt (UNIT *uptr, int32 val, char *cptr, void *desc);
161 t_stat cpu_set_30opt_i (UNIT *uptr, int32 val, char *cptr, void *desc);
162 t_stat cpu_set_30opt_o (UNIT *uptr, int32 val, char *cptr, void *desc);
163 t_stat cpu_set_fill (UNIT *uptr, int32 val, char *cptr, void *desc);
164 t_stat cpu_set_exec (UNIT *uptr, int32 val, char *cptr, void *desc);
165 t_stat cpu_one_inst (uint32 opc, uint32 ir);
166 uint32 Mul64 (uint32 a, uint32 b, uint32 *low);
167 t_bool Div32 (uint32 dvd, uint32 dvr, uint32 *q);
168 uint32 I_delay (uint32 opc, uint32 ea, uint32 op);
169 uint32 shift_in (uint32 a, uint32 dat, uint32 sh4);
170
171 extern t_stat op_p (uint32 dev, uint32 ch);
172 extern t_stat op_i (uint32 dev, uint32 ch, uint32 sh4);
173 extern void lgp_vm_init (void);
174
175 /* CPU data structures
176
177 cpu_dev CPU device descriptor
178 cpu_unit CPU unit descriptor
179 cpu_reg CPU register list
180 cpu_mod CPU modifiers list
181 */
182
183 UNIT cpu_unit = { UDATA (NULL, UNIT_FIX+UNIT_IN4B+UNIT_TTSS_D, MEMSIZE) };
184
185 REG cpu_reg[] = {
186 { DRDATA (C, PC, 12), REG_VMAD },
187 { HRDATA (A, A, 32), REG_VMIO },
188 { HRDATA (IR, IR, 32), REG_VMIO },
189 { FLDATA (OVF, OVF, 0) },
190 { FLDATA (TSW, t_switch, 0) },
191 { FLDATA (BP32, bp32, 0) },
192 { FLDATA (BP16, bp16, 0) },
193 { FLDATA (BP8, bp8, 0) },
194 { FLDATA (BP4, bp4, 0) },
195 { FLDATA (INPST, inp_strt, 0) },
196 { FLDATA (INPDN, inp_done, 0) },
197 { FLDATA (OUTST, out_strt, 0) },
198 { FLDATA (OUTDN, out_done, 0) },
199 { DRDATA (DELAY, delay, 7) },
200 { BRDATA (CQ, pcq, 16, 12, PCQ_SIZE), REG_RO + REG_CIRC },
201 { HRDATA (CQP, pcq_p, 6), REG_HRO },
202 { HRDATA (WRU, sim_int_char, 8) },
203 { NULL }
204 };
205
206 MTAB cpu_mod[] = {
207 { UNIT_LGP21, UNIT_LGP21, "LGP-21", "LGP21", &cpu_set_model, &cpu_show_model },
208 { UNIT_LGP21, 0, "LGP-30", "LGP30", &cpu_set_model, &cpu_show_model },
209 { UNIT_TTSS_D, UNIT_TTSS_D, 0, "TRACK" },
210 { UNIT_TTSS_D, 0, 0, "NORMAL" },
211 { UNIT_LGPH_D, UNIT_LGPH_D, 0, "LGPHEX" },
212 { UNIT_LGPH_D, 0, 0, "STANDARDHEX" },
213 { UNIT_MANI, UNIT_MANI, NULL, "MANUAL" },
214 { UNIT_MANI, 0, NULL, "TAPE" },
215 { UNIT_IN4B, UNIT_IN4B, NULL, "4B", &cpu_set_30opt },
216 { UNIT_IN4B, 0, NULL, "6B", &cpu_set_30opt },
217 { MTAB_XTD|MTAB_VDV, 0, NULL, "INPUT", &cpu_set_30opt_i },
218 { MTAB_XTD|MTAB_VDV, 0, NULL, "OUTPUT", &cpu_set_30opt_o },
219 { MTAB_XTD|MTAB_VDV, 0, NULL, "EXECUTE", &cpu_set_exec },
220 { MTAB_XTD|MTAB_VDV, 0, NULL, "FILL", &cpu_set_fill },
221 { 0 }
222 };
223
224 DEVICE cpu_dev = {
225 "CPU", &cpu_unit, cpu_reg, cpu_mod,
226 1, 10, 12, 1, 16, 32,
227 &cpu_ex, &cpu_dep, &cpu_reset,
228 NULL, NULL, NULL
229 };
230
231 /* Timing tables */
232
233 /* Optimization minima and maxima
234 Z B Y R I D N M P E U T H C A S */
235
236 static const int32 min_30[16] = {
237 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
238 };
239 static const int32 max_30[16] = {
240 7, 7, 7, 7, 7, 5, 8, 6, 7, 7, 0, 0, 7, 7, 7, 7
241 };
242 static const int32 min_21[16] = {
243 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
244 };
245 static const int32 max_21[16] = {
246 0, 16, 16, 16, 0, 58, 81, 79, 0, 16, 0, 0, 16, 16, 16, 16
247 };
248
249 static const uint32 log_to_phys_30[NSC_30] = { /* drum interlace chart */
250 0, 57, 50, 43, 36, 29, 22, 15, 8 ,
251 1, 58, 51, 44, 37, 30, 23, 16, 9 ,
252 2, 59, 52, 45, 38, 31, 24, 17, 10,
253 3, 60, 53, 46, 39, 32, 25, 18, 11,
254 4, 61, 54, 47, 40, 33, 26, 19, 12,
255 5, 62, 55, 48, 41, 32, 27, 20, 13,
256 6, 63, 56, 49, 42, 33, 28, 21, 14,
257 7
258 };
259
260 static const uint32 log_to_phys_21[NSC_21] = { /* disk interlace chart */
261 0, 64, 57, 121, 50, 114, 43, 107, 36, 100, 29, 93, 22, 86, 15, 79, 8, 72,
262 1, 65, 58, 122, 51, 115, 44, 108, 37, 101, 30, 94, 23, 87, 16, 80, 9, 73,
263 2, 66, 59, 123, 52, 116, 45, 109, 38, 102, 31, 95, 24, 88, 17, 81, 10, 74,
264 3, 67, 60, 124, 53, 117, 46, 110, 39, 103, 32, 96, 25, 89, 18, 82, 11, 75,
265 4, 68, 61, 125, 54, 118, 47, 111, 40, 104, 33, 97, 26, 90, 19, 83, 12, 76,
266 5, 69, 62, 126, 55, 119, 48, 112, 41, 105, 34, 98, 27, 91, 20, 84, 12, 77,
267 6, 70, 63, 127, 56, 120, 49, 113, 42, 106, 35, 99, 28, 92, 21, 85, 13, 78,
268 7, 71
269 };
270
271 t_stat sim_instr (void)
272 {
273 t_stat r = 0;
274 uint32 oPC;
275
276 /* Restore register state */
277
278 PC = PC & AMASK; /* mask PC */
279 sim_cancel_step (); /* defang SCP step */
280 if (lgp21_sov) { /* stop sense pending? */
281 lgp21_sov = 0;
282 if (!OVF) PC = (PC + 1) & AMASK; /* ovf off? skip */
283 else OVF = 0; /* on? reset */
284 }
285
286 /* Main instruction fetch/decode loop */
287
288 do {
289 if (sim_interval <= 0) { /* check clock queue */
290 if (r = sim_process_event ()) break;
291 }
292
293 if (delay > 0) { /* delay to next instr */
294 delay = delay - 1; /* count down delay */
295 sim_interval = sim_interval - 1;
296 continue; /* skip execution */
297 }
298
299 if (sim_brk_summ && /* breakpoint? */
300 sim_brk_test (PC, SWMASK ('E'))) {
301 r = STOP_IBKPT; /* stop simulation */
302 break;
303 }
304
305 IR = Read (oPC = PC); /* get instruction */
306 PC = (PC + 1) & AMASK; /* increment PC */
307 sim_interval = sim_interval - 1;
308
309 if (r = cpu_one_inst (oPC, IR)) { /* one instr; error? */
310 if (r == STOP_STALL) { /* stall? */
311 PC = oPC; /* back up PC */
312 delay = r = 0; /* no delay */
313 }
314 else break;
315 }
316
317 if (sim_step && (--sim_step <= 0)) /* do step count */
318 r = SCPE_STOP;
319
320 } while (r == 0); /* loop until halted */
321 pcq_r->qptr = pcq_p; /* update pc q ptr */
322 return r;
323 }
324
325 /* Execute one instruction */
326
327 t_stat cpu_one_inst (uint32 opc, uint32 ir)
328 {
329 uint32 ea, op, dat, res, dev, sh4, ch;
330 t_bool ovf_this_cycle = FALSE;
331 t_stat reason = 0;
332
333 op = I_GETOP (ir); /* opcode */
334 ea = I_GETEA (ir); /* address */
335 switch (op) { /* case on opcode */
336
337 /* Loads, stores, transfers instructions */
338
339 case OP_B: /* bring */
340 A = Read (ea); /* A <- M[ea] */
341 delay = I_delay (opc, ea, op);
342 break;
343
344 case OP_H: /* hold */
345 Write (ea, A); /* M[ea] <- A */
346 delay = I_delay (opc, ea, op);
347 break;
348
349 case OP_C: /* clear */
350 Write (ea, A); /* M[ea] <- A */
351 A = 0; /* A <- 0 */
352 delay = I_delay (opc, ea, op);
353 break;
354
355 case OP_Y: /* store address */
356 dat = Read (ea); /* get operand */
357 dat = (dat & ~I_EA) | (A & I_EA); /* merge address */
358 Write (ea, dat);
359 delay = I_delay (opc, ea, op);
360 break;
361
362 case OP_R: /* return address */
363 dat = Read (ea); /* get operand */
364 dat = (dat & ~I_EA) | (((PC + 1) & AMASK) << I_V_EA);
365 Write (ea, dat);
366 delay = I_delay (opc, ea, op);
367 break;
368
369 case OP_U: /* uncond transfer */
370 PCQ_ENTRY;
371 PC = ea; /* transfer */
372 delay = I_delay (opc, ea, op);
373 break;
374
375 case OP_T: /* conditional transfer */
376 if ((A & SIGN) || /* A < 0 or */
377 ((ir & SIGN) && t_switch)) { /* -T and Tswitch set? */
378 PCQ_ENTRY;
379 PC = ea; /* transfer */
380 }
381 delay = I_delay (opc, ea, op);
382 break;
383
384 /* Arithmetic and logical instructions */
385
386 case OP_A: /* add */
387 dat = Read (ea); /* get operand */
388 res = (A + dat) & DMASK; /* add */
389 if ((~A ^ dat) & (dat ^ res) & SIGN) /* calc overflow */
390 ovf_this_cycle = TRUE;
391 A = res; /* save result */
392 delay = I_delay (opc, ea, op);
393 break;
394
395 case OP_S: /* sub */
396 dat = Read (ea); /* get operand */
397 res = (A - dat) & DMASK; /* subtract */
398 if ((A ^ dat) & (~dat ^ res) & SIGN) /* calc overflow */
399 ovf_this_cycle = TRUE;
400 A = res;
401 delay = I_delay (opc, ea, op);
402 break;
403
404 case OP_M: /* multiply high */
405 dat = Read (ea); /* get operand */
406 A = (Mul64 (A, dat, NULL) << 1) & DMASK; /* multiply */
407 delay = I_delay (opc, ea, op);
408 break;
409
410 case OP_N: /* multiply low */
411 dat = Read (ea); /* get operand */
412 Mul64 (A, dat, &res); /* multiply */
413 A = res; /* keep low result */
414 delay = I_delay (opc, ea, op); /* total delay */
415 break;
416
417 case OP_D: /* divide */
418 dat = Read (ea); /* get operand */
419 if (Div32 (A, dat, &A)) ovf_this_cycle = TRUE; /* divide; overflow? */
420 delay = I_delay (opc, ea, op);
421 break;
422
423 case OP_E: /* extract */
424 dat = Read (ea); /* get operand */
425 A = A & dat; /* and */
426 delay = I_delay (opc, ea, op);
427 break;
428
429 /* IO instructions */
430
431 case OP_P: /* output */
432 if (Q_LGP21) { /* LGP-21 */
433 ch = A >> 26; /* char, 6b */
434 if (ir & SIGN) ch = (ch & 0x3C) | 2; /* 4b? convert */
435 dev = I_GETTK (ir); /* device select */
436 }
437 else { /* LGP-30 */
438 ch = I_GETTK (ir); /* char, always 6b */
439 dev = Q_OUTPT? DEV_PT: DEV_TT; /* device select */
440 }
441 reason = op_p (dev & DEV_MASK, ch); /* output */
442 delay = I_delay (sim_grtime (), ea, op); /* next instruction */
443 break;
444
445 case OP_I: /* input */
446 if (Q_LGP21) { /* LGP-21 */
447 ch = 0; /* initial shift */
448 sh4 = ir & SIGN; /* 4b/6b select */
449 dev = I_GETTK (ir); /* device select */
450 }
451 else { /* LGP-30 */
452 ch = I_GETTK (ir); /* initial shift */
453 sh4 = Q_IN4B; /* 4b/6b select */
454 dev = Q_INPT? DEV_PT: DEV_TT; /* device select */
455 }
456 if (dev == DEV_SHIFT) /* shift? */
457 A = shift_in (A, 0, sh4); /* shift 4/6b */
458 else reason = op_i (dev & DEV_MASK, ch, sh4); /* input */
459 delay = I_delay (sim_grtime (), ea, op); /* next instruction */
460 break;
461
462 case OP_Z:
463 if (Q_LGP21) { /* LGP-21 */
464 if (ea & 0xF80) { /* no stop? */
465 if (((ea & 0x800) && !bp32) || /* skip if any */
466 ((ea & 0x400) && !bp16) || /* selected switch */
467 ((ea & 0x200) && !bp8) || /* is off */
468 ((ea & 0x100) && !bp4) || /* or if */
469 ((ir & SIGN) && !OVF)) /* ovf sel and off */
470 PC = (PC + 1) & AMASK;
471 if (ir & SIGN) OVF = 0; /* -Z? clr overflow */
472 }
473 else { /* stop */
474 lgp21_sov = (ir & SIGN)? 1: 0; /* pending sense? */
475 reason = STOP_STOP; /* stop */
476 }
477 }
478 else { /* LGP-30 */
479 if (out_done) out_done = 0; /* P complete? */
480 else if (((ea & 0x800) && bp32) || /* bpt switch set? */
481 ((ea & 0x400) && bp16) ||
482 ((ea & 0x200) && bp8) ||
483 ((ea & 0x100) && bp4)) ; /* don't stop or stall */
484 else if (out_strt) reason = STOP_STALL; /* P pending? stall */
485 else reason = STOP_STOP; /* no, stop */
486 }
487 delay = I_delay (sim_grtime (), ea, op); /* next instruction */
488 break; /* end switch */
489 }
490
491 if (ovf_this_cycle) {
492 if (Q_LGP21) OVF = 1; /* LGP-21? set OVF */
493 else reason = STOP_OVF; /* LGP-30? stop */
494 }
495 return reason;
496 }
497
498 /* Support routines */
499
500 uint32 Read (uint32 ea)
501 {
502 return M[ea] & MMASK;
503 }
504
505 void Write (uint32 ea, uint32 dat)
506 {
507 M[ea] = dat & MMASK;
508 return;
509 }
510
511 /* Input shift */
512
513 uint32 shift_in (uint32 a, uint32 dat, uint32 sh4)
514 {
515 if (sh4) return (((a << 4) | (dat >> 2)) & DMASK);
516 return (((a << 6) | dat) & DMASK);
517 }
518
519 /* 32b * 32b multiply, signed */
520
521 uint32 Mul64 (uint32 a, uint32 b, uint32 *low)
522 {
523 uint32 sgn = a ^ b;
524 uint32 ah, bh, al, bl, rhi, rlo, rmid1, rmid2;
525
526 if ((a == 0) || (b == 0)) { /* zero argument? */
527 if (low) *low = 0;
528 return 0;
529 }
530 a = ABS (a);
531 b = ABS (b);
532 ah = (a >> 16) & M16; /* split operands */
533 bh = (b >> 16) & M16; /* into 16b chunks */
534 al = a & M16;
535 bl = b & M16;
536 rhi = ah * bh; /* high result */
537 rmid1 = ah * bl;
538 rmid2 = al * bh;
539 rlo = al * bl;
540 rhi = rhi + ((rmid1 >> 16) & M16) + ((rmid2 >> 16) & M16);
541 rmid1 = (rlo + (rmid1 << 16)) & M32; /* add mid1 to lo */
542 if (rmid1 < rlo) rhi = rhi + 1; /* carry? incr hi */
543 rmid2 = (rmid1 + (rmid2 << 16)) & M32; /* add mid2 to to */
544 if (rmid2 < rmid1) rhi = rhi + 1; /* carry? incr hi */
545 if (sgn & SIGN) { /* result negative? */
546 rmid2 = NEG (rmid2); /* negate */
547 rhi = (~rhi + (rmid2 == 0)) & M32;
548 }
549 if (low) *low = rmid2; /* low result */
550 return rhi & M32;
551 }
552
553 /* 32b/32b divide (done as 32b'0/32b) */
554
555 t_bool Div32 (uint32 dvd, uint32 dvr, uint32 *q)
556 {
557 uint32 sgn = dvd ^ dvr;
558 uint32 i, quo;
559
560 dvd = ABS (dvd);
561 dvr = ABS (dvr);
562 if (dvd >= dvr) return TRUE;
563 for (i = quo = 0; i < 31; i++) { /* 31 iterations */
564 quo = quo << 1; /* shift quotient */
565 dvd = dvd << 1; /* shift dividend */
566 if (dvd >= dvr) { /* step work? */
567 dvd = (dvd - dvr) & M32; /* subtract dvr */
568 quo = quo + 1;
569 }
570 }
571 quo = (quo + 1) & MMASK; /* round low bit */
572 if (sgn & SIGN) quo = NEG (quo); /* result -? */
573 if (q) *q = quo; /* return quo */
574 return FALSE; /* no overflow */
575 }
576
577 /* Rotational delay */
578
579 uint32 I_delay (uint32 opc, uint32 ea, uint32 op)
580 {
581 uint32 tmin = Q_LGP21? min_21[op]: min_30[op];
582 uint32 tmax = Q_LGP21? max_21[op]: max_30[op];
583 uint32 nsc, curp, newp, oprp, pcdelta, opdelta;
584
585 if (Q_LGP21) { /* LGP21 */
586 nsc = NSC_21; /* full rotation delay */
587 curp = log_to_phys_21[opc & SCMASK_21]; /* current phys pos */
588 newp = log_to_phys_21[PC & SCMASK_21]; /* new PC phys pos */
589 oprp = log_to_phys_21[ea & SCMASK_21]; /* ea phys pos */
590 pcdelta = (newp - curp + NSC_21) & SCMASK_21;
591 opdelta = (oprp - curp + NSC_21) & SCMASK_21;
592 }
593 else {
594 nsc = NSC_30;
595 curp = log_to_phys_30[opc & SCMASK_30];
596 newp = log_to_phys_30[PC & SCMASK_30];
597 oprp = log_to_phys_30[ea & SCMASK_30];
598 pcdelta = (newp - curp + NSC_30) & SCMASK_30;
599 opdelta = (oprp - curp + NSC_30) & SCMASK_30;
600 }
601 if (tmax == 0) { /* skip ea calc? */
602 if (pcdelta >= tmin) return pcdelta - 1; /* new PC >= min? */
603 return pcdelta + nsc - 1;
604 }
605 if ((opdelta >= tmin) && (opdelta <= tmax)) return pcdelta - 1;
606 return pcdelta + nsc - 1;
607 }
608
609 /* Reset routine */
610
611 t_stat cpu_reset (DEVICE *dptr)
612 {
613 OVF = 0;
614 inp_strt = 0;
615 inp_done = 0;
616 out_strt = 0;
617 out_done = 0;
618 lgp21_sov = 0;
619 delay = 0;
620 lgp_vm_init ();
621 pcq_r = find_reg ("CQ", NULL, dptr);
622 if (pcq_r) pcq_r->qptr = 0;
623 else return SCPE_IERR;
624 sim_brk_types = sim_brk_dflt = SWMASK ('E');
625 return SCPE_OK;
626 }
627
628 /* Validate option, must be LGP30 */
629
630 t_stat cpu_set_30opt (UNIT *uptr, int32 val, char *cptr, void *desc)
631 {
632 if (Q_LGP21) return SCPE_ARG;
633 return SCPE_OK;
634 }
635
636 /* Validate input option, must be LGP30 */
637
638 t_stat cpu_set_30opt_i (UNIT *uptr, int32 val, char *cptr, void *desc)
639 {
640 if (Q_LGP21 || (cptr == NULL)) return SCPE_ARG;
641 if (strcmp (cptr, "TTI") == 0) uptr->flags = uptr->flags & ~UNIT_INPT;
642 else if (strcmp (cptr, "PTR") == 0) uptr->flags = uptr->flags | UNIT_INPT;
643 else return SCPE_ARG;
644 return SCPE_OK;
645 }
646
647 /* Validate output option, must be LGP30 */
648
649 t_stat cpu_set_30opt_o (UNIT *uptr, int32 val, char *cptr, void *desc)
650 {
651 if (Q_LGP21 || (cptr == NULL)) return SCPE_ARG;
652 if (strcmp (cptr, "TTO") == 0) uptr->flags = uptr->flags & ~UNIT_OUTPT;
653 else if (strcmp (cptr, "PTP") == 0) uptr->flags = uptr->flags | UNIT_OUTPT;
654 else return SCPE_ARG;
655 return SCPE_OK;
656 }
657
658 /* Set CPU to LGP21 or LPG30 */
659
660 t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc)
661 {
662 if (val) uptr->flags = uptr->flags & ~(UNIT_IN4B|UNIT_INPT|UNIT_OUTPT);
663 return reset_all (0);
664 }
665
666 /* Show CPU type and all options */
667
668 t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
669 {
670 fputs (Q_LGP21? "LGP-21": "LGP-30", st);
671 if (uptr->flags & UNIT_TTSS_D) fputs (", track/sector", st);
672 if (uptr->flags & UNIT_LGPH_D) fputs (", LGP hex", st);
673 fputs (Q_MANI? ", manual": ", tape", st);
674 if (!Q_LGP21) {
675 fputs (Q_IN4B? ", 4b": ", 6b", st);
676 fputs (Q_INPT? ", in=PTR": ", in=TTI", st);
677 fputs (Q_OUTPT? ", out=PTP": ", out=TTO", st);
678 }
679 return SCPE_OK;
680 }
681
682 /* Memory examine */
683
684 t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
685 {
686 if (addr >= MEMSIZE) return SCPE_NXM;
687 if (vptr != NULL) *vptr = Read (addr);
688 return SCPE_OK;
689 }
690
691 /* Memory deposit */
692
693 t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
694 {
695 if (addr >= MEMSIZE) return SCPE_NXM;
696 Write (addr, val);
697 return SCPE_OK;
698 }
699
700 /* Execute */
701
702 t_stat cpu_set_exec (UNIT *uptr, int32 val, char *cptr, void *desc)
703 {
704 uint32 inst;
705 t_stat r;
706
707 if (cptr) {
708 inst = get_uint (cptr, 16, DMASK, &r);
709 if (r != SCPE_OK) return r;
710 }
711 else inst = IR;
712 while ((r = cpu_one_inst (PC, inst)) == STOP_STALL) {
713 sim_interval = 0;
714 if (r = sim_process_event ()) return r;
715 }
716 return r;
717 }
718
719 /* Fill */
720
721 t_stat cpu_set_fill (UNIT *uptr, int32 val, char *cptr, void *desc)
722 {
723 uint32 inst;
724 t_stat r;
725
726 if (cptr) {
727 inst = get_uint (cptr, 16, DMASK, &r);
728 if (r != SCPE_OK) return r;
729 IR = inst;
730 }
731 else IR = A;
732 return SCPE_OK;
733 }
Magically enhanced SIMH