PDP1/pdp1_clk.c

   1 /* pdp1_clk.c: PDP-1D clock simulator
   2
   3    Copyright (c) 2006, Robert M. Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    bused in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    clk          PDP-1D clock
  27
  28    Note that the clock is run at 1/8 of real speed (125Hz instead of 1Khz), to
  29    provide for eventual implementation of idling.
  30 */
  31
  32 #include "pdp1_defs.h"
  33
  34 #define CLK_HWRE_TPS    1000                            /* hardware freq */
  35 #define CLK_TPS         125                             /* sim freq */
  36 #define CLK_CNTS        (CLK_HWRE_TPS / CLK_TPS)        /* counts per tick */
  37 #define CLK_C1MIN       (1000 * 60)                     /* counts per min */
  38 #define CLK_C32MS       32                              /* counts per 32ms */
  39
  40 int32 clk32ms_sbs = 0;                                  /* 32ms SBS level */
  41 int32 clk1min_sbs = 0;                                  /* 1min SBS level */
  42 int32 clk_cntr = 0;
  43 int32 tmxr_poll = 5000;
  44
  45 extern int32 stop_inst;
  46
  47 t_stat clk_svc (UNIT *uptr);
  48 t_stat clk_reset (DEVICE *dptr);
  49
  50 /* CLK data structures
  51
  52    clk_dev      CLK device descriptor
  53    clk_unit     CLK unit
  54    clk_reg      CLK register list
  55 */
  56
  57 UNIT clk_unit = {
  58     UDATA (&clk_svc, 0, 0), 5000
  59     };
  60
  61 REG clk_reg[] = {
  62     { ORDATA (CNTR, clk_cntr, 16) },
  63     { DRDATA (SBS32LVL, clk32ms_sbs, 4), REG_HRO },
  64     { DRDATA (SBS1MLVL, clk1min_sbs, 4), REG_HRO },
  65     { NULL }
  66     };
  67
  68 MTAB clk_mod[] = {
  69     { MTAB_XTD|MTAB_VDV, 0, "SBS32MSLVL", "SBS32MSLVL",
  70       &dev_set_sbs, &dev_show_sbs, (void *) &clk32ms_sbs },
  71     { MTAB_XTD|MTAB_VDV, 0, "SBS1MINLVL", "SBS1MINLVL",
  72       &dev_set_sbs, &dev_show_sbs, (void *) &clk1min_sbs },
  73     { 0 }
  74     };
  75
  76 DEVICE clk_dev = {
  77     "CLK", &clk_unit, clk_reg, clk_mod,
  78     1, 10, 31, 1, 8, 8,
  79     NULL, NULL, &clk_reset,
  80     NULL, NULL, NULL,
  81     NULL, DEV_DISABLE | DEV_DIS
  82     };
  83
  84 /* Clock IOT routine */
  85
  86 int32 clk (int32 inst, int32 dev, int32 dat)
  87 {
  88 int32 used, incr;
  89
  90 if (clk_dev.flags & DEV_DIS)                            /* disabled? */
  91     return (stop_inst << IOT_V_REASON) | dat;           /* illegal inst */
  92 used = tmxr_poll - (sim_is_active (&clk_unit) - 1);
  93 incr = (used * CLK_CNTS) / tmxr_poll;
  94 return clk_cntr + incr;
  95 }
  96
  97 /* Unit service, generate appropriate interrupts */
  98
  99 t_stat clk_svc (UNIT *uptr)
 100 {
 101 if (clk_dev.flags & DEV_DIS) return SCPE_OK;            /* disabled? */
 102 tmxr_poll = sim_rtcn_calb (CLK_TPS, TMR_CLK);           /* calibrate clock */
 103 sim_activate (&clk_unit, tmxr_poll);                    /* reactivate unit */
 104 clk_cntr = clk_cntr + CLK_CNTS;                         /* incr counter */
 105 if ((clk_cntr % CLK_C32MS) == 0)                        /* 32ms interval? */
 106     dev_req_int (clk32ms_sbs);                          /* req intr */
 107 if (clk_cntr >= CLK_C1MIN) {                            /* 1min interval? */
 108     dev_req_int (clk1min_sbs);                          /* req intr */
 109     clk_cntr = 0;                                       /* reset counter */
 110     }
 111 return SCPE_OK;
 112 }
 113
 114 /* Reset routine */
 115
 116 t_stat clk_reset (DEVICE *dptr)
 117 {
 118 if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit);    /* disabled? */
 119 else {
 120     tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK);
 121     sim_activate_abs (&clk_unit, tmxr_poll);            /* activate unit */
 122     }
 123 clk_cntr = 0;                                           /* clear counter */
 124 return SCPE_OK;
 125 }