PDP1/pdp1_defs.h

   1 /* pdp1_defs.h: 18b PDP simulator definitions
   2
   3    Copyright (c) 1993-2006, Robert M. Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    21-Dec-06    RMS     Added 16-channel sequence break support
  27    22-Jul-05    RMS     Fixed definition of CPLS_DPY
  28    08-Feb-04    PLB     Added support for display
  29    08-Dec-03    RMS     Added support for parallel drum
  30    18-Oct-03    RMS     Added DECtape off reel message
  31    22-Jul-03    RMS     Updated for "hardware" RIM loader
  32                         Revised to detect I/O wait hang
  33    05-Dec-02    RMS     Added IOT skip support (required by drum)
  34    14-Apr-99    RMS     Changed t_addr to unsigned
  35
  36    The PDP-1 was Digital's first computer.  The system design evolved during
  37    its life, and as a result, specifications are sketchy or contradictory.
  38    This simulator is based on the 1962 maintenance manual.
  39
  40    This simulator implements the following options:
  41
  42    Automatic multiply/divide    Type 10
  43    Memory extension control     Type 15
  44    Parallel drum                Type 23
  45    Serial drum                  Type 24
  46    Graphic display              Type 30
  47    Line printer control         Type 62
  48    Microtape (DECtape) control  Type 550
  49 */
  50
  51 #ifndef _PDP1_DEFS_H_
  52 #define _PDP1_DEFS_H_   0
  53
  54 #include "sim_defs.h"
  55
  56 /* Simulator stop codes */
  57
  58 #define STOP_RSRV       1                               /* must be 1 */
  59 #define STOP_HALT       2                               /* HALT */
  60 #define STOP_IBKPT      3                               /* breakpoint */
  61 #define STOP_XCT        4                               /* nested XCT's */
  62 #define STOP_IND        5                               /* nested indirects */
  63 #define STOP_WAIT       6                               /* IO wait hang */
  64 #define STOP_DTOFF      7                               /* DECtape off reel */
  65 #define ERR_RMV         10                              /* restrict mode viol */
  66
  67 /* Memory */
  68
  69 #define ASIZE           16                              /* address bits */
  70 #define MAXMEMSIZE      (1u << ASIZE)                   /* max mem size */
  71 #define AMASK           (MAXMEMSIZE - 1)                /* address mask */
  72 #define MEMSIZE         (cpu_unit.capac)                /* actual memory size */
  73 #define MEM_ADDR_OK(x)  (((uint32) (x)) < MEMSIZE)
  74
  75 /* Architectural constants */
  76
  77 #define SIGN            0400000                         /* sign */
  78 #define DMASK           0777777                         /* data mask */
  79 #define DAMASK          0007777                         /* direct addr */
  80 #define EPCMASK         (AMASK & ~DAMASK)               /* extended addr */
  81 #define IA              0010000                         /* indirect flag */
  82 #define IO_WAIT         0010000                         /* I/O sync wait */
  83 #define IO_CPLS         0004000                         /* completion pulse */
  84 #define OP_DAC          0240000                         /* DAC */
  85 #define OP_DIO          0320000                         /* DIO */
  86 #define OP_JMP          0600000                         /* JMP */
  87 #define GEN_CPLS(x)     (((x) ^ ((x) << 1)) & IO_WAIT)  /* completion pulse? */
  88
  89 /* Program flags/sense switches */
  90
  91 #define PF_V_L          7
  92 #define PF_V_RNG        6
  93 #define PF_L            (1u << PF_V_L)
  94 #define PF_RNG          (1u << PF_V_RNG)
  95 #define PF_SS_1         0040
  96 #define PF_SS_2         0020
  97 #define PF_SS_3         0010
  98 #define PF_SS_4         0004
  99 #define PF_SS_5         0002
 100 #define PF_SS_6         0001
 101 #define PF_VR_ALL       0377
 102 #define PF_SS_ALL       0077
 103
 104 /* Restict mode */
 105
 106 #define RTB_IOT         0400000
 107 #define RTB_ILL         0200000
 108 #define RTB_HLT         0100000
 109 #define RTB_DBK         0040000
 110 #define RTB_CHR         0020000
 111 #define RTB_MB_MASK     0017777
 112
 113 #define RM45_V_BNK      14
 114 #define RM45_M_BNK      003
 115 #define RM48_V_BNK      12
 116 #define RM48_M_BNK      017
 117
 118 #define RN45_SIZE       4
 119
 120 /* IOT subroutine return codes */
 121
 122 #define IOT_V_SKP       18                              /* skip */
 123 #define IOT_SKP         (1 << IOT_V_SKP)
 124 #define IOT_V_REASON    (IOT_V_SKP + 1)                 /* reason */
 125 #define IOT_REASON      (1 << IOT_V_REASON)
 126 #define IORETURN(f,v)   ((f)? (v): SCPE_OK)             /* stop on error */
 127
 128 /* I/O status flags */
 129
 130 #define IOS_V_LPN       17                              /* light pen */
 131 #define IOS_V_PTR       16                              /* paper tape reader */
 132 #define IOS_V_TTO       15                              /* typewriter out */
 133 #define IOS_V_TTI       14                              /* typewriter in */
 134 #define IOS_V_PTP       13                              /* paper tape punch */
 135 #define IOS_V_DRM       12                              /* drum */
 136 #define IOS_V_SQB       11                              /* sequence break */
 137 #define IOS_V_PNT       3                               /* print done */
 138 #define IOS_V_SPC       2                               /* space done */
 139 #define IOS_V_DCS       1                               /* data comm sys */
 140 #define IOS_V_DRP       0                               /* parallel drum busy */
 141
 142 #define IOS_LPN         (1 << IOS_V_LPN)
 143 #define IOS_PTR         (1 << IOS_V_PTR)
 144 #define IOS_TTO         (1 << IOS_V_TTO)
 145 #define IOS_TTI         (1 << IOS_V_TTI)
 146 #define IOS_PTP         (1 << IOS_V_PTP)
 147 #define IOS_DRM         (1 << IOS_V_DRM)
 148 #define IOS_SQB         (1 << IOS_V_SQB)
 149 #define IOS_PNT         (1 << IOS_V_PNT)
 150 #define IOS_SPC         (1 << IOS_V_SPC)
 151 #define IOS_DCS         (1 << IOS_V_DCS)
 152 #define IOS_DRP         (1 << IOS_V_DRP)
 153
 154 /* Completion pulses */
 155
 156 #define CPLS_V_PTR      5
 157 #define CPLS_V_PTP      4
 158 #define CPLS_V_TTO      3
 159 #define CPLS_V_LPT      2
 160 #define CPLS_V_DPY      1
 161 #define CPLS_PTR        (1 << CPLS_V_PTR)
 162 #define CPLS_PTP        (1 << CPLS_V_PTP)
 163 #define CPLS_TTO        (1 << CPLS_V_TTO)
 164 #define CPLS_LPT        (1 << CPLS_V_LPT)
 165 #define CPLS_DPY        (1 << CPLS_V_DPY)
 166
 167 /* One channel sequence break */
 168
 169 #define SB_V_IP         0                               /* in progress */
 170 #define SB_V_RQ         1                               /* request */
 171 #define SB_V_ON         2                               /* enabled */
 172
 173 #define SB_IP           (1 << SB_V_IP)
 174 #define SB_RQ           (1 << SB_V_RQ)
 175 #define SB_ON           (1 << SB_V_ON)
 176
 177 /* 16 channel sequence break */
 178
 179 #define SBS_LVLS        16                              /* num levels */
 180 #define SBS_LVL_MASK    (SBS_LVLS - 1)
 181 #define SBS_LVL_RMV     14                              /* restrict level */
 182 #define SBS_MASK(x)     (1u << (SBS_LVLS - 1 - (x)))    /* level to mask */
 183
 184 /* Timers */
 185
 186 #define TMR_CLK         0
 187
 188 /* Device routines */
 189
 190 t_stat dev_req_int (int32 lvl);
 191 t_stat dev_set_sbs (UNIT *uptr, int32 val, char *cptr, void *desc);
 192 t_stat dev_show_sbs (FILE *st, UNIT *uptr, int32 val, void *desc);
 193
 194 #endif