PDP10/pdp10_bug_history.txt

   1 Bugs Found and Fixed During Simulator Debug
   2
   3 1. pushj cleared T2 after setting it
   4 2. if timer autoadjust is enabled, timer diagnostic may fail,
   5    depending on host CPU speed
   6 3. DFAD/DFSB should use FP_ONES instead of ONES
   7 4. TLB physical address max = 1MW, tested in diagnostic
   8 5. DPB does read/write, not read-modify/write
   9 6. Fetch error takes priority over traps, due to prefetching
  10    of next instruction
  11 7. HSB is 36b, was 32b
  12 8. CPU and PAG devices had mismatched types
  13 9. non-zero sections in Tops-20 paging section indirect may
  14    cause non-existent memory error, due to microcode "error"
  15 10. PXCT test for user mode was backward
  16 11. Timer interrupts were not implemented in Tops-20 indirect
  17    chains
  18 12. epta/upta hit known bug in VC++ implementation of 64b
  19    data types
  20 13. final W calculation in Tops-20 paging was incorrect
  21 14. Timer representation lost sub msec values
  22 15. UBA initialization reset the UBA itself
  23 16. RHCS1: writing IE cannot trigger an interrupt
  24 17. Tape bootstrap was set to 800bpi instead of 1600bpi
  25 18. FIXR off by 1 in testing for lower limit to process