PDP10/pdp10_tim.c

   1 /* pdp10_tim.c: PDP-10 tim subsystem simulator
   2
   3    Copyright (c) 1993-2007, Robert M Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    tim          timer subsystem
  27
  28    18-Jun-07    RMS     Added UNIT_IDLE flag
  29    03-Nov-06    RMS     Rewritten to support idling
  30    29-Oct-06    RMS     Added clock coscheduling function
  31    02-Feb-04    RMS     Exported variables needed by Ethernet simulator
  32    29-Jan-02    RMS     New data structures
  33    06-Jan-02    RMS     Added enable/disable support
  34    02-Dec-01    RMS     Fixed bug in ITS PC sampling (found by Dave Conroy)
  35    31-Aug-01    RMS     Changed int64 to t_int64 for Windoze
  36    17-Jul-01    RMS     Moved function prototype
  37    04-Jul-01    RMS     Added DZ11 support
  38 */
  39
  40 #include "pdp10_defs.h"
  41 #include <time.h>
  42
  43 /* Invariants */
  44
  45 #define TIM_HW_FREQ     4100000                         /* 4.1Mhz */
  46 #define TIM_HWRE_MASK   07777
  47 #define UNIT_V_Y2K      (UNIT_V_UF + 0)                 /* Y2K compliant OS */
  48 #define UNIT_Y2K        (1u << UNIT_V_Y2K)
  49
  50 /* Clock mode TOPS-10/ITS */
  51
  52 #define TIM_TPS_T10     60
  53 #define TIM_WAIT_T10    8000
  54 #define TIM_MULT_T10    1
  55 #define TIM_ITS_QUANT   (TIM_HW_FREQ / TIM_TPS_T10)
  56
  57 /* Clock mode TOPS-20/KLAD */
  58
  59 #define TIM_TPS_T20     1001
  60 #define TIM_WAIT_T20    500
  61 #define TIM_MULT_T20    16
  62
  63 /* Probability function for TOPS-20 idlelock */
  64
  65 #define PROB(x)         (((rand() * 100) / RAND_MAX) >= (x))
  66
  67 d10 tim_base[2] = { 0, 0 };                             /* 71b timebase */
  68 d10 tim_ttg = 0;                                        /* time to go */
  69 d10 tim_period = 0;                                     /* period */
  70 d10 quant = 0;                                          /* ITS quantum */
  71 int32 tim_mult = TIM_MULT_T10;                          /* tmxr poll mult */
  72 int32 tim_t20_prob = 33;                                /* TOPS-20 prob */
  73
  74 /* Exported variables */
  75
  76 int32 clk_tps = TIM_TPS_T10;                            /* clock ticks/sec */
  77 int32 tmr_poll = TIM_WAIT_T10;                          /* clock poll */
  78 int32 tmxr_poll = TIM_WAIT_T10 * TIM_MULT_T10;          /* term mux poll */
  79
  80 extern int32 apr_flg, pi_act;
  81 extern UNIT cpu_unit;
  82 extern d10 pcst;
  83 extern a10 pager_PC;
  84 extern int32 t20_idlelock;
  85
  86 DEVICE tim_dev;
  87 t_stat tcu_rd (int32 *data, int32 PA, int32 access);
  88 t_stat tim_svc (UNIT *uptr);
  89 t_stat tim_reset (DEVICE *dptr);
  90 void tim_incr_base (d10 *base, d10 incr);
  91
  92 extern d10 Read (a10 ea, int32 prv);
  93 extern d10 ReadM (a10 ea, int32 prv);
  94 extern void Write (a10 ea, d10 val, int32 prv);
  95 extern void WriteP (a10 ea, d10 val);
  96 extern int32 pi_eval (void);
  97 extern t_stat wr_nop (int32 data, int32 PA, int32 access);
  98
  99 /* TIM data structures
 100
 101    tim_dev      TIM device descriptor
 102    tim_unit     TIM unit descriptor
 103    tim_reg      TIM register list
 104 */
 105
 106 DIB tcu_dib = { IOBA_TCU, IOLN_TCU, &tcu_rd, &wr_nop, 0 };
 107
 108 UNIT tim_unit = { UDATA (&tim_svc, UNIT_IDLE, 0), TIM_WAIT_T10 };
 109
 110 REG tim_reg[] = {
 111     { BRDATA (TIMEBASE, tim_base, 8, 36, 2) },
 112     { ORDATA (TTG, tim_ttg, 36) },
 113     { ORDATA (PERIOD, tim_period, 36) },
 114     { ORDATA (QUANT, quant, 36) },
 115     { DRDATA (TIME, tim_unit.wait, 24), REG_NZ + PV_LEFT },
 116     { DRDATA (PROB, tim_t20_prob, 6), REG_NZ + PV_LEFT + REG_HIDDEN },
 117     { DRDATA (POLL, tmr_poll, 32), REG_HRO + PV_LEFT },
 118     { DRDATA (MUXPOLL, tmxr_poll, 32), REG_HRO + PV_LEFT },
 119     { DRDATA (MULT, tim_mult, 6), REG_HRO + PV_LEFT },
 120     { DRDATA (TPS, clk_tps, 12), REG_HRO + PV_LEFT },
 121     { NULL }
 122     };
 123
 124 MTAB tim_mod[] = {
 125     { UNIT_Y2K, 0, "non Y2K OS", "NOY2K", NULL },
 126     { UNIT_Y2K, UNIT_Y2K, "Y2K OS", "Y2K", NULL },
 127     { MTAB_XTD|MTAB_VDV, 000, "ADDRESS", NULL,
 128       NULL, &show_addr, NULL },
 129     { 0 }
 130     };
 131
 132 DEVICE tim_dev = {
 133     "TIM", &tim_unit, tim_reg, tim_mod,
 134     1, 0, 0, 0, 0, 0,
 135     NULL, NULL, &tim_reset,
 136     NULL, NULL, NULL,
 137     &tcu_dib, DEV_UBUS
 138     };
 139
 140 /* Timer instructions */
 141
 142 /* Timer - if the timer is running at less than hardware frequency,
 143    need to interpolate the value by calculating how much of the current
 144    clock tick has elapsed, and what that equates to in msec. */
 145
 146 t_bool rdtim (a10 ea, int32 prv)
 147 {
 148 d10 tempbase[2];
 149
 150 ReadM (INCA (ea), prv);                                 /* check 2nd word */
 151 tempbase[0] = tim_base[0];                              /* copy time base */
 152 tempbase[1] = tim_base[1];
 153 if (tim_mult != TIM_MULT_T20) {                         /* interpolate? */
 154     int32 used;
 155     d10 incr;
 156     used = tmr_poll - (sim_is_active (&tim_unit) - 1);
 157     incr = (d10) (((double) used * TIM_HW_FREQ) /
 158         ((double) tmr_poll * (double) clk_tps));
 159     tim_incr_base (tempbase, incr);
 160     }
 161 tempbase[0] = tempbase[0] & ~((d10) TIM_HWRE_MASK);     /* clear low 12b */
 162 Write (ea, tempbase[0], prv);
 163 Write (INCA(ea), tempbase[1], prv);
 164 return FALSE;
 165 }
 166
 167 t_bool wrtim (a10 ea, int32 prv)
 168 {
 169 tim_base[0] = Read (ea, prv);
 170 tim_base[1] = CLRS (Read (INCA (ea), prv));
 171 return FALSE;
 172 }
 173
 174 t_bool rdint (a10 ea, int32 prv)
 175 {
 176 Write (ea, tim_period, prv);
 177 return FALSE;
 178 }
 179
 180 t_bool wrint (a10 ea, int32 prv)
 181 {
 182 tim_period = Read (ea, prv);
 183 tim_ttg = tim_period;
 184 return FALSE;
 185 }
 186
 187 /* Timer service - the timer is only serviced when the 'ttg' register
 188    has reached 0 based on the expected frequency of clock interrupts. */
 189
 190 t_stat tim_svc (UNIT *uptr)
 191 {
 192 if (cpu_unit.flags & UNIT_KLAD)                         /* diags? */
 193     tmr_poll = uptr->wait;                              /* fixed clock */
 194 else tmr_poll = sim_rtc_calb (clk_tps);                 /* else calibrate */
 195 sim_activate (uptr, tmr_poll);                          /* reactivate unit */
 196 tmxr_poll = tmr_poll * tim_mult;                        /* set mux poll */
 197 tim_incr_base (tim_base, tim_period);                   /* incr time base */
 198 tim_ttg = tim_period;                                   /* reload */
 199 apr_flg = apr_flg | APRF_TIM;                           /* request interrupt */
 200 if (Q_ITS) {                                            /* ITS? */
 201     if (pi_act == 0)
 202         quant = (quant + TIM_ITS_QUANT) & DMASK;
 203     if (TSTS (pcst)) {                                  /* PC sampling? */
 204         WriteP ((a10) pcst & AMASK, pager_PC);          /* store sample */
 205         pcst = AOB (pcst);                              /* add 1,,1 */
 206         }
 207     }                                                   /* end ITS */
 208 else if (t20_idlelock && PROB (100 - tim_t20_prob))
 209     t20_idlelock = 0;
 210 return SCPE_OK;
 211 }
 212
 213 /* Clock coscheduling routine */
 214
 215 int32 clk_cosched (int32 wait)
 216 {
 217 int32 t;
 218
 219 if (tim_mult == TIM_MULT_T20) return wait;
 220 t = sim_is_active (&tim_unit);
 221 return (t? t - 1: wait);
 222 }
 223
 224 void tim_incr_base (d10 *base, d10 incr)
 225 {
 226 base[1] = base[1] + incr;                               /* add on incr */
 227 base[0] = base[0] + (base[1] >> 35);                    /* carry to high */
 228 base[0] = base[0] & DMASK;                              /* mask high */
 229 base[1] = base[1] & MMASK;                              /* mask low */
 230 return;
 231 }
 232
 233 /* Timer reset */
 234
 235 t_stat tim_reset (DEVICE *dptr)
 236 {
 237 tim_period = 0;                                         /* clear timer */
 238 tim_ttg = 0;
 239 apr_flg = apr_flg & ~APRF_TIM;                          /* clear interrupt */
 240 tmr_poll = sim_rtc_init (tim_unit.wait);                /* init timer */
 241 sim_activate_abs (&tim_unit, tmr_poll);                 /* activate unit */
 242 tmxr_poll = tmr_poll * tim_mult;                        /* set mux poll */
 243 return SCPE_OK;
 244 }
 245
 246 /* Set timer parameters from CPU model */
 247
 248 t_stat tim_set_mod (UNIT *uptr, int32 val, char *cptr, void *desc)
 249 {
 250 if (val & (UNIT_T20|UNIT_KLAD)) {
 251     clk_tps = TIM_TPS_T20;
 252     uptr->wait = TIM_WAIT_T20;
 253     tmr_poll = TIM_WAIT_T20;
 254     tim_mult = TIM_MULT_T20;
 255     uptr->flags = uptr->flags | UNIT_Y2K;
 256     }
 257 else {
 258     clk_tps = TIM_TPS_T10;
 259     uptr->wait = TIM_WAIT_T10;
 260     tmr_poll = TIM_WAIT_T10;
 261     tim_mult = TIM_MULT_T10;
 262     if (Q_ITS) uptr->flags = uptr->flags | UNIT_Y2K;
 263     else uptr->flags = uptr->flags & ~UNIT_Y2K;
 264     }
 265 tmxr_poll = tmr_poll * tim_mult;
 266 return SCPE_OK;
 267 }
 268
 269 /* Time of year clock */
 270
 271 t_stat tcu_rd (int32 *data, int32 PA, int32 access)
 272 {
 273 time_t curtim;
 274 struct tm *tptr;
 275
 276 curtim = time (NULL);                                   /* get time */
 277 tptr = localtime (&curtim);                             /* decompose */
 278 if (tptr == NULL) return SCPE_NXM;                      /* Y2K prob? */
 279 if ((tptr->tm_year > 99) && !(tim_unit.flags & UNIT_Y2K))
 280     tptr->tm_year = 99;
 281
 282 switch ((PA >> 1) & 03) {                               /* decode PA<3:1> */
 283
 284     case 0:                                             /* year/month/day */
 285         *data = (((tptr->tm_year) & 0177) << 9) |
 286                 (((tptr->tm_mon + 1) & 017) << 5) |
 287                 ((tptr->tm_mday) & 037);
 288         return SCPE_OK;
 289
 290     case 1:                                             /* hour/minute */
 291         *data = (((tptr->tm_hour) & 037) << 8) |
 292                 ((tptr->tm_min) & 077);
 293         return SCPE_OK;
 294
 295     case 2:                                             /* second */
 296         *data = (tptr->tm_sec) & 077;
 297         return SCPE_OK;
 298
 299     case 3:                                             /* status */
 300         *data = CSR_DONE;
 301         return SCPE_OK;
 302         }
 303
 304 return SCPE_NXM;                                        /* can't get here */
 305 }