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First Commit of my working state
[simh.git] / PDP11 / pdp11_cpumod.c
1 /* pdp11_cpumod.c: PDP-11 CPU model-specific features
2
3 Copyright (c) 2004-2008, Robert M Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 system PDP-11 model-specific registers
27
28 20-May-08 RMS Added JCSR default for KDJ11B, KDJ11E
29 22-Apr-08 RMS Fixed write behavior of 11/70 MBRK, LOSIZE, HISIZE
30 (found by Walter Mueller)
31 29-Apr-07 RMS Don't run bus setup routine during RESTORE
32 30-Aug-05 RMS Added additional 11/60 registers
33 16-Aug-05 RMS Fixed C++ declaration and cast problems
34 15-Feb-05 RMS Fixed bug in SHOW MODEL (from Sergey Okhapkin)
35 19-Jan-05 RMS Added variable SYSID, MBRK write (from Tim Chapman)
36
37 This module includes CPU- and system-specific registers, such as the Unibus
38 map and control registers on 22b Unibus systems, the board registers for the
39 F11- and J11-based systems, and the system registers for the PDP-11/44,
40 PDP-11/45, PDP-11/60, and PDP-11/70. Most registers are implemented at
41 a minimum level: just enough to satisfy the machine identification code
42 in the various operating systems.
43 */
44
45 #include "pdp11_defs.h"
46 #include "pdp11_cpumod.h"
47 #include <time.h>
48
49 /* Byte write macros for system registers */
50
51 #define ODD_IGN(cur) \
52 if ((access == WRITEB) && (pa & 1)) return SCPE_OK
53 #define ODD_WO(cur) \
54 if ((access == WRITEB) && (pa & 1)) cur = cur << 8
55 #define ODD_MRG(prv,cur) \
56 if (access == WRITEB) cur = \
57 ((pa & 1)? (((prv) & 0377) | ((cur) & 0177400)) : \
58 (((prv) & 0177400) | ((cur) & 0377)))
59
60 int32 SR = 0; /* switch register */
61 int32 DR = 0; /* display register */
62 int32 MBRK = 0; /* 11/70 microbreak */
63 int32 SYSID = 0x1234; /* 11/70 system ID */
64 int32 WCS = 0; /* 11/60 WCS control */
65 int32 CPUERR = 0; /* CPU error reg */
66 int32 MEMERR = 0; /* memory error reg */
67 int32 CCR = 0; /* cache control reg */
68 int32 HITMISS = 0; /* hit/miss reg */
69 int32 MAINT = 0; /* maint reg */
70 int32 JCSR = 0; /* J11 control */
71 int32 JCSR_dflt = 0; /* J11 boot ctl def */
72 int32 JPCR = 0; /* J11 page ctrl */
73 int32 JASR = 0; /* J11 addtl status */
74 int32 UDCR = 0; /* UBA diag ctrl */
75 int32 UDDR = 0; /* UBA diag data */
76 int32 UCSR = 0; /* UBA control */
77 int32 uba_last = 0; /* UBA last mapped */
78 int32 ub_map[UBM_LNT_LW] = { 0 }; /* UBA map array */
79 int32 toy_state = 0;
80 uint8 toy_data[TOY_LNT] = { 0 };
81 static int32 clk_tps_map[4] = { 60, 60, 50, 800 };
82
83 extern uint16 *M;
84 extern int32 R[8];
85 extern DEVICE cpu_dev, *sim_devices[];
86 extern UNIT cpu_unit;
87 extern FILE *sim_log;
88 extern int32 STKLIM, PIRQ;
89 extern uint32 cpu_model, cpu_type, cpu_opt;
90 extern int32 clk_fie, clk_fnxm, clk_tps, clk_default;
91 extern int32 sim_switches;
92
93 t_stat CPU24_rd (int32 *data, int32 addr, int32 access);
94 t_stat CPU24_wr (int32 data, int32 addr, int32 access);
95 t_stat CPU44_rd (int32 *data, int32 addr, int32 access);
96 t_stat CPU44_wr (int32 data, int32 addr, int32 access);
97 t_stat CPU45_rd (int32 *data, int32 addr, int32 access);
98 t_stat CPU45_wr (int32 data, int32 addr, int32 access);
99 t_stat CPU60_rd (int32 *data, int32 addr, int32 access);
100 t_stat CPU60_wr (int32 data, int32 addr, int32 access);
101 t_stat CPU70_rd (int32 *data, int32 addr, int32 access);
102 t_stat CPU70_wr (int32 data, int32 addr, int32 access);
103 t_stat CPUJ_rd (int32 *data, int32 addr, int32 access);
104 t_stat CPUJ_wr (int32 data, int32 addr, int32 access);
105 t_stat REG_rd (int32 *data, int32 addr, int32 access);
106 t_stat REG_wr (int32 data, int32 addr, int32 access);
107 t_stat SR_rd (int32 *data, int32 addr, int32 access);
108 t_stat DR_wr (int32 data, int32 addr, int32 access);
109 t_stat CTLFB_rd (int32 *data, int32 addr, int32 access);
110 t_stat CTLFB_wr (int32 data, int32 addr, int32 access);
111 t_stat CTLJB_rd (int32 *data, int32 addr, int32 access);
112 t_stat CTLJB_wr (int32 data, int32 addr, int32 access);
113 t_stat CTLJD_rd (int32 *data, int32 addr, int32 access);
114 t_stat CTLJD_wr (int32 data, int32 addr, int32 access);
115 t_stat CTLJE_rd (int32 *data, int32 addr, int32 access);
116 t_stat CTLJE_wr (int32 data, int32 addr, int32 access);
117 t_stat UBA24_rd (int32 *data, int32 addr, int32 access);
118 t_stat UBA24_wr (int32 data, int32 addr, int32 access);
119 t_stat UBAJ_rd (int32 *data, int32 addr, int32 access);
120 t_stat UBAJ_wr (int32 data, int32 addr, int32 access);
121 t_stat sys_reset (DEVICE *dptr);
122 int32 toy_read (void);
123 void toy_write (int32 bit);
124 uint8 toy_set (int32 val);
125 t_stat sys_set_jclk_dflt (UNIT *uptr, int32 val, char *cptr, void *desc);
126 t_stat sys_show_jclk_dflt (FILE *st, UNIT *uptr, int32 val, void *desc);
127
128 extern t_stat PSW_rd (int32 *data, int32 addr, int32 access);
129 extern t_stat PSW_wr (int32 data, int32 addr, int32 access);
130 extern t_stat APR_rd (int32 *data, int32 addr, int32 access);
131 extern t_stat APR_wr (int32 data, int32 addr, int32 access);
132 extern t_stat MMR012_rd (int32 *data, int32 addr, int32 access);
133 extern t_stat MMR012_wr (int32 data, int32 addr, int32 access);
134 extern t_stat MMR3_rd (int32 *data, int32 addr, int32 access);
135 extern t_stat MMR3_wr (int32 data, int32 addr, int32 access);
136 extern t_stat ubm_rd (int32 *data, int32 addr, int32 access);
137 extern t_stat ubm_wr (int32 data, int32 addr, int32 access);
138 extern void put_PIRQ (int32 val);
139
140 /* Fixed I/O address table entries */
141
142 DIB psw_dib = { IOBA_PSW, IOLN_PSW, &PSW_rd, &PSW_wr, 0 };
143 DIB cpuj_dib = { IOBA_CPU, IOLN_CPU, &CPUJ_rd, &CPUJ_wr, 0 };
144 DIB cpu24_dib = { IOBA_CPU, IOLN_CPU, &CPU24_rd, &CPU24_wr, 0 };
145 DIB cpu44_dib = { IOBA_CPU, IOLN_CPU, &CPU44_rd, &CPU44_wr, 0 };
146 DIB cpu45_dib = { IOBA_CPU, IOLN_CPU, &CPU45_rd, &CPU45_wr, 0 };
147 DIB cpu60_dib = { IOBA_CPU, IOLN_CPU, &CPU60_rd, &CPU60_wr, 0 };
148 DIB cpu70_dib = { IOBA_CPU, IOLN_CPU, &CPU70_rd, &CPU70_wr, 0 };
149 DIB reg_dib = { IOBA_GPR, IOLN_GPR, &REG_rd, &REG_wr, 0 };
150 DIB ctlfb_dib = { IOBA_CTL, IOLN_CTL, &CTLFB_rd, &CTLFB_wr };
151 DIB ctljb_dib = { IOBA_CTL, IOLN_CTL, &CTLJB_rd, &CTLJB_wr };
152 DIB ctljd_dib = { IOBA_CTL, IOLN_CTL, &CTLJD_rd, &CTLJD_wr };
153 DIB ctlje_dib = { IOBA_CTL, IOLN_CTL, &CTLJE_rd, &CTLJE_wr };
154 DIB uba24_dib = { IOBA_UCTL, IOLN_UCTL, &UBA24_rd, &UBA24_wr };
155 DIB ubaj_dib = {IOBA_UCTL, IOLN_UCTL, &UBAJ_rd, &UBAJ_wr };
156 DIB supv_dib = { IOBA_SUP, IOLN_SUP, &APR_rd, &APR_wr, 0 };
157 DIB kipdr_dib = { IOBA_KIPDR, IOLN_KIPDR, &APR_rd, &APR_wr, 0 };
158 DIB kdpdr_dib = { IOBA_KDPDR, IOLN_KDPDR, &APR_rd, &APR_wr, 0 };
159 DIB kipar_dib = { IOBA_KIPAR, IOLN_KIPAR, &APR_rd, &APR_wr, 0 };
160 DIB kdpar_dib = { IOBA_KDPAR, IOLN_KDPAR, &APR_rd, &APR_wr, 0 };
161 DIB uipdr_dib = { IOBA_UIPDR, IOLN_UIPDR, &APR_rd, &APR_wr, 0 };
162 DIB udpdr_dib = { IOBA_UDPDR, IOLN_UDPDR, &APR_rd, &APR_wr, 0 };
163 DIB uipar_dib = { IOBA_UIPAR, IOLN_UIPAR, &APR_rd, &APR_wr, 0 };
164 DIB udpar_dib = { IOBA_UDPAR, IOLN_UDPAR, &APR_rd, &APR_wr, 0 };
165 DIB sr_dib = { IOBA_SR, IOLN_SR, &SR_rd, NULL, 0 };
166 DIB dr_dib = { IOBA_SR, IOLN_SR, NULL, &DR_wr, 0 };
167 DIB mmr012_dib = { IOBA_MMR012, IOLN_MMR012, &MMR012_rd, &MMR012_wr, 0 };
168 DIB mmr3_dib = { IOBA_MMR3, IOLN_MMR3, &MMR3_rd, &MMR3_wr, 0 };
169 DIB ubm_dib = { IOBA_UBM, IOLN_UBM, &ubm_rd, &ubm_wr, 0 };
170
171 CPUTAB cpu_tab[MOD_MAX] = {
172 { "11/03", SOP_1103, OPT_1103, MEMSIZE64K, PSW_1103,
173 0, 0, 0, 0, 0 },
174 { "11/04", SOP_1104, OPT_1104, MEMSIZE64K, PSW_1104,
175 0, 0, 0, 0, 0 },
176 { "11/05", SOP_1105, OPT_1105, MEMSIZE64K, PSW_1105,
177 0, 0, 0, 0, 0 },
178 { "11/20", SOP_1120, OPT_1120, MEMSIZE64K, PSW_1120,
179 0, 0, 0, 0, 0 },
180 { "11/23", SOP_1123, OPT_1123, MAXMEMSIZE, PSW_F,
181 MFPT_F, PAR_F, PDR_F, MM0_F, MM3_F },
182 { "11/23+", SOP_1123P, OPT_1123P, MAXMEMSIZE, PSW_F,
183 MFPT_F, PAR_F, PDR_F, MM0_F, MM3_F },
184 { "11/24", SOP_1124, OPT_1124, MAXMEMSIZE, PSW_F,
185 MFPT_F, PAR_F, PDR_F, MM0_F, MM3_F },
186 { "11/34", SOP_1134, OPT_1134, UNIMEMSIZE, PSW_1134,
187 0, PAR_1134, PDR_1134, MM0_1134, 0 },
188 { "11/40", SOP_1140, OPT_1140, UNIMEMSIZE, PSW_1140,
189 0, PAR_1140, PDR_1140, MM0_1140, 0 },
190 { "11/44", SOP_1144, OPT_1144, MAXMEMSIZE, PSW_1144,
191 MFPT_44, PAR_1144, PDR_1144, MM0_1144, MM3_1144 },
192 { "11/45", SOP_1145, OPT_1145, UNIMEMSIZE, PSW_1145,
193 0, PAR_1145, PDR_1145, MM0_1145, MM3_1145 },
194 { "11/60", SOP_1160, OPT_1160, UNIMEMSIZE, PSW_1160,
195 0, PAR_1160, PDR_1160, MM0_1160, 0 },
196 { "11/70", SOP_1170, OPT_1170, MAXMEMSIZE, PSW_1170,
197 0, PAR_1170, PDR_1170, MM0_1170, MM3_1170 },
198 { "11/73", SOP_1173, OPT_1173, MAXMEMSIZE, PSW_J,
199 MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },
200 { "11/53", SOP_1153, OPT_1153, MAXMEMSIZE, PSW_J,
201 MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },
202 { "11/73B", SOP_1173B, OPT_1173B, MAXMEMSIZE, PSW_J,
203 MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },
204 { "11/83", SOP_1183, OPT_1183, MAXMEMSIZE, PSW_J,
205 MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },
206 { "11/84", SOP_1184, OPT_1184, MAXMEMSIZE, PSW_J,
207 MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },
208 { "11/93", SOP_1193, OPT_1193, MAXMEMSIZE, PSW_J,
209 MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },
210 { "11/94", SOP_1194, OPT_1194, MAXMEMSIZE, PSW_J,
211 MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J }
212 };
213
214 CNFTAB cnf_tab[] = {
215 { HAS_PSW, 0, &psw_dib }, /* PSW */
216 { CPUT_J, 0, &cpuj_dib }, /* CPU control */
217 { CPUT_24, 0, &cpu24_dib },
218 { CPUT_44, 0, &cpu44_dib },
219 { CPUT_45, 0, &cpu45_dib },
220 { CPUT_60, 0, &cpu60_dib },
221 { CPUT_70, 0, &cpu70_dib },
222 { HAS_IOSR, 0, &reg_dib },
223 { CPUT_23P, 0, &ctlfb_dib }, /* board ctls */
224 { CPUT_JB, 0, &ctljb_dib },
225 { CPUT_53, 0, &ctljd_dib },
226 { CPUT_JE, 0, &ctlje_dib },
227 { CPUT_24, 0, &uba24_dib }, /* UBA */
228 { CPUT_JU, 0, &ubaj_dib },
229 { 0, OPT_MMU, &kipdr_dib }, /* MMU */
230 { 0, OPT_MMU, &kipar_dib },
231 { 0, OPT_MMU, &uipdr_dib },
232 { 0, OPT_MMU, &uipar_dib },
233 { 0, OPT_MMU, &mmr012_dib }, /* MMR0-2 */
234 { HAS_MMR3, 0, &mmr3_dib }, /* MMR3 */
235 { 0, OPT_UBM, &ubm_dib }, /* Unibus map */
236 { HAS_SID, 0, &kdpdr_dib }, /* supv, I/D */
237 { HAS_SID, 0, &kdpar_dib },
238 { HAS_SID, 0, &supv_dib },
239 { HAS_SID, 0, &udpdr_dib },
240 { HAS_SID, 0, &udpar_dib },
241 { HAS_SR, 0, &sr_dib }, /* SR */
242 { HAS_DR, 0, &dr_dib }, /* DR */
243 { 0, 0, NULL }
244 };
245
246 static const char *opt_name[] = {
247 "Unibus", "Qbus", "EIS", "NOEIS", "FIS", "NOFIS",
248 "FPP", "NOFPP", "CIS", "NOCIS", "MMU", "NOMMU",
249 "RH11", "RH70", "PARITY", "NOPARITY", "Unibus map", "No map", NULL
250 };
251
252 static const char *jcsr_val[4] = {
253 "LINE", "50HZ", "60HZ", "800HZ"
254 };
255
256 /* SYSTEM data structures
257
258 sys_dev SYSTEM device descriptor
259 sys_unit SYSTEM unit descriptor
260 sys_reg SYSTEM register list
261 */
262
263 UNIT sys_unit = { UDATA (NULL, 0, 0) };
264
265 REG sys_reg[] = {
266 { ORDATA (SR, SR, 16) },
267 { ORDATA (DR, DR, 16) },
268 { ORDATA (MEMERR, MEMERR, 16) },
269 { ORDATA (CCR, CCR, 16) },
270 { ORDATA (MAINT, MAINT, 16) },
271 { ORDATA (HITMISS, HITMISS, 16) },
272 { ORDATA (CPUERR, CPUERR, 16) },
273 { ORDATA (MBRK, MBRK, 16) },
274 { ORDATA (WCS, WCS, 16) },
275 { ORDATA (SYSID, SYSID, 16) },
276 { ORDATA (JCSR, JCSR, 16) },
277 { ORDATA (JCSR_DFLT, JCSR_dflt, 16), REG_HRO },
278 { ORDATA (JPCR, JPCR, 16) },
279 { ORDATA (JASR, JASR, 16) },
280 { ORDATA (UDCR, UDCR, 16) },
281 { ORDATA (UDDR, UDDR, 16) },
282 { ORDATA (UCSR, UCSR, 16) },
283 { ORDATA (ULAST, uba_last, 23) },
284 { BRDATA (UBMAP, ub_map, 8, 22, UBM_LNT_LW) },
285 { DRDATA (TOY_STATE, toy_state, 6), REG_HRO },
286 { BRDATA (TOY_DATA, toy_data, 8, 8, TOY_LNT), REG_HRO },
287 { NULL}
288 };
289
290 MTAB sys_mod[] = {
291 { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "JCLK_DFLT", "JCLK_DFLT",
292 &sys_set_jclk_dflt, &sys_show_jclk_dflt },
293 { 0 }
294 };
295
296 DEVICE sys_dev = {
297 "SYSTEM", &sys_unit, sys_reg, sys_mod,
298 1, 0, 0, 0, 0, 0,
299 NULL, NULL, &sys_reset,
300 NULL, NULL, NULL,
301 NULL, 0, 0,
302 NULL, NULL, NULL
303 };
304
305 /* Switch and display registers - many */
306
307 t_stat SR_rd (int32 *data, int32 pa, int32 access)
308 {
309 *data = SR;
310 return SCPE_OK;
311 }
312
313 t_stat DR_wr (int32 data, int32 pa, int32 access)
314 {
315 DR = data;
316 return SCPE_OK;
317 }
318
319 /* GPR's - 11/04, 11/05 */
320
321 t_stat REG_rd (int32 *data, int32 pa, int32 access)
322 {
323 *data = R[pa & 07];
324 return SCPE_OK;
325 }
326
327 t_stat REG_wr (int32 data, int32 pa, int32 access)
328 {
329 int32 reg = pa & 07;
330
331 if (access == WRITE) R[reg] = data;
332 else if (pa & 1) R[reg] = (R[reg] & 0377) | (data << 8);
333 else R[reg] = (R[reg] & ~0377) | data;
334 return SCPE_OK;
335 }
336
337 /* CPU control registers - 11/24 */
338
339 t_stat CPU24_rd (int32 *data, int32 pa, int32 access)
340 {
341 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
342
343 case 013: /* CPUERR */
344 *data = 0;
345 return SCPE_OK;
346 } /* end switch PA */
347
348 *data = 0;
349 return SCPE_NXM; /* unimplemented */
350 }
351
352 t_stat CPU24_wr (int32 data, int32 pa, int32 access)
353 {
354 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
355
356 case 013: /* CPUERR */
357 return SCPE_OK;
358 } /* end switch pa */
359
360 return SCPE_NXM; /* unimplemented */
361 }
362
363 /* CPU control registers - 11/44 */
364
365 t_stat CPU44_rd (int32 *data, int32 pa, int32 access)
366 {
367 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
368
369 case 002: /* MEMERR */
370 *data = MEMERR;
371 return SCPE_OK;
372
373 case 003: /* CCR */
374 *data = CCR & CCR44_RD;
375 return SCPE_OK;
376
377 case 004: /* MAINT */
378 *data = MAINT & CMR44_RD;
379 return SCPE_OK;
380
381 case 005: /* Hit/miss */
382 *data = HITMISS;
383 return SCPE_OK;
384
385 case 006: /* CDR */
386 *data = 0;
387 return SCPE_OK;
388
389 case 013: /* CPUERR */
390 if (CPUERR & CPUE_YEL) /* 11/44 stack err */
391 CPUERR = (CPUERR & ~CPUE_YEL) | CPUE_RED; /* in <2> not <3> */
392 if (CPUERR & (CPUE_ODD|CPUE_NXM|CPUE_TMO)) /* additional flag */
393 CPUERR = CPUERR | CPUE44_BUSE;
394 *data = CPUERR & CPUE_IMP;
395 return SCPE_OK;
396
397 case 015: /* PIRQ */
398 *data = PIRQ;
399 return SCPE_OK;
400 } /* end switch PA */
401
402 *data = 0;
403 return SCPE_NXM; /* unimplemented */
404 }
405
406 t_stat CPU44_wr (int32 data, int32 pa, int32 access)
407 {
408 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
409
410 case 002: /* MEMERR */
411 MEMERR = 0;
412 return SCPE_OK;
413
414 case 003: /* CCR */
415 ODD_MRG (CCR, data);
416 CCR = data & CCR44_WR;
417 return SCPE_OK;
418
419 case 004: /* MAINT */
420 ODD_MRG (MAINT, data);
421 MAINT = data & CMR44_WR;
422 return SCPE_OK;
423
424 case 005: /* Hit/miss */
425 return SCPE_OK;
426
427 case 013: /* CPUERR */
428 CPUERR = 0;
429 return SCPE_OK;
430
431 case 015: /* PIRQ */
432 ODD_WO (data);
433 put_PIRQ (data);
434 return SCPE_OK;
435 }
436
437 return SCPE_NXM; /* unimplemented */
438 }
439
440 /* CPU control registers - 11/45 */
441
442 t_stat CPU45_rd (int32 *data, int32 pa, int32 access)
443 {
444 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
445
446 case 014: /* MBRK */
447 *data = MBRK;
448 return SCPE_OK;
449
450 case 015: /* PIRQ */
451 *data = PIRQ;
452 return SCPE_OK;
453
454 case 016: /* STKLIM */
455 *data = STKLIM & STKLIM_RW;
456 return SCPE_OK;
457 } /* end switch PA */
458
459 *data = 0;
460 return SCPE_NXM; /* unimplemented */
461 }
462
463 t_stat CPU45_wr (int32 data, int32 pa, int32 access)
464 {
465 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
466
467 case 015: /* PIRQ */
468 ODD_WO (data);
469 put_PIRQ (data);
470 return SCPE_OK;
471
472 case 016: /* STKLIM */
473 ODD_WO (data);
474 STKLIM = data & STKLIM_RW;
475 return SCPE_OK;
476 } /* end switch pa */
477
478 return SCPE_NXM; /* unimplemented */
479 }
480
481 /* CPU control registers - 11/60 */
482
483 t_stat CPU60_rd (int32 *data, int32 pa, int32 access)
484 {
485 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
486
487 case 000: /* WCS */
488 *data = WCS & WCS60_RD;
489 return SCPE_OK;
490
491 case 002: /* MEMERR */
492 *data = MEMERR & MEME60_RD;
493 return SCPE_OK;
494
495 case 003: /* CCR */
496 *data = CCR & CCR60_RD;
497 return SCPE_OK;
498
499 case 005: /* Hit/miss */
500 *data = HITMISS;
501 return SCPE_OK;
502
503 case 013: /* CPUERR */
504 if (CPUERR & CPUE_NXM) /* TMO only */
505 CPUERR = (CPUERR & ~CPUE_NXM) | CPUE_TMO;
506 *data = CPUERR & CPUE60_RD;
507 return SCPE_OK;
508
509 case 016: /* STKLIM */
510 *data = STKLIM & STKLIM_RW;
511 return SCPE_OK;
512 } /* end switch PA */
513
514 *data = 0;
515 return SCPE_NXM; /* unimplemented */
516 }
517
518 t_stat CPU60_wr (int32 data, int32 pa, int32 access)
519 {
520 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
521
522 case 000: /* WCS */
523 WCS = data & WCS60_WR;
524 return SCPE_OK;
525
526 case 002: /* MEMERR */
527 MEMERR = 0;
528 return SCPE_OK;
529
530 case 003: /* CCR */
531 ODD_IGN (data);
532 CCR = data & CCR60_WR;
533 return SCPE_OK;
534
535 case 005: /* Hit/miss */
536 return SCPE_OK;
537
538 case 013: /* CPUERR */
539 CPUERR = 0;
540 return SCPE_OK;
541
542 case 014: /* MBRK */
543 MBRK = data & MBRK60_WR;
544 return SCPE_OK;
545
546 case 016: /* STKLIM */
547 ODD_WO (data);
548 STKLIM = data & STKLIM_RW;
549 return SCPE_OK;
550 } /* end switch pa */
551
552 return SCPE_NXM; /* unimplemented */
553 }
554
555 /* CPU control registers - 11/70 */
556
557 t_stat CPU70_rd (int32 *data, int32 pa, int32 access)
558 {
559 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
560
561 case 000: /* low error */
562 *data = 0;
563 return SCPE_OK;
564
565 case 001: /* high error */
566 *data = 0;
567 return SCPE_OK;
568
569 case 002: /* MEMERR */
570 *data = MEMERR;
571 return SCPE_OK;
572
573 case 003: /* CCR */
574 *data = CCR;
575 return SCPE_OK;
576
577 case 004: /* MAINT */
578 *data = 0;
579 return SCPE_OK;
580
581 case 005: /* Hit/miss */
582 *data = HITMISS;
583 return SCPE_OK;
584
585 case 010: /* low size */
586 *data = (MEMSIZE >> 6) - 1;
587 return SCPE_OK;
588
589 case 011: /* high size */
590 *data = 0;
591 return SCPE_OK;
592
593 case 012: /* system ID */
594 *data = SYSID;
595 return SCPE_OK;
596
597 case 013: /* CPUERR */
598 *data = CPUERR & CPUE_IMP;
599 return SCPE_OK;
600
601 case 014: /* MBRK */
602 *data = MBRK;
603 return SCPE_OK;
604
605 case 015: /* PIRQ */
606 *data = PIRQ;
607 return SCPE_OK;
608
609 case 016: /* STKLIM */
610 *data = STKLIM & STKLIM_RW;
611 return SCPE_OK;
612 } /* end switch PA */
613
614 *data = 0;
615 return SCPE_NXM; /* unimplemented */
616 }
617
618 t_stat CPU70_wr (int32 data, int32 pa, int32 access)
619 {
620 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
621
622 case 002: /* MEMERR */
623 ODD_WO (data);
624 MEMERR = MEMERR & ~data;
625 return SCPE_OK;
626
627 case 003: /* CCR */
628 ODD_MRG (CCR, data);
629 CCR = data;
630 return SCPE_OK;
631
632 case 004: /* MAINT */
633 return SCPE_OK;
634
635 case 005: /* Hit/miss */
636 return SCPE_OK;
637
638 case 010: /* low size */
639 return SCPE_OK;
640
641 case 011: /* high size */
642 return SCPE_OK;
643
644 case 013: /* CPUERR */
645 CPUERR = 0;
646 return SCPE_OK;
647
648 case 014: /* MBRK */
649 ODD_IGN (data);
650 MBRK = data & MBRK70_WR;
651 return SCPE_OK;
652
653 case 015: /* PIRQ */
654 ODD_WO (data);
655 put_PIRQ (data);
656 return SCPE_OK;
657
658 case 016: /* STKLIM */
659 ODD_WO (data);
660 STKLIM = data & STKLIM_RW;
661 return SCPE_OK;
662 } /* end switch pa */
663
664 return SCPE_NXM; /* unimplemented */
665 }
666
667 /* CPU control registers - J11 */
668
669 t_stat CPUJ_rd (int32 *data, int32 pa, int32 access)
670 {
671 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
672
673 case 002: /* MEMERR */
674 *data = MEMERR;
675 return SCPE_OK;
676
677 case 003: /* CCR */
678 *data = CCR;
679 return SCPE_OK;
680
681 case 004: /* MAINT */
682 *data = MAINT | MAINT_NOFPA | MAINT_BPOK | (UNIBUS? MAINT_U: MAINT_Q);
683 if (CPUT (CPUT_53)) *data |= MAINT_KDJD | MAINT_POROM;
684 if (CPUT (CPUT_73)) *data |= MAINT_KDJA | MAINT_POODT;
685 if (CPUT (CPUT_73B|CPUT_83|CPUT_84)) *data |= MAINT_KDJB | MAINT_POROM;
686 if (CPUT (CPUT_93|CPUT_94)) *data |= MAINT_KDJE | MAINT_POROM;
687 return SCPE_OK;
688
689 case 005: /* Hit/miss */
690 if (CPUT (CPUT_73B)) *data = 0; /* must be 0 for 73B */
691 else *data = HITMISS | 010; /* must be nz for 11/8X */
692 return SCPE_OK;
693
694 case 013: /* CPUERR */
695 *data = CPUERR & CPUE_IMP;
696 return SCPE_OK;
697
698 case 015: /* PIRQ */
699 *data = PIRQ;
700 return SCPE_OK;
701 } /* end switch PA */
702
703 *data = 0;
704 return SCPE_NXM; /* unimplemented */
705 }
706
707 t_stat CPUJ_wr (int32 data, int32 pa, int32 access)
708 {
709 switch ((pa >> 1) & 017) { /* decode pa<4:1> */
710
711 case 002: /* MEMERR */
712 MEMERR = 0;
713 return SCPE_OK;
714
715 case 003: /* CCR */
716 ODD_MRG (CCR, data);
717 CCR = data;
718 return SCPE_OK;
719
720 case 004: /* MAINT */
721 return SCPE_OK;
722
723 case 005: /* Hit/miss */
724 return SCPE_OK;
725
726 case 013: /* CPUERR */
727 CPUERR = 0;
728 return SCPE_OK;
729
730 case 015: /* PIRQ */
731 ODD_WO (data);
732 put_PIRQ (data);
733 return SCPE_OK;
734 } /* end switch pa */
735
736 return SCPE_NXM; /* unimplemented */
737 }
738
739 /* Board control registers - KDF11B */
740
741 t_stat CTLFB_rd (int32 *data, int32 pa, int32 access)
742 {
743 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
744
745 case 0: /* PCR */
746 *data = JPCR & PCRFB_RW;
747 return SCPE_OK;
748
749 case 1: /* MAINT */
750 *data = MAINT;
751 return SCPE_OK;
752
753 case 2: /* CDR */
754 *data = SR & CDRFB_RD;
755 return SCPE_OK;
756 }
757
758 *data = 0;
759 return SCPE_NXM;
760 }
761
762 t_stat CTLFB_wr (int32 data, int32 pa, int32 access)
763 {
764 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
765
766 case 0: /* PCR */
767 ODD_MRG (JPCR, data);
768 JPCR = data & PCRFB_RW;
769 return SCPE_OK;
770 case 1: /* MAINT */
771 ODD_MRG (MAINT, data);
772 MAINT = data;
773 return SCPE_OK;
774 case 2: /* CDR */
775 ODD_WO (data);
776 DR = data & CDRFB_WR;
777 return SCPE_OK;
778 }
779
780 return SCPE_NXM;
781 }
782
783 /* Board control registers - KDJ11B */
784
785 t_stat CTLJB_rd (int32 *data, int32 pa, int32 access)
786 {
787 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
788
789 case 0: /* CSR */
790 *data = JCSR & CSRJB_RD;
791 return SCPE_OK;
792
793 case 1: /* PCR */
794 *data = JPCR & PCRJB_RW;
795 return SCPE_OK;
796
797 case 2: /* CDR */
798 *data = SR & CDRJB_RD;
799 return SCPE_OK;
800 }
801
802 *data = 0;
803 return SCPE_NXM;
804 }
805
806 t_stat CTLJB_wr (int32 data, int32 pa, int32 access)
807 {
808 int32 t;
809
810 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
811
812 case 0: /* CSR */
813 ODD_MRG (JCSR, data);
814 JCSR = (JCSR & ~CSRJB_WR) | (data & CSRJB_WR);
815 if (JCSR & CSRJ_LTCI) clk_fie = 1; /* force LTC int enb? */
816 else clk_fie = 0;
817 if (JCSR & CSRJ_LTCD) clk_fnxm = 1; /* force LTC reg nxm? */
818 else clk_fnxm = 0;
819 t = CSRJ_LTCSEL (JCSR); /* get freq sel */
820 if (t) clk_tps = clk_tps_map[t];
821 else clk_tps = clk_default;
822 return SCPE_OK;
823
824 case 1: /* PCR */
825 ODD_MRG (JPCR, data);
826 JPCR = data & PCRJB_RW;
827 return SCPE_OK;
828
829 case 2: /* CDR */
830 ODD_WO (data);
831 DR = data & CDRJB_WR;
832 return SCPE_OK;
833 }
834
835 return SCPE_NXM;
836 }
837
838 /* Board control registers - KDJ11D */
839
840 t_stat CTLJD_rd (int32 *data, int32 pa, int32 access)
841 {
842 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
843
844 case 0: /* CSR */
845 *data = JCSR & CSRJD_RD;
846 return SCPE_OK;
847 }
848
849 *data = 0;
850 return SCPE_NXM;
851 }
852
853 t_stat CTLJD_wr (int32 data, int32 pa, int32 access)
854 {
855 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
856
857 case 0: /* CSR */
858 ODD_MRG (JCSR, data);
859 JCSR = (JCSR & ~CSRJD_WR) | (data & CSRJD_WR);
860 return SCPE_OK;
861 }
862
863 return SCPE_NXM;
864 }
865
866 /* Board control registers - KDJ11E */
867
868 t_stat CTLJE_rd (int32 *data, int32 pa, int32 access)
869 {
870 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
871
872 case 0: /* CSR */
873 *data = JCSR & CSRJE_RD;
874 return SCPE_OK;
875
876 case 1: /* PCR */
877 *data = JPCR & PCRJE_RW;
878 return SCPE_OK;
879
880 case 2: /* CDR */
881 *data = SR & CDRJE_RD;
882 return SCPE_OK;
883
884 case 3: /* ASR */
885 JASR = (JASR & ~ASRJE_TOY) | (toy_read () << ASRJE_V_TOY);
886 *data = JASR & ASRJE_RW;
887 return SCPE_OK;
888 }
889
890 *data = 0;
891 return SCPE_NXM;
892 }
893
894 t_stat CTLJE_wr (int32 data, int32 pa, int32 access)
895 {
896 int32 t;
897
898 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
899
900 case 0: /* CSR */
901 ODD_MRG (JCSR, data);
902 JCSR = (JCSR & ~CSRJE_WR) | (data & CSRJE_WR);
903 if (JCSR & CSRJ_LTCI) clk_fie = 1; /* force LTC int enb? */
904 else clk_fie = 0;
905 if (JCSR & CSRJ_LTCD) clk_fnxm = 1; /* force LTC reg nxm? */
906 else clk_fnxm = 0;
907 t = CSRJ_LTCSEL (JCSR); /* get freq sel */
908 if (t) clk_tps = clk_tps_map[t];
909 else clk_tps = clk_default;
910 return SCPE_OK;
911
912 case 1: /* PCR */
913 ODD_MRG (JPCR, data);
914 JPCR = data & PCRJE_RW;
915 return SCPE_OK;
916
917 case 2: /* CDR */
918 ODD_WO (data);
919 DR = data & CDRJE_WR;
920 return SCPE_OK;
921
922 case 3: /* ASR */
923 ODD_MRG (JASR, data);
924 JASR = data & ASRJE_RW;
925 toy_write (ASRJE_TOYBIT (JASR));
926 return SCPE_OK;
927 }
928
929 return SCPE_NXM;
930 }
931
932 /* Unibus adapter registers - KT24 */
933
934 t_stat UBA24_rd (int32 *data, int32 pa, int32 access)
935 {
936 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
937
938 case 2: /* LMAL */
939 *data = uba_last & LMAL_RD;
940 return SCPE_OK;
941 case 3: /* LMAH */
942 *data = uba_last & LMAH_RD;
943 return SCPE_OK;
944 }
945
946 *data = 0;
947 return SCPE_NXM;
948 }
949
950 t_stat UBA24_wr (int32 data, int32 pa, int32 access)
951 {
952 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
953
954 case 3: /* ASR */
955 ODD_IGN (data);
956 uba_last = (uba_last & ~LMAH_WR) | ((data & LMAH_WR) << 16);
957 return SCPE_OK;
958 }
959
960 return SCPE_NXM;
961 }
962
963 /* Unibus registers - KTJ11B */
964
965 t_stat UBAJ_rd (int32 *data, int32 pa, int32 access)
966 {
967 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
968
969 case 0: /* DCR */
970 *data = UDCR & DCRKTJ_RD;
971 return SCPE_OK;
972
973 case 1: /* DDR */
974 *data = UDDR & DDRKTJ_RW;
975 return SCPE_OK;
976
977 case 2: /* CSR */
978 *data = UCSR & MCRKTJ_RD;
979 return SCPE_OK;
980 }
981
982 *data = 0;
983 return SCPE_NXM;
984 }
985
986 t_stat UBAJ_wr (int32 data, int32 pa, int32 access)
987 {
988 switch ((pa >> 1) & 03) { /* decode pa<2:1> */
989
990 case 0: /* DCR */
991 ODD_MRG (UDCR, data);
992 UDCR = (UDCR & ~DCRKTJ_WR) | (data & DCRKTJ_WR);
993 return SCPE_OK;
994
995 case 1: /* DDR */
996 ODD_MRG (UDDR, data);
997 UDDR = data & DDRKTJ_RW;;
998 return SCPE_OK;
999
1000 case 2: /* CSR */
1001 ODD_MRG (UCSR, data);
1002 UCSR = (UCSR & ~MCRKTJ_WR) | (data & MCRKTJ_WR);
1003 return SCPE_OK;
1004 }
1005
1006 return SCPE_NXM;
1007 }
1008
1009 /* KDJ11E TOY routines */
1010
1011 int32 toy_read (void)
1012 {
1013 time_t curr;
1014 struct tm *ctm;
1015 int32 bit;
1016
1017 if (toy_state == 0) {
1018 curr = time (NULL); /* get curr time */
1019 if (curr == (time_t) -1) return 0; /* error? */
1020 ctm = localtime (&curr); /* decompose */
1021 if (ctm == NULL) return 0; /* error? */
1022 toy_data[TOY_HSEC] = 0x50;
1023 toy_data[TOY_SEC] = toy_set (ctm->tm_sec);
1024 toy_data[TOY_MIN] = toy_set (ctm->tm_min);
1025 toy_data[TOY_HR] = toy_set (ctm->tm_hour);
1026 toy_data[TOY_DOW] = toy_set (ctm->tm_wday);
1027 toy_data[TOY_DOM] = toy_set (ctm->tm_mday);
1028 toy_data[TOY_MON] = toy_set (ctm->tm_mon + 1);
1029 toy_data[TOY_YR] = toy_set (ctm->tm_year % 100);
1030 }
1031 bit = toy_data[toy_state >> 3] >> (toy_state & 07);
1032 toy_state = (toy_state + 1) % (TOY_LNT * 8);
1033 return (bit & 1);
1034 }
1035
1036 void toy_write (int32 bit)
1037 {
1038 toy_state = 0;
1039 return;
1040 }
1041
1042 uint8 toy_set (int32 val)
1043 {
1044 uint32 d1, d2;
1045
1046 d1 = val / 10;
1047 d2 = val % 10;
1048 return (uint8) ((d1 << 4) | d2);
1049 }
1050
1051 /* Build I/O space entries for CPU */
1052
1053 t_stat cpu_build_dib (void)
1054 {
1055 int32 i;
1056 t_stat r;
1057
1058 for (i = 0; cnf_tab[i].dib != NULL; i++) { /* loop thru config tab */
1059 if (((cnf_tab[i].cpum == 0) || (cpu_type & cnf_tab[i].cpum)) &&
1060 ((cnf_tab[i].optm == 0) || (cpu_opt & cnf_tab[i].optm))) {
1061 if (r = build_ubus_tab (&cpu_dev, cnf_tab[i].dib)) /* add to dispatch tab */
1062 return r;
1063 }
1064 }
1065 return SCPE_OK;
1066 }
1067
1068 /* Set/show CPU model */
1069
1070 t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc)
1071 {
1072 if (cptr != NULL) return SCPE_ARG;
1073 if (val >= MOD_MAX) return SCPE_IERR;
1074 if (val == (int32) cpu_model) return SCPE_OK;
1075 if (MEMSIZE > cpu_tab[val].maxm)
1076 cpu_set_size (uptr, cpu_tab[val].maxm, NULL, NULL);
1077 if (MEMSIZE > cpu_tab[val].maxm) return SCPE_INCOMP;
1078 cpu_model = val;
1079 cpu_type = 1u << cpu_model;
1080 cpu_opt = cpu_tab[cpu_model].std;
1081 cpu_set_bus (cpu_opt);
1082 reset_all (0); /* reset world */
1083 return SCPE_OK;
1084 }
1085
1086 t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
1087 {
1088 uint32 i, all_opt;
1089
1090 fprintf (st, "%s", cpu_tab[cpu_model].name);
1091 all_opt = cpu_tab[cpu_model].opt;
1092 for (i = 0; opt_name[2 * i] != NULL; i++) {
1093 if ((all_opt >> i) & 1) fprintf (st, ", %s",
1094 ((cpu_opt >> i) & 1)? opt_name[2 * i]: opt_name[(2 * i) + 1]);
1095 }
1096 return SCPE_OK;
1097 }
1098
1099 /* Set/clear CPU option */
1100
1101 t_stat cpu_set_opt (UNIT *uptr, int32 val, char *cptr, void *desc)
1102 {
1103 if (cptr) return SCPE_ARG;
1104 if ((val & cpu_tab[cpu_model].opt) == 0) return SCPE_ARG;
1105 cpu_opt = cpu_opt | val;
1106 return SCPE_OK;
1107 }
1108
1109 t_stat cpu_clr_opt (UNIT *uptr, int32 val, char *cptr, void *desc)
1110 {
1111 if (cptr) return SCPE_ARG;
1112 if ((val & cpu_tab[cpu_model].opt) == 0) return SCPE_ARG;
1113 cpu_opt = cpu_opt & ~val;
1114 return SCPE_OK;
1115 }
1116
1117 /* Memory allocation */
1118
1119 t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
1120 {
1121 int32 mc = 0;
1122 uint32 i, clim;
1123 uint16 *nM;
1124
1125 if ((val <= 0) || (val > (int32) cpu_tab[cpu_model].maxm) ||
1126 ((val & 07777) != 0)) return SCPE_ARG;
1127 for (i = val; i < MEMSIZE; i = i + 2) mc = mc | M[i >> 1];
1128 if ((mc != 0) && !get_yn ("Really truncate memory [N]?", FALSE))
1129 return SCPE_OK;
1130 nM = (uint16 *) calloc (val >> 1, sizeof (uint16));
1131 if (nM == NULL) return SCPE_MEM;
1132 clim = (((t_addr) val) < MEMSIZE)? val: MEMSIZE;
1133 for (i = 0; i < clim; i = i + 2) nM[i >> 1] = M[i >> 1];
1134 free (M);
1135 M = nM;
1136 MEMSIZE = val;
1137 if (!(sim_switches & SIM_SW_REST)) /* unless restore, */
1138 cpu_set_bus (cpu_opt); /* alter periph config */
1139 return SCPE_OK;
1140 }
1141
1142 /* Bus configuration, disable Unibus or Qbus devices */
1143
1144 t_stat cpu_set_bus (int32 opt)
1145 {
1146 DEVICE *dptr;
1147 uint32 i, mask;
1148
1149 if (opt & BUS_U) mask = DEV_UBUS; /* Unibus variant? */
1150 else if (MEMSIZE <= UNIMEMSIZE) /* 18b Qbus devices? */
1151 mask = DEV_QBUS | DEV_Q18;
1152 else mask = DEV_QBUS; /* must be 22b */
1153 for (i = 0; (dptr = sim_devices[i]) != NULL; i++) {
1154 if ((dptr->flags & DEV_DISABLE) && /* disable-able? */
1155 !(dptr->flags & DEV_DIS) && /* enabled? */
1156 ((dptr->flags & mask) == 0)) { /* not allowed? */
1157 printf ("Disabling %s\n", sim_dname (dptr));
1158 if (sim_log) fprintf (sim_log, "Disabling %s\n", sim_dname (dptr));
1159 dptr->flags = dptr->flags | DEV_DIS;
1160 }
1161 }
1162 return SCPE_OK;
1163 }
1164
1165 /* System reset */
1166
1167 t_stat sys_reset (DEVICE *dptr)
1168 {
1169 int32 i;
1170
1171 CCR = 0;
1172 HITMISS = 0;
1173 CPUERR = 0;
1174 MEMERR = 0;
1175 if (!CPUT (CPUT_J)) MAINT = 0;
1176 MBRK = 0;
1177 WCS = 0;
1178 if (CPUT (CPUT_JB|CPUT_JE))
1179 JCSR = JCSR_dflt;
1180 else JCSR = 0;
1181 JPCR = 0;
1182 JASR = 0;
1183 UDCR = 0;
1184 UDDR = 0;
1185 UCSR = 0;
1186 uba_last = 0;
1187 DR = 0;
1188 toy_state = 0;
1189 for (i = 0; i < UBM_LNT_LW; i++) ub_map[i] = 0;
1190 for (i = 0; i < TOY_LNT; i++) toy_data[i] = 0;
1191 return SCPE_OK;
1192 }
1193
1194 /* Set/show JCLK default values */
1195
1196 t_stat sys_set_jclk_dflt (UNIT *uptr, int32 val, char *cptr, void *desc)
1197 {
1198 uint32 i;
1199
1200 if ((CPUT (CPUT_JB|CPUT_JE)) && cptr) {
1201 for (i = 0; i < 4; i++) {
1202 if (strncmp (cptr, jcsr_val[i], strlen (cptr)) == 0) {
1203 JCSR_dflt = i << CSRJ_V_LTCSEL;
1204 return SCPE_OK;
1205 }
1206 }
1207 }
1208 return SCPE_ARG;
1209 }
1210
1211 t_stat sys_show_jclk_dflt (FILE *st, UNIT *uptr, int32 val, void *desc)
1212 {
1213 if (CPUT (CPUT_JB|CPUT_JE))
1214 fprintf (st, "JCLK default=%s\n", jcsr_val[CSRJ_LTCSEL (JCSR_dflt)]);
1215 else fprintf (st, "Not implemented\n");
1216 return SCPE_OK;
1217 }
Magically enhanced SIMH