PDP11/pdp11_rh.c

   1 /* pdp11_rh.c: PDP-11 Massbus adapter simulator
   2
   3    Copyright (c) 2005-2008, Robert M Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    rha, rhb             RH11/RH70 Massbus adapter
  27
  28    02-Feb-08    RMS     Fixed DMA memory address limit test (found by John Dundas)
  29    17-May-07    RMS     Moved CS1 drive enable to devices
  30    21-Nov-05    RMS     Added enable/disable routine
  31    07-Jul-05    RMS     Removed extraneous externs
  32
  33    WARNING: The interupt logic of the RH11/RH70 is unusual and must be
  34    simulated with great precision.  The RH11 has an internal interrupt
  35    request flop, CSTB INTR, which is controlled as follows:
  36
  37    - Writing IE and DONE simultaneously sets CSTB INTR
  38    - Controller clear, INIT, and interrupt acknowledge clear CSTB INTR
  39      (and also clear IE)
  40    - A transition of DONE from 0 to 1 sets CSTB INTR from IE
  41
  42    The output of CSTB INTR is OR'd with the AND of RPCS1<SC,DONE,IE> to
  43    create the interrupt request signal.  Thus,
  44
  45    - The DONE interrupt is edge sensitive, but the SC interrupt is
  46      level sensitive.
  47    - The DONE interrupt, once set, is not disabled if IE is cleared,
  48      but the SC interrupt is.
  49 */
  50
  51 #if defined (VM_PDP10)                                  /* PDP10 version */
  52 #error "PDP-10 uses pdp10_rp.c and pdp10_tu.c!"
  53
  54 #elif defined (VM_VAX)                                  /* VAX version */
  55 #error "VAX uses vax780_mba.c!"
  56
  57 #else                                                   /* PDP-11 version */
  58 #include "pdp11_defs.h"
  59 #endif
  60
  61 /* CS1 - base + 000 - control/status 1 */
  62
  63 #define CS1_OF          0
  64 #define CS1_GO          CSR_GO                          /* go */
  65 #define CS1_V_FNC       1                               /* function pos */
  66 #define CS1_M_FNC       037                             /* function mask */
  67 #define CS1_FNC         (CS1_M_FNC << CS1_V_FNC)
  68 #define FNC_XFER        024                             /* >=? data xfr */
  69 #define CS1_IE          CSR_IE                          /* int enable */
  70 #define CS1_DONE        CSR_DONE                        /* ready */
  71 #define CS1_V_UAE       8                               /* Unibus addr ext */
  72 #define CS1_M_UAE       03
  73 #define CS1_UAE         (CS1_M_UAE << CS1_V_UAE)
  74 #define CS1_MCPE        0020000                         /* Mbus par err NI */
  75 #define CS1_TRE         0040000                         /* transfer err */
  76 #define CS1_SC          0100000                         /* special cond */
  77 #define CS1_MBZ         0012000
  78 #define CS1_DRV         (CS1_FNC | CS1_GO)
  79 #define GET_FNC(x)      (((x) >> CS1_V_FNC) & CS1_M_FNC)
  80
  81 /* WC - base + 002 - word count */
  82
  83 #define WC_OF           1
  84
  85 /* BA - base + 004 - base address */
  86
  87 #define BA_OF           2
  88 #define BA_MBZ          0000001                         /* must be zero */
  89
  90 /* CS2 - base + 010 - control/status 2 */
  91
  92 #define CS2_OF          3
  93 #define CS2_V_UNIT      0                               /* unit pos */
  94 #define CS2_M_UNIT      07                              /* unit mask */
  95 #define CS2_UNIT        (CS2_M_UNIT << CS2_V_UNIT)
  96 #define CS2_UAI         0000010                         /* addr inhibit */
  97 #define CS2_PAT         0000020                         /* parity test NI */
  98 #define CS2_CLR         0000040                         /* controller clear */
  99 #define CS2_IR          0000100                         /* input ready */
 100 #define CS2_OR          0000200                         /* output ready */
 101 #define CS2_MDPE        0000400                         /* Mbus par err NI */
 102 #define CS2_MXF         0001000                         /* missed xfer NI */
 103 #define CS2_PGE         0002000                         /* program err */
 104 #define CS2_NEM         0004000                         /* nx mem err */
 105 #define CS2_NED         0010000                         /* nx drive err */
 106 #define CS2_PE          0020000                         /* parity err NI */
 107 #define CS2_WCE         0040000                         /* write check err */
 108 #define CS2_DLT         0100000                         /* data late NI */
 109 #define CS2_MBZ         (CS2_CLR)
 110 #define CS2_RW          (CS2_UNIT | CS2_UAI | CS2_PAT | CS2_MXF | CS2_PE)
 111 #define CS2_ERR         (CS2_MDPE | CS2_MXF | CS2_PGE | CS2_NEM | \
 112                          CS2_NED | CS2_PE | CS2_WCE | CS2_DLT)
 113 #define GET_UNIT(x)     (((x) >> CS2_V_UNIT) & CS2_M_UNIT)
 114
 115 /* DB - base + 022 - data buffer */
 116
 117 #define DB_OF           4
 118
 119 /* BAE - base + 050/34 - bus address extension */
 120
 121 #define BAE_OF          5
 122 #define AE_M_MAE        0                               /* addr ext pos */
 123 #define AE_V_MAE        077                             /* addr ext mask */
 124 #define AE_MBZ          0177700
 125
 126 /* CS3 - base + 052/36 - control/status 3 */
 127
 128 #define CS3_OF          6
 129 #define CS3_APE         0100000                         /* addr perr - NI */
 130 #define CS3_DPO         0040000                         /* data perr odd - NI */
 131 #define CS3_DPE         0020000                         /* data perr even - NI */
 132 #define CS3_WCO         0010000                         /* wchk err odd */
 133 #define CS3_WCE         0004000                         /* wchk err even */
 134 #define CS3_DBL         0002000                         /* dbl word xfer - NI */
 135 #define CS3_IPCK        0000017                         /* wrong par - NI */
 136 #define CS3_ERR         (CS3_APE|CS3_DPO|CS3_DPE|CS3_WCO|CS3_WCE)
 137 #define CS3_MBZ         0001660
 138 #define CS3_RW          (CS1_IE | CS3_IPCK)
 139
 140 #define MBA_OFSMASK     077                             /* max 32 reg */
 141 #define INT             0000                            /* int reg flag */
 142 #define EXT             0100                            /* ext reg flag */
 143
 144 /* Declarations */
 145
 146 #define RH11            (cpu_opt & OPT_RH11)
 147
 148 typedef struct {
 149     uint32 cs1;                                         /* ctrl/status 1 */
 150     uint32 wc;                                          /* word count */
 151     uint32 ba;                                          /* bus addr */
 152     uint32 cs2;                                         /* ctrl/status 2 */
 153     uint32 db;                                          /* data buffer */
 154     uint32 bae;                                         /* addr ext */
 155     uint32 cs3;                                         /* ctrl/status 3 */
 156     uint32 iff;                                         /* int flip flop */
 157     } MBACTX;
 158
 159 MBACTX massbus[MBA_NUM];
 160
 161 extern int32 cpu_opt, cpu_bme;
 162 extern uint16 *M;
 163 extern int32 int_req[IPL_HLVL];
 164 extern t_addr cpu_memsize;
 165 extern FILE *sim_deb;
 166 extern FILE *sim_log;
 167 extern int32 sim_switches;
 168
 169 t_stat mba_reset (DEVICE *dptr);
 170 t_stat mba_rd (int32 *val, int32 pa, int32 access);
 171 t_stat mba_wr (int32 val, int32 pa, int32 access);
 172 t_stat mba_set_type (UNIT *uptr, int32 val, char *cptr, void *desc);
 173 t_stat mba_show_type (FILE *st, UNIT *uptr, int32 val, void *desc);
 174 int32 mba0_inta (void);
 175 int32 mba1_inta (void);
 176 void mba_set_int (uint32 mb);
 177 void mba_clr_int (uint32 mb);
 178 void mba_upd_cs1 (uint32 set, uint32 clr, uint32 mb);
 179 void mba_set_cs2 (uint32 flg, uint32 mb);
 180 uint32 mba_map_pa (int32 pa, int32 *ofs);
 181 DEVICE mba0_dev, mba1_dev;
 182
 183 extern uint32 Map_Addr (uint32 ba);
 184
 185 /* Massbus register dispatches */
 186
 187 static t_stat (*mbregR[MBA_NUM])(int32 *dat, int32 ad, int32 md);
 188 static t_stat (*mbregW[MBA_NUM])(int32 dat, int32 ad, int32 md);
 189 static int32 (*mbabort[MBA_NUM])(void);
 190
 191 /* Unibus to register offset map */
 192
 193 static int32 mba_mapofs[(MBA_OFSMASK + 1) >> 1] = {
 194  INT|0,  INT|1,  INT|2,  EXT|5,  INT|3,  EXT|1,  EXT|2,  EXT|4,
 195  EXT|7,  INT|4,  EXT|3,  EXT|6,  EXT|8,  EXT|9,  EXT|10, EXT|11,
 196  EXT|12, EXT|13, EXT|14, EXT|15, EXT|16, EXT|17, EXT|18, EXT|19,
 197  EXT|20, EXT|21, EXT|22, EXT|23, EXT|24, EXT|25, EXT|26, EXT|27
 198  };
 199
 200 /* Massbus adapter data structures
 201
 202    mbax_dev     RHx device descriptor
 203    mbax_unit    RHx units
 204    mbax_reg     RHx register list
 205 */
 206
 207 DIB mba0_dib = {
 208     IOBA_RP, IOLN_RP, &mba_rd, &mba_wr,
 209     1, IVCL (RP), VEC_RP, { &mba0_inta }
 210     };
 211
 212 UNIT mba0_unit = { UDATA (NULL, 0, 0) };
 213
 214 REG mba0_reg[] = {
 215     { ORDATA (CS1, massbus[0].cs1, 16) },
 216     { ORDATA (WC, massbus[0].wc, 16) },
 217     { ORDATA (BA, massbus[0].ba, 16) },
 218     { ORDATA (CS2, massbus[0].cs2, 16) },
 219     { ORDATA (DB, massbus[0].db, 16) },
 220     { ORDATA (BAE, massbus[0].bae, 6) },
 221     { ORDATA (CS3, massbus[0].cs3, 16) },
 222     { FLDATA (IFF, massbus[0].iff, 0) },
 223     { FLDATA (INT, IREQ (RP), INT_V_RP) },
 224     { FLDATA (SC, massbus[0].cs1, CSR_V_ERR) },
 225     { FLDATA (DONE, massbus[0].cs1, CSR_V_DONE) },
 226     { FLDATA (IE, massbus[0].cs1, CSR_V_IE) },
 227     { ORDATA (DEVADDR, mba0_dib.ba, 32), REG_HRO },
 228     { ORDATA (DEVVEC, mba0_dib.vec, 16), REG_HRO },
 229     { NULL }
 230     };
 231
 232 MTAB mba0_mod[] = {
 233     { MTAB_XTD|MTAB_VDV, 0100, "ADDRESS", "ADDRESS",
 234       &set_addr, &show_addr, NULL },
 235     { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
 236       &set_vec, &show_vec, NULL },
 237     { 0 }
 238     };
 239
 240 DIB mba1_dib = {
 241     IOBA_TU, IOLN_TU, &mba_rd, &mba_wr,
 242     1, IVCL (TU), VEC_TU, { &mba1_inta }
 243     };
 244
 245 UNIT mba1_unit = { UDATA (NULL, 0, 0) };
 246
 247 REG mba1_reg[] = {
 248     { ORDATA (CS1, massbus[1].cs1, 16) },
 249     { ORDATA (WC, massbus[1].wc, 16) },
 250     { ORDATA (BA, massbus[1].ba, 16) },
 251     { ORDATA (CS2, massbus[1].cs2, 16) },
 252     { ORDATA (DB, massbus[1].db, 16) },
 253     { ORDATA (BAE, massbus[1].bae, 6) },
 254     { ORDATA (CS3, massbus[1].cs3, 16) },
 255     { FLDATA (IFF, massbus[1].iff, 0) },
 256     { FLDATA (INT, IREQ (TU), INT_V_TU) },
 257     { FLDATA (SC, massbus[1].cs1, CSR_V_ERR) },
 258     { FLDATA (DONE, massbus[1].cs1, CSR_V_DONE) },
 259     { FLDATA (IE, massbus[1].cs1, CSR_V_IE) },
 260     { ORDATA (DEVADDR, mba1_dib.ba, 32), REG_HRO },
 261     { ORDATA (DEVVEC, mba1_dib.vec, 16), REG_HRO },
 262     { NULL }
 263     };
 264
 265 MTAB mba1_mod[] = {
 266     { MTAB_XTD|MTAB_VDV, 0040, "ADDRESS", "ADDRESS",
 267       &set_addr, &show_addr, NULL },
 268     { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
 269       &set_vec, &show_vec, NULL },
 270     { 0 }
 271     };
 272
 273 DEVICE mba_dev[] = {
 274     {
 275     "RHA", &mba0_unit, mba0_reg, mba0_mod,
 276     1, 0, 0, 0, 0, 0,
 277     NULL, NULL, &mba_reset,
 278     NULL, NULL, NULL,
 279     &mba0_dib, DEV_DEBUG | DEV_DISABLE | DEV_UBUS | DEV_QBUS
 280     },
 281     {
 282     "RHB", &mba1_unit, mba1_reg, mba1_mod,
 283     1, 0, 0, 0, 0, 0,
 284     NULL, NULL, &mba_reset,
 285     NULL, NULL, NULL,
 286     &mba1_dib, DEV_DEBUG | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS
 287     }
 288     };
 289
 290 /* Read Massbus adapter register */
 291
 292 t_stat mba_rd (int32 *val, int32 pa, int32 mode)
 293 {
 294 int32 ofs, dat, mb, drv;
 295 t_stat r;
 296
 297 mb = mba_map_pa (pa, &ofs);                             /* get mb number */
 298 if ((mb < 0) || (ofs < 0)) return SCPE_NXM;             /* valid? */
 299 drv = GET_UNIT (massbus[mb].cs2);                       /* get drive */
 300 mba_upd_cs1 (0, 0, mb);                                 /* update CS1 */
 301
 302 if (ofs & EXT) {                                        /* external? */
 303     if (!mbregR[mb]) return SCPE_NXM;                   /* device there? */
 304     r = mbregR[mb] (val, ofs & ~EXT, drv);              /* call device */
 305     if (r == MBE_NXD) mba_set_cs2 (CS2_NED, mb);        /* nx drive? */
 306     else if (r == MBE_NXR) return SCPE_NXM;             /* nx reg? */
 307     return SCPE_OK;
 308     }
 309
 310 switch (ofs) {                                          /* case on reg */
 311
 312     case CS1_OF:                                        /* CS1 */
 313         if (!mbregR[mb]) return SCPE_NXM;               /* nx device? */
 314         r = mbregR[mb] (&dat, ofs, drv);                /* get dev cs1 */
 315         if (r == MBE_NXD) mba_set_cs2 (CS2_NED, mb);    /* nx drive? */
 316         *val = massbus[mb].cs1 | dat;
 317         break;
 318
 319     case WC_OF:                                         /* WC */
 320         *val = massbus[mb].wc;
 321         break;
 322
 323     case BA_OF:                                         /* BA */
 324         *val = massbus[mb].ba & ~BA_MBZ;
 325         break;
 326
 327     case CS2_OF:                                        /* CS2 */
 328         *val = massbus[mb].cs2 = (massbus[mb].cs2 & ~CS2_MBZ) | CS2_IR | CS2_OR;
 329         break;
 330
 331     case DB_OF:                                         /* DB */
 332         *val = massbus[mb].db;
 333         break;
 334
 335     case BAE_OF:                                        /* BAE */
 336         *val = massbus[mb].bae = massbus[mb].bae & ~AE_MBZ;
 337         break;
 338
 339     case CS3_OF:                                        /* CS3 */
 340         *val = massbus[mb].cs3 = (massbus[mb].cs3 & ~(CS1_IE | CS3_MBZ)) |
 341             (massbus[mb].cs1 & CS1_IE);
 342         break;
 343
 344     default:                                            /* huh? */
 345         return SCPE_NXM;
 346         }
 347
 348 return SCPE_OK;
 349 }
 350
 351 t_stat mba_wr (int32 val, int32 pa, int32 access)
 352 {
 353 int32 ofs, cs1f, drv, mb;
 354 t_stat r;
 355 t_bool cs1dt;
 356
 357 mb = mba_map_pa (pa, &ofs);                             /* get mb number */
 358 if ((mb < 0) || (ofs < 0)) return SCPE_NXM;             /* valid? */
 359 drv = GET_UNIT (massbus[mb].cs2);                       /* get drive */
 360
 361 if (ofs & EXT) {                                        /* external? */
 362     if (!mbregW[mb]) return SCPE_NXM;                   /* device there? */
 363     if ((access == WRITEB) && (pa & 1))                 /* byte writes */
 364         val = val << 8;                                 /* don't work */
 365     r = mbregW[mb] (val, ofs & ~EXT, drv);              /* write dev reg */
 366     if (r == MBE_NXD) mba_set_cs2 (CS2_NED, mb);        /* nx drive? */
 367     else if (r == MBE_NXR) return SCPE_NXM;             /* nx reg? */
 368     mba_upd_cs1 (0, 0, mb);                             /* update status */
 369     return SCPE_OK;
 370     }
 371
 372 cs1f = 0;                                               /* no int on cs1 upd */
 373 switch (ofs) {                                          /* case on reg */
 374
 375     case CS1_OF:                                        /* CS1 */
 376         if (!mbregW[mb]) return SCPE_NXM;               /* device exist? */
 377         if ((access == WRITEB) && (pa & 1)) val = val << 8;
 378         if (val & CS1_TRE) {                            /* error clear? */
 379             massbus[mb].cs1 &= ~CS1_TRE;                /* clr CS1<TRE> */
 380             massbus[mb].cs2 &= ~CS2_ERR;                /* clr CS2<15:8> */
 381             massbus[mb].cs3 &= ~CS3_ERR;                /* clr CS3<15:11> */
 382             }
 383         if ((access == WRITE) || (pa & 1)) {            /* hi byte write? */
 384             if (massbus[mb].cs1 & CS1_DONE)             /* done set? */
 385                 massbus[mb].cs1 = (massbus[mb].cs1 & ~CS1_UAE) | (val & CS1_UAE);
 386             }
 387         if ((access == WRITE) || !(pa & 1)) {           /* lo byte write? */
 388             if ((val & CS1_DONE) && (val & CS1_IE))     /* to DONE+IE? */
 389                 massbus[mb].iff = 1;                    /* set CSTB INTR */
 390             massbus[mb].cs1 = (massbus[mb].cs1 & ~CS1_IE) | (val & CS1_IE);
 391             cs1dt = (val & CS1_GO) && (GET_FNC (val) >= FNC_XFER);
 392             if (cs1dt && ((massbus[mb].cs1 & CS1_DONE) == 0))  /* dt, done clr? */
 393                 mba_set_cs2 (CS2_PGE, mb);              /* prgm error */
 394             else {
 395                 r = mbregW[mb] (val & 077, ofs, drv);   /* write dev CS1 */
 396                 if (r == MBE_NXD) mba_set_cs2 (CS2_NED, mb);    /* nx drive? */
 397                 else if (r == MBE_NXR) return SCPE_NXM; /* nx reg? */
 398                 else if (cs1dt && (r == SCPE_OK)) {     /* xfer, no err? */
 399                     massbus[mb].cs1 &= ~(CS1_TRE | CS1_MCPE | CS1_DONE);
 400                     massbus[mb].cs2 &= ~CS2_ERR;        /* clear errors */
 401                     massbus[mb].cs3 &= ~(CS3_ERR | CS3_DBL);
 402                     }
 403                 }
 404             }
 405         massbus[mb].cs3 = (massbus[mb].cs3 & ~CS1_IE) | /* update CS3 */
 406             (massbus[mb].cs1 & CS1_IE);
 407         massbus[mb].bae = (massbus[mb].bae & ~CS1_M_UAE) | /* update BAE */
 408             ((massbus[mb].cs1 >> CS1_V_UAE) & CS1_M_UAE);
 409         break;
 410
 411     case WC_OF:                                         /* WC */
 412         if (access == WRITEB) val = (pa & 1)?
 413             (massbus[mb].wc & 0377) | (val << 8):
 414             (massbus[mb].wc & ~0377) | val;
 415         massbus[mb].wc = val;
 416         break;
 417
 418     case BA_OF:                                         /* BA */
 419         if (access == WRITEB) val = (pa & 1)?
 420             (massbus[mb].ba & 0377) | (val << 8):
 421             (massbus[mb].ba & ~0377) | val;
 422         massbus[mb].ba = val & ~BA_MBZ;
 423         break;
 424
 425     case CS2_OF:                                        /* CS2 */
 426         if ((access == WRITEB) && (pa & 1)) val = val << 8;
 427         if (val & CS2_CLR) mba_reset (&mba_dev[mb]);    /* init? */
 428         else {
 429             if ((val & ~massbus[mb].cs2) & (CS2_PE | CS2_MXF))
 430                 cs1f = CS1_SC;                          /* diagn intr */
 431             if (access == WRITEB) val = (massbus[mb].cs2 &  /* merge val */
 432                 ((pa & 1)? 0377: 0177400)) | val;
 433             massbus[mb].cs2 = (massbus[mb].cs2 & ~CS2_RW) |
 434                 (val & CS2_RW) | CS2_IR | CS2_OR;
 435             }
 436         break;
 437
 438     case DB_OF:                                         /* DB */
 439         if (access == WRITEB) val = (pa & 1)?
 440             (massbus[mb].db & 0377) | (val << 8):
 441             (massbus[mb].db & ~0377) | val;
 442         massbus[mb].db = val;
 443         break;
 444
 445     case BAE_OF:                                       /* BAE */
 446         if ((access == WRITEB) && (pa & 1)) break;
 447         massbus[mb].bae = val & ~AE_MBZ;
 448         massbus[mb].cs1 = (massbus[mb].cs1 & ~CS1_UAE) | /* update CS1 */
 449             ((massbus[mb].bae << CS1_V_UAE) & CS1_UAE);
 450         break;
 451
 452     case CS3_OF:                                        /* CS3 */
 453         if ((access == WRITEB) && (pa & 1)) break;
 454         massbus[mb].cs3 = (massbus[mb].cs3 & ~CS3_RW) | (val & CS3_RW);
 455         massbus[mb].cs1 = (massbus[mb].cs1 & ~CS1_IE) | /* update CS1 */
 456             (massbus[mb].cs3 & CS1_IE);
 457         break;
 458
 459     default:
 460         return SCPE_NXM;
 461         }
 462
 463 mba_upd_cs1 (cs1f, 0, mb);                              /* update status */
 464 return SCPE_OK;
 465 }
 466
 467 /* Massbus I/O routines
 468
 469    mb_rdbufW    -       fetch word buffer from memory
 470    mb_wrbufW    -       store word buffer into memory
 471    mb_chbufW    -       compare word buffer with memory
 472
 473    Returns number of bytes successfully transferred/checked
 474 */
 475
 476 int32 mba_rdbufW (uint32 mb, int32 bc, uint16 *buf)
 477 {
 478 int32 i, j, ba, mbc, pbc;
 479 uint32 pa;
 480
 481 bc = bc & ~1;                                           /* bc even */
 482 if (mb >= MBA_NUM) return 0;                            /* valid MBA? */
 483 ba = (massbus[mb].bae << 16) | massbus[mb].ba;          /* get busaddr */
 484 mbc = (0200000 - massbus[mb].wc) << 1;                  /* MB byte count */
 485 if (bc > mbc) bc = mbc;                                 /* use smaller */
 486 for (i = 0; i < bc; i = i + pbc) {                      /* loop by pages */
 487     if (RH11 && cpu_bme) pa = Map_Addr (ba);            /* map addr */
 488     else pa = ba;
 489     if (!ADDR_IS_MEM (pa)) {                            /* NXM? */
 490         mba_set_cs2 (CS2_NEM, mb);                      /* set error */
 491         break;
 492         }
 493     pbc = UBM_PAGSIZE - UBM_GETOFF (pa);                /* left in page */
 494     if (pbc > (bc - i)) pbc = bc - i;                   /* limit to rem xfr */
 495     for (j = 0; j < pbc; j = j + 2) {                   /* loop by words */
 496         *buf++ = M[pa >> 1];                            /* fetch word */
 497         if (!(massbus[mb].cs2 & CS2_UAI)) {             /* if not inhb */
 498             ba = ba + 2;                                /* incr ba, pa */
 499             pa = pa + 2;
 500             }
 501         }
 502     }
 503 massbus[mb].wc = (massbus[mb].wc + (bc >> 1)) & DMASK;   /* update wc */
 504 massbus[mb].ba = ba & DMASK;                             /* update ba */
 505 massbus[mb].bae = (ba >> 16) & ~AE_MBZ;                  /* upper 6b */
 506 massbus[mb].cs1 = (massbus[mb].cs1 & ~ CS1_UAE) |         /* update CS1 */
 507     ((massbus[mb].bae << CS1_V_UAE) & CS1_UAE);
 508 return i;
 509 }
 510
 511 int32 mba_wrbufW (uint32 mb, int32 bc, uint16 *buf)
 512 {
 513 int32 i, j, ba, mbc, pbc;
 514 uint32 pa;
 515
 516 bc = bc & ~1;                                           /* bc even */
 517 if (mb >= MBA_NUM) return 0;                            /* valid MBA? */
 518 ba = (massbus[mb].bae << 16) | massbus[mb].ba;          /* get busaddr */
 519 mbc = (0200000 - massbus[mb].wc) << 1;                  /* MB byte count */
 520 if (bc > mbc) bc = mbc;                                 /* use smaller */
 521 for (i = 0; i < bc; i = i + pbc) {                      /* loop by pages */
 522     if (RH11 && cpu_bme) pa = Map_Addr (ba);            /* map addr */
 523     else pa = ba;
 524     if (!ADDR_IS_MEM (pa)) {                            /* NXM? */
 525         mba_set_cs2 (CS2_NEM, mb);                      /* set error */
 526         break;
 527         }
 528     pbc = UBM_PAGSIZE - UBM_GETOFF (pa);                /* left in page */
 529     if (pbc > (bc - i)) pbc = bc - i;                   /* limit to rem xfr */
 530     for (j = 0; j < pbc; j = j + 2) {                   /* loop by words */
 531         M[pa >> 1] = *buf++;                            /* put word */
 532         if (!(massbus[mb].cs2 & CS2_UAI)) {             /* if not inhb */
 533             ba = ba + 2;                                /* incr ba, pa */
 534             pa = pa + 2;
 535             }
 536         }
 537     }
 538 massbus[mb].wc = (massbus[mb].wc + (bc >> 1)) & DMASK;  /* update wc */
 539 massbus[mb].ba = ba & DMASK;                            /* update ba */
 540 massbus[mb].bae = (ba >> 16) & ~AE_MBZ;                 /* upper 6b */
 541 massbus[mb].cs1 = (massbus[mb].cs1 & ~ CS1_UAE) |       /* update CS1 */
 542     ((massbus[mb].bae << CS1_V_UAE) & CS1_UAE);
 543 return i;
 544 }
 545
 546 int32 mba_chbufW (uint32 mb, int32 bc, uint16 *buf)
 547 {
 548 int32 i, j, ba, mbc, pbc;
 549 uint32 pa;
 550
 551 bc = bc & ~1;                                           /* bc even */
 552 if (mb >= MBA_NUM) return 0;                            /* valid MBA? */
 553 ba = (massbus[mb].bae << 16) | massbus[mb].ba;          /* get busaddr */
 554 mbc = (0200000 - massbus[mb].wc) << 1;                  /* MB byte count */
 555 if (bc > mbc) bc = mbc;                                 /* use smaller */
 556 for (i = 0; i < bc; i = i + pbc) {                      /* loop by pages */
 557     if (RH11 && cpu_bme) pa = Map_Addr (ba);            /* map addr */
 558     else pa = ba;
 559     if (!ADDR_IS_MEM (pa)) {                            /* NXM? */
 560         mba_set_cs2 (CS2_NEM, mb);                      /* set error */
 561         break;
 562         }
 563     pbc = UBM_PAGSIZE - UBM_GETOFF (pa);                /* left in page */
 564     if (pbc > (bc - i)) pbc = bc - i;                   /* limit to rem xfr */
 565     for (j = 0; j < pbc; j = j + 2) {                   /* loop by words */
 566         massbus[mb].db = *buf++;                        /* get dev word */
 567         if (M[pa >> 1] != massbus[mb].db) {             /* miscompare? */
 568             mba_set_cs2 (CS2_WCE, mb);                  /* set error */
 569             massbus[mb].cs3 = massbus[mb].cs3 |         /* set even/odd */
 570                 ((pa & 1)? CS3_WCO: CS3_WCE);
 571             break;
 572             }
 573         if (!(massbus[mb].cs2 & CS2_UAI)) {             /* if not inhb */
 574             ba = ba + 2;                                /* incr ba, pa */
 575             pa = pa + 2;
 576             }
 577         }
 578     }
 579 massbus[mb].wc = (massbus[mb].wc + (bc >> 1)) & DMASK;  /* update wc */
 580 massbus[mb].ba = ba & DMASK;                            /* update ba */
 581 massbus[mb].bae = (ba >> 16) & ~AE_MBZ;                 /* upper 6b */
 582 massbus[mb].cs1 = (massbus[mb].cs1 & ~ CS1_UAE) |       /* update CS1 */
 583     ((massbus[mb].bae << CS1_V_UAE) & CS1_UAE);
 584 return i;
 585 }
 586
 587 /* Device access, status, and interrupt routines */
 588
 589 void mba_set_don (uint32 mb)
 590 {
 591 mba_upd_cs1 (CS1_DONE, 0, mb);
 592 return;
 593 }
 594
 595 void mba_upd_ata (uint32 mb, uint32 val)
 596 {
 597 if (val) mba_upd_cs1 (CS1_SC, 0, mb);
 598 else mba_upd_cs1 (0, CS1_SC, mb);
 599 return;
 600 }
 601
 602 void mba_set_exc (uint32 mb)
 603 {
 604 mba_upd_cs1 (CS1_TRE | CS1_DONE, 0, mb);
 605 return;
 606 }
 607
 608 int32 mba_get_bc (uint32 mb)
 609 {
 610 if (mb >= MBA_NUM) return 0;
 611 return ((0200000 - massbus[mb].wc) << 1);
 612 }
 613
 614 int32 mba_get_csr (uint32 mb)
 615 {
 616 DIB *dibp;
 617
 618 if (mb >= MBA_NUM) return 0;
 619 dibp = (DIB *) mba_dev[mb].ctxt;
 620 return dibp->ba;
 621 }
 622
 623 void mba_set_int (uint32 mb)
 624 {
 625 DIB *dibp;
 626
 627 if (mb >= MBA_NUM) return;
 628 dibp = (DIB *) mba_dev[mb].ctxt;
 629 int_req[dibp->vloc >> 5] |= (1 << (dibp->vloc & 037));
 630 return;
 631 }
 632
 633 void mba_clr_int (uint32 mb)
 634 {
 635 DIB *dibp;
 636
 637 if (mb >= MBA_NUM) return;
 638 dibp = (DIB *) mba_dev[mb].ctxt;
 639 int_req[dibp->vloc >> 5] &= ~(1 << (dibp->vloc & 037));
 640 return;
 641 }
 642
 643 void mba_upd_cs1 (uint32 set, uint32 clr, uint32 mb)
 644 {
 645 if (mb >= MBA_NUM) return;
 646 if ((set & ~massbus[mb].cs1) & CS1_DONE)                    /* DONE 0 to 1? */
 647     massbus[mb].iff = (massbus[mb].cs1 & CS1_IE)? 1: 0;     /* CSTB INTR <- IE */
 648 massbus[mb].cs1 = (massbus[mb].cs1 & ~(clr | CS1_MCPE | CS1_MBZ | CS1_DRV)) | set;
 649 if (massbus[mb].cs2 & CS2_ERR) massbus[mb].cs1 = massbus[mb].cs1 | CS1_TRE | CS1_SC;
 650 else if (massbus[mb].cs1 & CS1_TRE) massbus[mb].cs1 = massbus[mb].cs1 | CS1_SC;
 651 if (massbus[mb].iff ||
 652     ((massbus[mb].cs1 & CS1_SC) &&
 653      (massbus[mb].cs1 & CS1_DONE) &&
 654      (massbus[mb].cs1 & CS1_IE)))
 655     mba_set_int (mb);
 656 else mba_clr_int (mb);
 657 return;
 658 }
 659
 660 void mba_set_cs2 (uint32 flag, uint32 mb)
 661 {
 662 if (mb >= MBA_NUM) return;
 663 massbus[mb].cs2 = massbus[mb].cs2 | flag;
 664 mba_upd_cs1 (0, 0, mb);
 665 return;
 666 }
 667
 668 /* Interrupt acknowledge */
 669
 670 int32 mba0_inta (void)
 671 {
 672 massbus[0].cs1 &= ~CS1_IE;                              /* clear int enable */
 673 massbus[0].cs3 &= ~CS1_IE;                              /* in both registers */
 674 massbus[0].iff = 0;                                     /* clear CSTB INTR */
 675 return mba0_dib.vec;                                    /* acknowledge */
 676 }
 677
 678 int32 mba1_inta (void)
 679 {
 680 massbus[1].cs1 &= ~CS1_IE;                              /* clear int enable */
 681 massbus[1].cs3 &= ~CS1_IE;                              /* in both registers */
 682 massbus[1].iff = 0;                                     /* clear CSTB INTR */
 683 return mba1_dib.vec;                                    /* acknowledge */
 684 }
 685
 686 /* Map physical address to Massbus number, offset */
 687
 688 uint32 mba_map_pa (int32 pa, int32 *ofs)
 689 {
 690 int32 i, uo, ba, lnt;
 691 DIB *dibp;
 692
 693 for (i = 0; i < MBA_NUM; i++) {                         /* loop thru ctrls */
 694     dibp = (DIB *) mba_dev[i].ctxt;                     /* get DIB */
 695     ba = dibp->ba;
 696     lnt = dibp->lnt;
 697     if ((pa >= ba) &&                                   /* in range? */
 698         (pa < (ba + lnt))) {
 699         if (pa < (ba + (lnt - 4))) {                    /* not last two? */
 700             uo = ((pa - ba) & MBA_OFSMASK) >> 1;        /* get Unibus offset */
 701             *ofs = mba_mapofs[uo];                      /* map thru PROM */
 702             return i;                                   /* return ctrl idx */
 703             }
 704         else if (RH11) return -1;                       /* RH11? done */
 705         else {                                          /* RH70 */
 706             uo = (pa - (ba + (lnt - 4))) >> 1;          /* offset relative */
 707             *ofs = BAE_OF + uo;                         /* to BAE */
 708             return i;
 709             }
 710         }
 711     }
 712 return -1;
 713 }
 714
 715 /* Reset Massbus adapter */
 716
 717 t_stat mba_reset (DEVICE *dptr)
 718 {
 719 uint32 mb;
 720
 721 mb = dptr - mba_dev;
 722 if (mb >= MBA_NUM) return SCPE_NOFNC;
 723 massbus[mb].cs1 = CS1_DONE;
 724 massbus[mb].wc = 0;
 725 massbus[mb].ba = 0;
 726 massbus[mb].cs2 = 0;
 727 massbus[mb].db = 0;
 728 massbus[mb].bae= 0;
 729 massbus[mb].cs3 = 0;
 730 massbus[mb].iff = 0;
 731 mba_clr_int (mb);
 732 if (mbabort[mb]) mbabort[mb] ();
 733 return SCPE_OK;
 734 }
 735
 736 /* Enable/disable Massbus adapter */
 737
 738 void mba_set_enbdis (uint32 mb, t_bool dis)
 739 {
 740 if (mb >= MBA_NUM) return;                              /* valid MBA? */
 741 if (dis) mba_dev[mb].flags |= DEV_DIS;
 742 else mba_dev[mb].flags &= ~DEV_DIS;
 743 return;
 744 }
 745
 746 /* Show Massbus adapter number */
 747
 748 t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc)
 749 {
 750 DEVICE *dptr = find_dev_from_unit (uptr);
 751 DIB *dibp;
 752
 753 if (dptr == NULL) return SCPE_IERR;
 754 dibp = (DIB *) dptr->ctxt;
 755 if (dibp == NULL) return SCPE_IERR;
 756 fprintf (st, "Massbus adapter %d", dibp->ba);
 757 return SCPE_OK;
 758 }
 759
 760 /* Init Mbus tables */
 761
 762 void init_mbus_tab (void)
 763 {
 764 uint32 i;
 765
 766 for (i = 0; i < MBA_NUM; i++) {
 767     mbregR[i] = NULL;
 768     mbregW[i] = NULL;
 769     mbabort[i] = NULL;
 770     }
 771 return;
 772 }
 773
 774 /* Build dispatch tables */
 775
 776 t_stat build_mbus_tab (DEVICE *dptr, DIB *dibp)
 777 {
 778 uint32 idx;
 779
 780 if ((dptr == NULL) || (dibp == NULL)) return SCPE_IERR; /* validate args */
 781 idx = dibp->ba;                                         /* Mbus # */
 782 if (idx >= MBA_NUM) return SCPE_STOP;
 783 if ((mbregR[idx] && dibp->rd &&                         /* conflict? */
 784     (mbregR[idx] != dibp->rd)) ||
 785     (mbregW[idx] && dibp->wr &&
 786     (mbregW[idx] != dibp->wr)) ||
 787     (mbabort[idx] && dibp->ack[0] &&
 788     (mbabort[idx] != dibp->ack[0]))) {
 789         printf ("Massbus %s assignment conflict at %d\n",
 790             sim_dname (dptr), dibp->ba);
 791         if (sim_log) fprintf (sim_log,
 792             "Massbus %s assignment conflict at %d\n",
 793             sim_dname (dptr), dibp->ba);
 794         return SCPE_STOP;
 795         }
 796 if (dibp->rd) mbregR[idx] = dibp->rd;                   /* set rd dispatch */
 797 if (dibp->wr) mbregW[idx] = dibp->wr;                   /* set wr dispatch */
 798 if (dibp->ack[0]) mbabort[idx] = dibp->ack[0];          /* set abort dispatch */
 799 return SCPE_OK;
 800 }
 801