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First Commit of my working state
[simh.git] / PDP11 / pdp11_tc.c
1 /* pdp11_tc.c: PDP-11 DECtape simulator
2
3 Copyright (c) 1993-2006, Robert M Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 tc TC11/TU56 DECtape
27
28 23-Jun-06 RMS Fixed switch conflict in ATTACH
29 10-Feb-06 RMS READ sets extended data bits in TCST (found by Alan Frisbie)
30 16-Aug-05 RMS Fixed C++ declaration and cast problems
31 07-Jul-05 RMS Removed extraneous externs
32 30-Sep-04 RMS Revised Unibus interface
33 25-Jan-04 RMS Revised for device debug support
34 09-Jan-04 RMS Changed sim_fsize calling sequence, added STOP_OFFR
35 29-Dec-03 RMS Changed initial status to disabled (in Qbus system)
36 18-Oct-03 RMS Fixed reverse checksum in read all
37 Added DECtape off reel message
38 Simplified timing
39 25-Apr-03 RMS Revised for extended file support
40 14-Mar-03 RMS Fixed variable size interaction with save/restore
41 29-Sep-02 RMS Added variable address support to bootstrap
42 Added vector change/display support
43 Added 16b format support
44 New data structures
45 30-May-02 RMS Widened POS to 32b
46 26-Jan-02 RMS Revised bootstrap to conform to M9312
47 06-Jan-02 RMS Revised enable/disable support
48 30-Nov-01 RMS Added read only unit, extended SET/SHOW support
49 24-Nov-01 RMS Converted POS, STATT, LASTT to arrays
50 09-Nov-01 RMS Added bus map support
51 15-Sep-01 RMS Integrated debug logging
52 27-Sep-01 RMS Fixed interrupt after stop for RSTS/E
53 07-Sep-01 RMS Revised device disable and interrupt mechanisms
54 29-Aug-01 RMS Added casts to PDP-8 unpack routine
55 17-Jul-01 RMS Moved function prototype
56 11-May-01 RMS Fixed bug in reset
57 26-Apr-01 RMS Added device enable/disable support
58 18-Apr-01 RMS Changed to rewind tape before boot
59 16-Mar-01 RMS Fixed bug in interrupt after stop
60 15-Mar-01 RMS Added 129th word to PDP-8 format
61
62 PDP-11 DECtapes are represented in memory by fixed length buffer of 32b words.
63 Three file formats are supported:
64
65 18b/36b 256 words per block [256 x 18b]
66 16b 256 words per block [256 x 16b]
67 12b 129 words per block [129 x 12b]
68
69 When a 16b or 12b DECtape file is read in, it is converted to 18b/36b format.
70
71 DECtape motion is measured in 3b lines. Time between lines is 33.33us.
72 Tape density is nominally 300 lines per inch. The format of a DECtape (as
73 taken from the TD8E formatter) is:
74
75 reverse end zone 8192 reverse end zone codes ~ 10 feet
76 reverse buffer 200 interblock codes
77 block 0
78 :
79 block n
80 forward buffer 200 interblock codes
81 forward end zone 8192 forward end zone codes ~ 10 feet
82
83 A block consists of five 18b header words, a tape-specific number of data
84 words, and five 18b trailer words. All systems except the PDP-8 use a
85 standard block length of 256 words; the PDP-8 uses a standard block length
86 of 86 words (x 18b = 129 words x 12b).
87
88 Because a DECtape file only contains data, the simulator cannot support
89 write timing and mark track and can only do a limited implementation
90 of read all and write all. Read all assumes that the tape has been
91 conventionally written forward:
92
93 header word 0 0
94 header word 1 block number (for forward reads)
95 header words 2,3 0
96 header word 4 checksum (for reverse reads)
97 :
98 trailer word 4 checksum (for forward reads)
99 trailer words 3,2 0
100 trailer word 1 block number (for reverse reads)
101 trailer word 0 0
102
103 Write all writes only the data words and dumps the interblock words in the
104 bit bucket.
105 */
106
107 #include "pdp11_defs.h"
108
109 #define DT_NUMDR 8 /* #drives */
110 #define DT_M_NUMDR (DT_NUMDR - 1)
111 #define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
112 #define UNIT_V_8FMT (UNIT_V_UF + 1) /* 12b format */
113 #define UNIT_V_11FMT (UNIT_V_UF + 2) /* 16b format */
114 #define UNIT_WLK (1 << UNIT_V_WLK)
115 #define UNIT_8FMT (1 << UNIT_V_8FMT)
116 #define UNIT_11FMT (1 << UNIT_V_11FMT)
117 #define STATE u3 /* unit state */
118 #define LASTT u4 /* last time update */
119 #define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
120
121 /* System independent DECtape constants */
122
123 #define DT_LPERMC 6 /* lines per mark track */
124 #define DT_BLKWD 1 /* blk no word in h/t */
125 #define DT_CSMWD 4 /* checksum word in h/t */
126 #define DT_HTWRD 5 /* header/trailer words */
127 #define DT_EZLIN (8192 * DT_LPERMC) /* end zone length */
128 #define DT_BFLIN (200 * DT_LPERMC) /* buffer length */
129 #define DT_BLKLN (DT_BLKWD * DT_LPERMC) /* blk no line in h/t */
130 #define DT_CSMLN (DT_CSMWD * DT_LPERMC) /* csum line in h/t */
131 #define DT_HTLIN (DT_HTWRD * DT_LPERMC) /* header/trailer lines */
132
133 /* 16b, 18b, 36b DECtape constants */
134
135 #define D18_WSIZE 6 /* word size in lines */
136 #define D18_BSIZE 256 /* block size in 18b */
137 #define D18_TSIZE 578 /* tape size */
138 #define D18_LPERB (DT_HTLIN + (D18_BSIZE * DT_WSIZE) + DT_HTLIN)
139 #define D18_FWDEZ (DT_EZLIN + (D18_LPERB * D18_TSIZE))
140 #define D18_CAPAC (D18_TSIZE * D18_BSIZE) /* tape capacity */
141 #define D16_FILSIZ (D18_TSIZE * D18_BSIZE * sizeof (int16))
142
143 /* 12b DECtape constants */
144
145 #define D8_WSIZE 4 /* word size in lines */
146 #define D8_BSIZE 86 /* block size in 18b */
147 #define D8_TSIZE 1474 /* tape size */
148 #define D8_LPERB (DT_HTLIN + (D8_BSIZE * DT_WSIZE) + DT_HTLIN)
149 #define D8_FWDEZ (DT_EZLIN + (D8_LPERB * D8_TSIZE))
150 #define D8_CAPAC (D8_TSIZE * D8_BSIZE) /* tape capacity */
151
152 #define D8_NBSIZE ((D8_BSIZE * D18_WSIZE) / D8_WSIZE)
153 #define D8_FILSIZ (D8_NBSIZE * D8_TSIZE * sizeof (int16))
154
155 /* This controller */
156
157 #define DT_CAPAC D18_CAPAC /* default */
158 #define DT_WSIZE D18_WSIZE
159
160 /* Calculated constants, per unit */
161
162 #define DTU_BSIZE(u) (((u)->flags & UNIT_8FMT)? D8_BSIZE: D18_BSIZE)
163 #define DTU_TSIZE(u) (((u)->flags & UNIT_8FMT)? D8_TSIZE: D18_TSIZE)
164 #define DTU_LPERB(u) (((u)->flags & UNIT_8FMT)? D8_LPERB: D18_LPERB)
165 #define DTU_FWDEZ(u) (((u)->flags & UNIT_8FMT)? D8_FWDEZ: D18_FWDEZ)
166 #define DTU_CAPAC(u) (((u)->flags & UNIT_8FMT)? D8_CAPAC: D18_CAPAC)
167
168 #define DT_LIN2BL(p,u) (((p) - DT_EZLIN) / DTU_LPERB (u))
169 #define DT_LIN2OF(p,u) (((p) - DT_EZLIN) % DTU_LPERB (u))
170 #define DT_LIN2WD(p,u) ((DT_LIN2OF (p,u) - DT_HTLIN) / DT_WSIZE)
171 #define DT_BLK2LN(p,u) (((p) * DTU_LPERB (u)) + DT_EZLIN)
172 #define DT_QREZ(u) (((u)->pos) < DT_EZLIN)
173 #define DT_QFEZ(u) (((u)->pos) >= ((uint32) DTU_FWDEZ (u)))
174 #define DT_QEZ(u) (DT_QREZ (u) || DT_QFEZ (u))
175
176 /* TCST - 177340 - status register */
177
178 #define STA_END 0100000 /* end zone */
179 #define STA_PAR 0040000 /* parity err */
180 #define STA_MRK 0020000 /* mark trk err */
181 #define STA_ILO 0010000 /* illegal op */
182 #define STA_SEL 0004000 /* select err */
183 #define STA_BLKM 0002000 /* block miss err */
184 #define STA_DATM 0001000 /* data miss err */
185 #define STA_NXM 0000400 /* nx mem err */
186 #define STA_UPS 0000200 /* up to speed */
187 #define STA_V_XD 0 /* extended data */
188 #define STA_M_XD 03
189 #define STA_ALLERR (STA_END | STA_PAR | STA_MRK | STA_ILO | \
190 STA_SEL | STA_BLKM | STA_DATM | STA_NXM )
191 #define STA_RWERR (STA_END | STA_PAR | STA_MRK | \
192 STA_BLKM | STA_DATM | STA_NXM )
193 #define STA_RW 0000003
194 #define STA_GETXD(x) (((x) >> STA_V_XD) & STA_M_XD)
195
196 /* TCCM - 177342 - command register */
197
198 /* #define CSR_ERR 0100000 */
199 #define CSR_MNT 0020000 /* maint (unimpl) */
200 #define CSR_INH 0010000 /* delay inhibit */
201 #define CSR_DIR 0004000 /* reverse */
202 #define CSR_V_UNIT 8 /* unit select */
203 #define CSR_M_UNIT 07
204 #define CSR_UNIT (CSR_M_UNIT << CSR_V_UNIT)
205 /* #define CSR_DONE 0000200 */
206 /* #define CSR_IE 0000100 */
207 #define CSR_V_MEX 4 /* mem extension */
208 #define CSR_M_MEX 03
209 #define CSR_MEX (CSR_M_MEX << CSR_V_MEX)
210 #define CSR_V_FNC 1 /* function */
211 #define CSR_M_FNC 07
212 #define FNC_STOP 00 /* stop all */
213 #define FNC_SRCH 01 /* search */
214 #define FNC_READ 02 /* read */
215 #define FNC_RALL 03 /* read all */
216 #define FNC_SSEL 04 /* stop selected */
217 #define FNC_WMRK 05 /* write */
218 #define FNC_WRIT 06 /* write all */
219 #define FNC_WALL 07 /* write timing */
220 /* define CSR_GO 0000001 */
221 #define CSR_RW 0117576 /* read/write */
222
223 #define CSR_GETUNIT(x) (((x) >> CSR_V_UNIT) & CSR_M_UNIT)
224 #define CSR_GETMEX(x) (((x) >> CSR_V_MEX) & CSR_M_MEX)
225 #define CSR_GETFNC(x) (((x) >> CSR_V_FNC) & CSR_M_FNC)
226 #define CSR_INCMEX(x) (((x) & ~CSR_MEX) | (((x) + (1 << CSR_V_MEX)) & CSR_MEX))
227
228 /* TCWC - 177344 - word count */
229
230 /* TCBA - 177346 - bus address */
231
232 /* TCDT - 177350 - data */
233
234 /* DECtape state */
235
236 #define DTS_V_MOT 3 /* motion */
237 #define DTS_M_MOT 07
238 #define DTS_STOP 0 /* stopped */
239 #define DTS_DECF 2 /* decel, fwd */
240 #define DTS_DECR 3 /* decel, rev */
241 #define DTS_ACCF 4 /* accel, fwd */
242 #define DTS_ACCR 5 /* accel, rev */
243 #define DTS_ATSF 6 /* @speed, fwd */
244 #define DTS_ATSR 7 /* @speed, rev */
245 #define DTS_DIR 01 /* dir mask */
246 #define DTS_V_FNC 0 /* function */
247 #define DTS_M_FNC 07
248 #define DTS_OFR FNC_WMRK /* "off reel" */
249 #define DTS_GETMOT(x) (((x) >> DTS_V_MOT) & DTS_M_MOT)
250 #define DTS_GETFNC(x) (((x) >> DTS_V_FNC) & DTS_M_FNC)
251 #define DTS_V_2ND 6 /* next state */
252 #define DTS_V_3RD (DTS_V_2ND + DTS_V_2ND) /* next next */
253 #define DTS_STA(y,z) (((y) << DTS_V_MOT) | ((z) << DTS_V_FNC))
254 #define DTS_SETSTA(y,z) uptr->STATE = DTS_STA (y, z)
255 #define DTS_SET2ND(y,z) uptr->STATE = (uptr->STATE & 077) | \
256 ((DTS_STA (y, z)) << DTS_V_2ND)
257 #define DTS_SET3RD(y,z) uptr->STATE = (uptr->STATE & 07777) | \
258 ((DTS_STA (y, z)) << DTS_V_3RD)
259 #define DTS_NXTSTA(x) (x >> DTS_V_2ND)
260
261 /* Logging */
262
263 #define LOG_MS 0x1
264 #define LOG_RW 0x2
265 #define LOG_BL 0x4
266
267 #define DT_SETDONE tccm = tccm | CSR_DONE; \
268 if (tccm & CSR_IE) SET_INT (DTA)
269 #define DT_CLRDONE tccm = tccm & ~CSR_DONE; \
270 CLR_INT (DTA)
271 #define ABS(x) (((x) < 0)? (-(x)): (x))
272
273 extern uint16 *M; /* memory */
274 extern int32 int_req[IPL_HLVL];
275 extern UNIT cpu_unit;
276 extern int32 sim_switches;
277 extern FILE *sim_deb;
278
279 int32 tcst = 0; /* status */
280 int32 tccm = 0; /* command */
281 int32 tcwc = 0; /* word count */
282 int32 tcba = 0; /* bus address */
283 int32 tcdt = 0; /* data */
284 int32 dt_ctime = 100; /* fast cmd time */
285 int32 dt_ltime = 12; /* interline time */
286 int32 dt_dctime = 40000; /* decel time */
287 int32 dt_substate = 0;
288 int32 dt_logblk = 0;
289 int32 dt_stopoffr = 0;
290
291 DEVICE dt_dev;
292 t_stat dt_rd (int32 *data, int32 PA, int32 access);
293 t_stat dt_wr (int32 data, int32 PA, int32 access);
294 t_stat dt_svc (UNIT *uptr);
295 t_stat dt_svcdone (UNIT *uptr);
296 t_stat dt_reset (DEVICE *dptr);
297 t_stat dt_attach (UNIT *uptr, char *cptr);
298 t_stat dt_detach (UNIT *uptr);
299 t_stat dt_boot (int32 unitno, DEVICE *dptr);
300 void dt_deselect (int32 oldf);
301 void dt_newsa (int32 newf);
302 void dt_newfnc (UNIT *uptr, int32 newsta);
303 t_bool dt_setpos (UNIT *uptr);
304 void dt_schedez (UNIT *uptr, int32 dir);
305 void dt_seterr (UNIT *uptr, int32 e);
306 void dt_stopunit (UNIT *uptr);
307 int32 dt_comobv (int32 val);
308 int32 dt_csum (UNIT *uptr, int32 blk);
309 int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos);
310 extern int32 sim_is_running;
311
312 /* DT data structures
313
314 dt_dev DT device descriptor
315 dt_unit DT unit list
316 dt_reg DT register list
317 dt_mod DT modifier list
318 */
319
320 DIB dt_dib = {
321 IOBA_TC, IOLN_TC, &dt_rd, &dt_wr,
322 1, IVCL (DTA), VEC_DTA, { NULL }
323 };
324
325 UNIT dt_unit[] = {
326 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
327 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
328 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
329 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
330 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
331 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
332 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
333 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
334 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
335 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
336 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
337 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
338 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
339 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
340 { UDATA (&dt_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
341 UNIT_ROABLE+UNIT_11FMT, DT_CAPAC) },
342 { UDATA (&dt_svcdone, UNIT_DIS, 0) }
343 };
344
345 #define DT_TIMER (DT_NUMDR)
346
347 REG dt_reg[] = {
348 { ORDATA (TCST, tcst, 16) },
349 { ORDATA (TCCM, tccm, 16) },
350 { ORDATA (TCWC, tcwc, 16) },
351 { ORDATA (TCBA, tcba, 16) },
352 { ORDATA (TCDT, tcdt, 16) },
353 { FLDATA (INT, IREQ (DTA), INT_V_DTA) },
354 { FLDATA (ERR, tccm, CSR_V_ERR) },
355 { FLDATA (DONE, tccm, CSR_V_DONE) },
356 { FLDATA (IE, tccm, CSR_V_DONE) },
357 { DRDATA (CTIME, dt_ctime, 31), REG_NZ },
358 { DRDATA (LTIME, dt_ltime, 31), REG_NZ },
359 { DRDATA (DCTIME, dt_dctime, 31), REG_NZ },
360 { ORDATA (SUBSTATE, dt_substate, 1) },
361 { DRDATA (LBLK, dt_logblk, 12), REG_HIDDEN },
362 { URDATA (POS, dt_unit[0].pos, 10, T_ADDR_W, 0,
363 DT_NUMDR, PV_LEFT | REG_RO) },
364 { URDATA (STATT, dt_unit[0].STATE, 8, 18, 0,
365 DT_NUMDR, REG_RO) },
366 { URDATA (LASTT, dt_unit[0].LASTT, 10, 32, 0,
367 DT_NUMDR, REG_HRO) },
368 { FLDATA (STOP_OFFR, dt_stopoffr, 0) },
369 { ORDATA (DEVADDR, dt_dib.ba, 32), REG_HRO },
370 { ORDATA (DEVVEC, dt_dib.vec, 16), REG_HRO },
371 { NULL }
372 };
373
374 MTAB dt_mod[] = {
375 { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
376 { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
377 { UNIT_8FMT + UNIT_11FMT, 0, "18b", NULL, NULL },
378 { UNIT_8FMT + UNIT_11FMT, UNIT_8FMT, "12b", NULL, NULL },
379 { UNIT_8FMT + UNIT_11FMT, UNIT_11FMT, "16b", NULL, NULL },
380 { MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
381 &set_addr, &show_addr, NULL },
382 { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
383 &set_vec, &show_vec, NULL },
384 { 0 }
385 };
386
387 DEBTAB dt_deb[] = {
388 { "MOTION", LOG_MS },
389 { "DATA", LOG_RW },
390 { "BLOCK", LOG_BL },
391 { NULL, 0 }
392 };
393
394 DEVICE dt_dev = {
395 "TC", dt_unit, dt_reg, dt_mod,
396 DT_NUMDR + 1, 8, 24, 1, 8, 18,
397 NULL, NULL, &dt_reset,
398 &dt_boot, &dt_attach, &dt_detach,
399 &dt_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0,
400 dt_deb, NULL, NULL
401 };
402
403 /* IO dispatch routines, I/O addresses 17777340 - 17777350 */
404
405 t_stat dt_rd (int32 *data, int32 PA, int32 access)
406 {
407 int32 j, unum, mot, fnc;
408
409 j = (PA >> 1) & 017; /* get reg offset */
410 unum = CSR_GETUNIT (tccm); /* get drive */
411 switch (j) {
412
413 case 000: /* TCST */
414 mot = DTS_GETMOT (dt_unit[unum].STATE); /* get motion */
415 if (mot >= DTS_ATSF) tcst = tcst | STA_UPS; /* set/clr speed */
416 else tcst = tcst & ~STA_UPS;
417 *data = tcst;
418 break;
419
420 case 001: /* TCCM */
421 if (tcst & STA_ALLERR) tccm = tccm | CSR_ERR; /* set/clr error */
422 else tccm = tccm & ~CSR_ERR;
423 *data = tccm;
424 break;
425
426 case 002: /* TCWC */
427 *data = tcwc;
428 break;
429
430 case 003: /* TCBA */
431 *data = tcba;
432 break;
433
434 case 004: /* TCDT */
435 fnc = DTS_GETFNC (dt_unit[unum].STATE); /* get function */
436 if (fnc == FNC_RALL) { /* read all? */
437 DT_CLRDONE; /* clear done */
438 }
439 *data = tcdt;
440 break;
441 }
442
443 return SCPE_OK;
444 }
445
446 t_stat dt_wr (int32 data, int32 PA, int32 access)
447 {
448 int32 i, j, unum, old_tccm, fnc;
449 UNIT *uptr;
450
451 j = (PA >> 1) & 017; /* get reg offset */
452 switch (j) {
453
454 case 000: /* TCST */
455 if ((access == WRITEB) && (PA & 1)) break;
456 tcst = (tcst & ~STA_RW) | (data & STA_RW);
457 break;
458
459 case 001: /* TCCM */
460 old_tccm = tccm; /* save prior */
461 if (access == WRITEB) data = (PA & 1)?
462 (tccm & 0377) | (data << 8): (tccm & ~0377) | data;
463 if ((data & CSR_IE) == 0) CLR_INT (DTA);
464 else if ((((tccm & CSR_IE) == 0) && (tccm & CSR_DONE)) ||
465 (data & CSR_DONE)) SET_INT (DTA);
466 tccm = (tccm & ~CSR_RW) | (data & CSR_RW);
467 if ((data & CSR_GO) && (tccm & CSR_DONE)) { /* new cmd? */
468 tcst = tcst & ~STA_ALLERR; /* clear errors */
469 tccm = tccm & ~(CSR_ERR | CSR_DONE); /* clear done, err */
470 CLR_INT (DTA); /* clear int */
471 if ((old_tccm ^ tccm) & CSR_UNIT) dt_deselect (old_tccm);
472 unum = CSR_GETUNIT (tccm); /* get drive */
473 fnc = CSR_GETFNC (tccm); /* get function */
474 if (fnc == FNC_STOP) { /* stop all? */
475 sim_activate (&dt_dev.units[DT_TIMER], dt_ctime);
476 for (i = 0; i < DT_NUMDR; i++)
477 dt_stopunit (dt_dev.units + i); /* stop unit */
478 break;
479 }
480 uptr = dt_dev.units + unum;
481 if (uptr->flags & UNIT_DIS) /* disabled? */
482 dt_seterr (uptr, STA_SEL); /* select err */
483 if ((fnc == FNC_WMRK) || /* write mark? */
484 ((fnc == FNC_WALL) && (uptr->flags & UNIT_WPRT)) ||
485 ((fnc == FNC_WRIT) && (uptr->flags & UNIT_WPRT)))
486 dt_seterr (uptr, STA_ILO); /* illegal op */
487 if (!(tccm & CSR_ERR)) dt_newsa (tccm);
488 }
489 else if ((tccm & CSR_ERR) == 0) { /* clear err? */
490 tcst = tcst & ~STA_RWERR;
491 if (tcst & STA_ALLERR) tccm = tccm | CSR_ERR;
492 }
493 break;
494
495 case 002: /* TCWC */
496 tcwc = data; /* word write only! */
497 break;
498
499 case 003: /* TCBA */
500 tcba = data; /* word write only! */
501 break;
502
503 case 004: /* TCDT */
504 unum = CSR_GETUNIT (tccm); /* get drive */
505 fnc = DTS_GETFNC (dt_unit[unum].STATE); /* get function */
506 if (fnc == FNC_WALL) { /* write all? */
507 DT_CLRDONE; /* clear done */
508 }
509 tcdt = data; /* word write only! */
510 break;
511 }
512
513 return SCPE_OK;
514 }
515
516 /* Unit deselect */
517
518 void dt_deselect (int32 oldf)
519 {
520 int32 old_unit = CSR_GETUNIT (oldf);
521 UNIT *uptr = dt_dev.units + old_unit;
522 int32 old_mot = DTS_GETMOT (uptr->STATE);
523
524 if (old_mot >= DTS_ATSF) /* at speed? */
525 dt_newfnc (uptr, DTS_STA (old_mot, DTS_OFR));
526 else if (old_mot >= DTS_ACCF) /* accelerating? */
527 DTS_SET2ND (DTS_ATSF | (old_mot & DTS_DIR), DTS_OFR);
528 return;
529 }
530
531 /* New operation
532
533 1. If function = stop
534 - if not already stopped or decelerating, schedule deceleration
535 - schedule command completion
536 2. If change in direction,
537 - if not decelerating, schedule deceleration
538 - set accelerating (other dir) as next state
539 - set function as next next state
540 3. If not accelerating or at speed,
541 - schedule acceleration
542 - set function as next state
543 4. If not yet at speed,
544 - set function as next state
545 5. If at speed,
546 - set function as current state, schedule function
547 */
548
549 void dt_newsa (int32 newf)
550 {
551 int32 new_unit, prev_mot, new_fnc;
552 int32 prev_dir, new_dir;
553 UNIT *uptr;
554
555 new_unit = CSR_GETUNIT (newf); /* new, old units */
556 uptr = dt_dev.units + new_unit;
557 if ((uptr->flags & UNIT_ATT) == 0) { /* new unit attached? */
558 dt_seterr (uptr, STA_SEL); /* no, error */
559 return;
560 }
561 prev_mot = DTS_GETMOT (uptr->STATE); /* previous motion */
562 prev_dir = prev_mot & DTS_DIR; /* previous dir */
563 new_fnc = CSR_GETFNC (newf); /* new function */
564 new_dir = (newf & CSR_DIR) != 0; /* new di? */
565
566 if (new_fnc == FNC_SSEL) { /* stop unit? */
567 sim_activate (&dt_dev.units[DT_TIMER], dt_ctime); /* sched done */
568 dt_stopunit (uptr); /* stop unit */
569 return;
570 }
571
572 if (prev_mot == DTS_STOP) { /* start? */
573 if (dt_setpos (uptr)) return; /* update pos */
574 sim_cancel (uptr); /* stop current */
575 sim_activate (uptr, dt_dctime - (dt_dctime >> 2)); /* sched accel */
576 DTS_SETSTA (DTS_ACCF | new_dir, 0); /* state = accel */
577 DTS_SET2ND (DTS_ATSF | new_dir, new_fnc); /* next = fnc */
578 return;
579 }
580
581 if (prev_dir ^ new_dir) { /* dir chg? */
582 dt_stopunit (uptr); /* stop unit */
583 DTS_SET2ND (DTS_ACCF | new_dir, 0); /* next = accel */
584 DTS_SET3RD (DTS_ATSF | new_dir, new_fnc); /* next next = fnc */
585 return;
586 }
587
588 if (prev_mot < DTS_ACCF) { /* not accel/at speed? */
589 if (dt_setpos (uptr)) return; /* update pos */
590 sim_cancel (uptr); /* cancel cur */
591 sim_activate (uptr, dt_dctime - (dt_dctime >> 2)); /* sched accel */
592 DTS_SETSTA (DTS_ACCF | new_dir, 0); /* state = accel */
593 DTS_SET2ND (DTS_ATSF | new_dir, new_fnc); /* next = fnc */
594 return;
595 }
596
597 if (prev_mot < DTS_ATSF) { /* not at speed? */
598 DTS_SET2ND (DTS_ATSF | new_dir, new_fnc); /* next = fnc */
599 return;
600 }
601
602 dt_newfnc (uptr, DTS_STA (DTS_ATSF | new_dir, new_fnc));/* state = fnc */
603 return;
604 }
605
606 /* Schedule new DECtape function
607
608 This routine is only called if
609 - the selected unit is attached
610 - the selected unit is at speed (forward or backward)
611
612 This routine
613 - updates the selected unit's position
614 - updates the selected unit's state
615 - schedules the new operation
616 */
617
618 void dt_newfnc (UNIT *uptr, int32 newsta)
619 {
620 int32 fnc, dir, blk, unum, relpos, newpos;
621 uint32 oldpos;
622
623 oldpos = uptr->pos; /* save old pos */
624 if (dt_setpos (uptr)) return; /* update pos */
625 uptr->STATE = newsta; /* update state */
626 fnc = DTS_GETFNC (uptr->STATE); /* set variables */
627 dir = DTS_GETMOT (uptr->STATE) & DTS_DIR;
628 unum = (int32) (uptr - dt_dev.units);
629 if (oldpos == uptr->pos)
630 uptr->pos = uptr->pos + (dir? -1: 1);
631 blk = DT_LIN2BL (uptr->pos, uptr);
632
633 if (dir? DT_QREZ (uptr): DT_QFEZ (uptr)) { /* wrong ez? */
634 dt_seterr (uptr, STA_END); /* set ez flag, stop */
635 return;
636 }
637 dt_substate = 0; /* substate = normal */
638 sim_cancel (uptr); /* cancel cur op */
639 switch (fnc) { /* case function */
640
641 case DTS_OFR: /* off reel */
642 if (dir) newpos = -1000; /* rev? < start */
643 else newpos = DTU_FWDEZ (uptr) + DT_EZLIN + 1000; /* fwd? > end */
644 break;
645
646 case FNC_SRCH: /* search */
647 if (dir) newpos = DT_BLK2LN ((DT_QFEZ (uptr)?
648 DTU_TSIZE (uptr): blk), uptr) - DT_BLKLN - DT_WSIZE;
649 else newpos = DT_BLK2LN ((DT_QREZ (uptr)?
650 0: blk + 1), uptr) + DT_BLKLN + (DT_WSIZE - 1);
651 if (DEBUG_PRI (dt_dev, LOG_MS)) fprintf (sim_deb, ">>DT%d: searching %s\n",
652 unum, (dir? "backward": "forward"));
653 break;
654
655 case FNC_WRIT: /* write */
656 case FNC_READ: /* read */
657 if (DT_QEZ (uptr)) { /* in "ok" end zone? */
658 if (dir) newpos = DTU_FWDEZ (uptr) - DT_HTLIN - DT_WSIZE;
659 else newpos = DT_EZLIN + DT_HTLIN + (DT_WSIZE - 1);
660 break;
661 }
662 relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
663 if ((relpos >= DT_HTLIN) && /* in data zone? */
664 (relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
665 dt_seterr (uptr, STA_BLKM);
666 return;
667 }
668 if (dir) newpos = DT_BLK2LN (((relpos >= (DTU_LPERB (uptr) - DT_HTLIN))?
669 blk + 1: blk), uptr) - DT_HTLIN - DT_WSIZE;
670 else newpos = DT_BLK2LN (((relpos < DT_HTLIN)?
671 blk: blk + 1), uptr) + DT_HTLIN + (DT_WSIZE - 1);
672 if (DEBUG_PRI (dt_dev, LOG_RW) ||
673 (DEBUG_PRI (dt_dev, LOG_BL) && (blk == dt_logblk)))
674 fprintf (sim_deb, ">>DT%d: %s block %d %s\n",
675 unum, ((fnc == FNC_READ)? "read": "write"),
676 blk, (dir? "backward": "forward"));
677 break;
678
679 case FNC_RALL: /* read all */
680 case FNC_WALL: /* write all */
681 if (DT_QEZ (uptr)) { /* in "ok" end zone? */
682 if (dir) newpos = DTU_FWDEZ (uptr) - DT_WSIZE;
683 else newpos = DT_EZLIN + (DT_WSIZE - 1);
684 }
685 else {
686 relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
687 if (dir? (relpos < (DTU_LPERB (uptr) - DT_CSMLN)): /* switch in time? */
688 (relpos >= DT_CSMLN)) {
689 dt_seterr (uptr, STA_BLKM);
690 return;
691 }
692 if (dir) newpos = DT_BLK2LN (blk + 1, uptr) - DT_CSMLN - DT_WSIZE;
693 else newpos = DT_BLK2LN (blk, uptr) + DT_CSMLN + (DT_WSIZE - 1);
694 }
695 if (fnc == FNC_WALL) sim_activate /* write all? */
696 (&dt_dev.units[DT_TIMER], dt_ctime); /* sched done */
697 if (DEBUG_PRI (dt_dev, LOG_RW) ||
698 (DEBUG_PRI (dt_dev, LOG_BL) && (blk == dt_logblk)))
699 fprintf (sim_deb, ">>DT%d: read all block %d %s\n",
700 unum, blk, (dir? "backward": "forward"));
701 break;
702
703 default:
704 dt_seterr (uptr, STA_SEL); /* bad state */
705 return;
706 }
707
708 sim_activate (uptr, ABS (newpos - ((int32) uptr->pos)) * dt_ltime);
709 return;
710 }
711
712 /* Update DECtape position
713
714 DECtape motion is modeled as a constant velocity, with linear
715 acceleration and deceleration. The motion equations are as follows:
716
717 t = time since operation started
718 tmax = time for operation (accel, decel only)
719 v = at speed velocity in lines (= 1/dt_ltime)
720
721 Then:
722 at speed dist = t * v
723 accel dist = (t^2 * v) / (2 * tmax)
724 decel dist = (((2 * t * tmax) - t^2) * v) / (2 * tmax)
725
726 This routine uses the relative (integer) time, rather than the absolute
727 (floating point) time, to allow save and restore of the start times.
728 */
729
730 t_bool dt_setpos (UNIT *uptr)
731 {
732 uint32 new_time, ut, ulin, udelt;
733 int32 mot = DTS_GETMOT (uptr->STATE);
734 int32 unum, delta;
735
736 new_time = sim_grtime (); /* current time */
737 ut = new_time - uptr->LASTT; /* elapsed time */
738 if (ut == 0) return FALSE; /* no time gone? exit */
739 uptr->LASTT = new_time; /* update last time */
740 switch (mot & ~DTS_DIR) { /* case on motion */
741
742 case DTS_STOP: /* stop */
743 delta = 0;
744 break;
745
746 case DTS_DECF: /* slowing */
747 ulin = ut / (uint32) dt_ltime;
748 udelt = dt_dctime / dt_ltime;
749 delta = ((ulin * udelt * 2) - (ulin * ulin)) / (2 * udelt);
750 break;
751
752 case DTS_ACCF: /* accelerating */
753 ulin = ut / (uint32) dt_ltime;
754 udelt = (dt_dctime - (dt_dctime >> 2)) / dt_ltime;
755 delta = (ulin * ulin) / (2 * udelt);
756 break;
757
758 case DTS_ATSF: /* at speed */
759 delta = ut / (uint32) dt_ltime;
760 break;
761 }
762
763 if (mot & DTS_DIR) uptr->pos = uptr->pos - delta; /* update pos */
764 else uptr->pos = uptr->pos + delta;
765 if (((int32) uptr->pos < 0) ||
766 ((int32) uptr->pos > (DTU_FWDEZ (uptr) + DT_EZLIN))) {
767 detach_unit (uptr); /* off reel? */
768 uptr->STATE = uptr->pos = 0;
769 unum = (int32) (uptr - dt_dev.units);
770 if ((unum == CSR_GETUNIT (tccm)) && (CSR_GETFNC (tccm) != FNC_STOP))
771 dt_seterr (uptr, STA_SEL); /* error */
772 return TRUE;
773 }
774 return FALSE;
775 }
776
777 /* Command timer service after stop - set done */
778
779 t_stat dt_svcdone (UNIT *uptr)
780 {
781 DT_SETDONE;
782 return SCPE_OK;
783 }
784
785 /* Unit service
786
787 Unit must be attached, detach cancels operation
788 */
789
790 t_stat dt_svc (UNIT *uptr)
791 {
792 int32 mot = DTS_GETMOT (uptr->STATE);
793 int32 dir = mot & DTS_DIR;
794 int32 fnc = DTS_GETFNC (uptr->STATE);
795 int32 *fbuf = (int32 *) uptr->filebuf;
796 int32 blk, wrd, relpos, dat;
797 uint32 ba, ma;
798 uint16 wbuf;
799
800 /* Motion cases
801
802 Decelerating - if next state != stopped, must be accel reverse
803 Accelerating - next state must be @speed, schedule function
804 At speed - do functional processing
805 */
806
807 switch (mot) {
808
809 case DTS_DECF: case DTS_DECR: /* decelerating */
810 if (dt_setpos (uptr)) /* upd pos; off reel? */
811 return IORETURN (dt_stopoffr, STOP_DTOFF);
812 uptr->STATE = DTS_NXTSTA (uptr->STATE); /* advance state */
813 if (uptr->STATE) /* not stopped? */
814 sim_activate (uptr, dt_dctime - (dt_dctime >> 2)); /* reversing */
815 return SCPE_OK;
816
817 case DTS_ACCF: case DTS_ACCR: /* accelerating */
818 dt_newfnc (uptr, DTS_NXTSTA (uptr->STATE)); /* adv state, sched */
819 return SCPE_OK;
820
821 case DTS_ATSF: case DTS_ATSR: /* at speed */
822 break; /* check function */
823
824 default: /* other */
825 dt_seterr (uptr, STA_SEL); /* state error */
826 return SCPE_OK;
827 }
828
829 /* Functional cases
830
831 Search - transfer block number, schedule next block
832 Off reel - detach unit (it must be deselected)
833 */
834
835 if (dt_setpos (uptr)) /* upd pos; off reel? */
836 return IORETURN (dt_stopoffr, STOP_DTOFF);
837 if (DT_QEZ (uptr)) { /* in end zone? */
838 dt_seterr (uptr, STA_END); /* end zone error */
839 return SCPE_OK;
840 }
841 blk = DT_LIN2BL (uptr->pos, uptr); /* get block # */
842
843 switch (fnc) { /* at speed, check fnc */
844
845 case FNC_SRCH: /* search */
846 tcdt = blk; /* set block # */
847 dt_schedez (uptr, dir); /* sched end zone */
848 DT_SETDONE; /* set done */
849 break;
850
851 case DTS_OFR: /* off reel */
852 detach_unit (uptr); /* must be deselected */
853 uptr->STATE = uptr->pos = 0; /* no visible action */
854 break;
855
856 /* Read
857
858 If wc ovf has not occurred, inc ma, wc and copy word from tape to memory
859 If wc ovf, set flag
860 If not end of block, schedule next word
861 If end of block and not wc ovf, schedule next block
862 If end of block and wc ovf, set done, schedule end zone
863 */
864
865 case FNC_READ: /* read */
866 wrd = DT_LIN2WD (uptr->pos, uptr); /* get word # */
867 if (!dt_substate) { /* !wc ovf? */
868 ma = (CSR_GETMEX (tccm) << 16) | tcba; /* form 18b addr */
869 ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
870 tcdt = wbuf = fbuf[ba] & DMASK; /* read word */
871 tcst = (tcst & ~STA_M_XD) | ((fbuf[ma] >> 16) & STA_M_XD);
872 if (Map_WriteW (ma, 2, &wbuf)) { /* store, nxm? */
873 dt_seterr (uptr, STA_NXM);
874 break;
875 }
876 tcwc = (tcwc + 1) & DMASK; /* incr MA, WC */
877 tcba = (tcba + 2) & DMASK;
878 if (tcba <= 1) tccm = CSR_INCMEX (tccm);
879 if (tcwc == 0) dt_substate = 1;
880 }
881 if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not end blk? */
882 sim_activate (uptr, DT_WSIZE * dt_ltime);
883 else if (dt_substate) { /* wc ovf? */
884 dt_schedez (uptr, dir); /* sched end zone */
885 DT_SETDONE; /* set done */
886 }
887 else sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
888 break;
889
890 /* Write
891
892 If wc ovf has not occurred, inc ma, wc
893 Copy word from memory (or 0, to fill block) to tape
894 If wc ovf, set flag
895 If not end of block, schedule next word
896 If end of block and not wc ovf, schedule next block
897 If end of block and wc ovf, set done, schedule end zone
898 */
899
900 case FNC_WRIT: /* write */
901 wrd = DT_LIN2WD (uptr->pos, uptr); /* get word # */
902 if (dt_substate) tcdt = 0; /* wc ovf? fill */
903 else {
904 ma = (CSR_GETMEX (tccm) << 16) | tcba; /* form 18b addr */
905 if (Map_ReadW (ma, 2, &wbuf)) { /* fetch word */
906 dt_seterr (uptr, STA_NXM);
907 break;
908 }
909 tcdt = wbuf; /* get word */
910 tcwc = (tcwc + 1) & DMASK; /* incr MA, WC */
911 tcba = (tcba + 2) & DMASK;
912 if (tcba <= 1) tccm = CSR_INCMEX (tccm);
913 }
914 ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
915 fbuf[ba] = tcdt; /* write word */
916 if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
917 if (tcwc == 0) dt_substate = 1;
918 if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not end blk? */
919 sim_activate (uptr, DT_WSIZE * dt_ltime);
920 else if (dt_substate) { /* wc ovf? */
921 dt_schedez (uptr, dir); /* sched end zone */
922 DT_SETDONE;
923 }
924 else sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
925 break;
926
927 /* Read all - read current header or data word */
928
929 case FNC_RALL:
930 if (tccm & CSR_DONE) { /* done set? */
931 dt_seterr (uptr, STA_DATM); /* data miss */
932 break;
933 }
934 relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
935 if ((relpos >= DT_HTLIN) && /* in data zone? */
936 (relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
937 wrd = DT_LIN2WD (uptr->pos, uptr);
938 ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
939 dat = fbuf[ba]; /* get tape word */
940 }
941 else dat = dt_gethdr (uptr, blk, relpos); /* get hdr */
942 if (dir) dat = dt_comobv (dat); /* rev? comp obv */
943 tcdt = dat & DMASK; /* low 16b */
944 tcst = (tcst & ~STA_M_XD) | ((dat >> 16) & STA_M_XD);
945 sim_activate (uptr, DT_WSIZE * dt_ltime);
946 DT_SETDONE; /* set done */
947 break;
948
949 /* Write all - write current header or data word */
950
951 case FNC_WALL:
952 if (tccm & CSR_DONE) { /* done set? */
953 dt_seterr (uptr, STA_DATM); /* data miss */
954 break;
955 }
956 relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
957 if ((relpos >= DT_HTLIN) && /* in data zone? */
958 (relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
959 wrd = DT_LIN2WD (uptr->pos, uptr);
960 dat = (STA_GETXD (tcst) << 16) | tcdt; /* get data word */
961 if (dir) dat = dt_comobv (dat); /* rev? comp obv */
962 ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
963 fbuf[ba] = dat; /* write word */
964 if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
965 }
966 /* else /* ignore hdr */
967 sim_activate (uptr, DT_WSIZE * dt_ltime);
968 DT_SETDONE; /* set done */
969 break;
970
971 default:
972 dt_seterr (uptr, STA_SEL); /* impossible state */
973 break;
974 }
975 return SCPE_OK;
976 }
977
978 /* Utility routines */
979
980 /* Set error flag */
981
982 void dt_seterr (UNIT *uptr, int32 e)
983 {
984 int32 mot = DTS_GETMOT (uptr->STATE);
985
986 tcst = tcst | e; /* set error flag */
987 tccm = tccm | CSR_ERR;
988 if (!(tccm & CSR_DONE)) { /* not done? */
989 DT_SETDONE;
990 }
991 if (mot >= DTS_ACCF) { /* ~stopped or stopping? */
992 sim_cancel (uptr); /* cancel activity */
993 if (dt_setpos (uptr)) return; /* update position */
994 sim_activate (uptr, dt_dctime); /* sched decel */
995 DTS_SETSTA (DTS_DECF | (mot & DTS_DIR), 0); /* state = decel */
996 }
997 return;
998 }
999
1000 /* Stop unit */
1001
1002 void dt_stopunit (UNIT *uptr)
1003 {
1004 int32 mot = DTS_GETMOT (uptr->STATE);
1005 int32 dir = mot & DTS_DIR;
1006
1007 if (mot == DTS_STOP) return; /* already stopped? */
1008 if ((mot & ~DTS_DIR) != DTS_DECF) { /* !already stopping? */
1009 if (dt_setpos (uptr)) return; /* update pos */
1010 sim_cancel (uptr); /* stop current */
1011 sim_activate (uptr, dt_dctime); /* schedule decel */
1012 }
1013 DTS_SETSTA (DTS_DECF | dir, 0); /* state = decel */
1014 return;
1015 }
1016
1017 /* Schedule end zone */
1018
1019 void dt_schedez (UNIT *uptr, int32 dir)
1020 {
1021 int32 newpos;
1022
1023 if (dir) newpos = DT_EZLIN - DT_WSIZE; /* rev? rev ez */
1024 else newpos = DTU_FWDEZ (uptr) + DT_WSIZE; /* fwd? fwd ez */
1025 sim_activate (uptr, ABS (newpos - ((int32) uptr->pos)) * dt_ltime);
1026 return;
1027 }
1028
1029 /* Complement obverse routine (18b) */
1030
1031 int32 dt_comobv (int32 dat)
1032 {
1033 dat = dat ^ 0777777; /* compl obverse */
1034 dat = ((dat >> 15) & 07) | ((dat >> 9) & 070) |
1035 ((dat >> 3) & 0700) | ((dat & 0700) << 3) |
1036 ((dat & 070) << 9) | ((dat & 07) << 15);
1037 return dat;
1038 }
1039
1040 /* Checksum routine */
1041
1042 int32 dt_csum (UNIT *uptr, int32 blk)
1043 {
1044 int32 *fbuf = (int32 *) uptr->filebuf;
1045 int32 ba = blk * DTU_BSIZE (uptr);
1046 int32 i, csum, wrd;
1047
1048 csum = 077; /* init csum */
1049 for (i = 0; i < DTU_BSIZE (uptr); i++) { /* loop thru buf */
1050 wrd = fbuf[ba + i] ^ 0777777; /* get ~word */
1051 csum = csum ^ (wrd >> 12) ^ (wrd >> 6) ^ wrd;
1052 }
1053 return (csum & 077);
1054 }
1055
1056 /* Get header word (18b) */
1057
1058 int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos)
1059 {
1060 int32 wrd = relpos / DT_WSIZE;
1061
1062 if (wrd == DT_BLKWD) return blk; /* fwd blknum */
1063 if (wrd == DT_CSMWD) return 077; /* rev csum */
1064 if (wrd == (2 * DT_HTWRD + DTU_BSIZE (uptr) - DT_CSMWD - 1)) /* fwd csum */
1065 return (dt_csum (uptr, blk) << 12);
1066 if (wrd == (2 * DT_HTWRD + DTU_BSIZE (uptr) - DT_BLKWD - 1)) /* rev blkno */
1067 return dt_comobv (blk);
1068 return 0; /* all others */
1069 }
1070
1071 /* Reset routine */
1072
1073 t_stat dt_reset (DEVICE *dptr)
1074 {
1075 int32 i, prev_mot;
1076 UNIT *uptr;
1077
1078 for (i = 0; i < DT_NUMDR; i++) { /* stop all activity */
1079 uptr = dt_dev.units + i;
1080 if (sim_is_running) { /* RESET? */
1081 prev_mot = DTS_GETMOT (uptr->STATE); /* get motion */
1082 if ((prev_mot & ~DTS_DIR) > DTS_DECF) { /* accel or spd? */
1083 if (dt_setpos (uptr)) continue; /* update pos */
1084 sim_cancel (uptr);
1085 sim_activate (uptr, dt_dctime); /* sched decel */
1086 DTS_SETSTA (DTS_DECF | (prev_mot & DTS_DIR), 0);
1087 }
1088 }
1089 else {
1090 sim_cancel (uptr); /* sim reset */
1091 uptr->STATE = 0;
1092 uptr->LASTT = sim_grtime ();
1093 }
1094 }
1095 tcst = tcwc = tcba = tcdt = 0; /* clear reg */
1096 tccm = CSR_DONE;
1097 CLR_INT (DTA); /* clear int req */
1098 return SCPE_OK;
1099 }
1100
1101 /* Device bootstrap */
1102
1103 #define BOOT_START 02000 /* start */
1104 #define BOOT_ENTRY (BOOT_START + 002) /* entry */
1105 #define BOOT_UNIT (BOOT_START + 010) /* unit number */
1106 #define BOOT_CSR (BOOT_START + 020) /* CSR */
1107 #define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))
1108
1109 static const uint16 boot_rom[] = {
1110 0042124, /* "TD" */
1111 0012706, BOOT_START, /* MOV #boot_start, SP */
1112 0012700, 0000000, /* MOV #unit, R0 ; unit number */
1113 0010003, /* MOV R0, R3 */
1114 0000303, /* SWAB R3 */
1115 0012701, 0177342, /* MOV #TCCM, R1 ; csr */
1116 0012702, 0004003, /* RW: MOV #4003, R2 ; rev+rnum+go */
1117 0050302, /* BIS R3, R2 */
1118 0010211, /* MOV R2, (R1) ; load csr */
1119 0032711, 0100200, /* BIT #100200, (R1) ; wait */
1120 0001775, /* BEQ .-4 */
1121 0100370, /* BPL RW ; no err, cont */
1122 0005761, 0177776, /* TST -2(R1) ; end zone? */
1123 0100036, /* BPL ER ; no, err */
1124 0012702, 0000003, /* MOV #3, R2 ; rnum+go */
1125 0050302, /* BIS R3, R2 */
1126 0010211, /* MOV R2, (R1) ; load csr */
1127 0032711, 0100200, /* BIT #100200, (R1) ; wait */
1128 0001775, /* BEQ .-4 */
1129 0100426, /* BMI ER ; err, die */
1130 0005761, 0000006, /* TST 6(R1) ; blk 0? */
1131 0001023, /* BNE ER ; no, die */
1132 0012761, 0177000, 0000002, /* MOV #-256.*2, 2(R1) ; load wc */
1133 0005061, 0000004, /* CLR 4(R1) ; clear ba */
1134 0012702, 0000005, /* MOV #READ+GO, R2 ; read & go */
1135 0050302, /* BIS R3, R2 */
1136 0010211, /* MOV R2, (R1) ; load csr */
1137 0005002, /* CLR R2 */
1138 0005003, /* CLR R3 */
1139 0012704, BOOT_START+020, /* MOV #START+20, R4 */
1140 0005005, /* CLR R5 */
1141 0032711, 0100200, /* BIT #100200, (R1) ; wait */
1142 0001775, /* BEQ .-4 */
1143 0100401, /* BMI ER ; err, die */
1144 0005007, /* CLR PC */
1145 0012711, 0000001, /* ER: MOV #1, (R1) ; stop all */
1146 0000000 /* HALT */
1147 };
1148
1149 t_stat dt_boot (int32 unitno, DEVICE *dptr)
1150 {
1151 int32 i;
1152 extern int32 saved_PC;
1153
1154 dt_unit[unitno].pos = DT_EZLIN;
1155 for (i = 0; i < BOOT_LEN; i++) M[(BOOT_START >> 1) + i] = boot_rom[i];
1156 M[BOOT_UNIT >> 1] = unitno & DT_M_NUMDR;
1157 M[BOOT_CSR >> 1] = (dt_dib.ba & DMASK) + 02;
1158 saved_PC = BOOT_ENTRY;
1159 return SCPE_OK;
1160 }
1161
1162 /* Attach routine
1163
1164 Determine 12b, 16b, or 18b/36b format
1165 Allocate buffer
1166 If 12b, read 12b format and convert to 18b in buffer
1167 If 16b, read 16b format and convert to 18b in buffer
1168 If 18b/36b, read data into buffer
1169 */
1170
1171 t_stat dt_attach (UNIT *uptr, char *cptr)
1172 {
1173 uint16 pdp8b[D8_NBSIZE];
1174 uint16 pdp11b[D18_BSIZE];
1175 uint32 ba, sz, k, *fbuf;
1176 int32 u = uptr - dt_dev.units;
1177 t_stat r;
1178
1179 r = attach_unit (uptr, cptr); /* attach */
1180 if (r != SCPE_OK) return r; /* fail? */
1181 if ((sim_switches & SIM_SW_REST) == 0) { /* not from rest? */
1182 uptr->flags = (uptr->flags | UNIT_11FMT) & ~UNIT_8FMT; /* default 16b */
1183 if (sim_switches & SWMASK ('T')) /* att 12b? */
1184 uptr->flags = (uptr->flags | UNIT_8FMT) & ~UNIT_11FMT;
1185 else if (sim_switches & SWMASK ('F')) /* att 18b? */
1186 uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT);
1187 else if (!(sim_switches & SWMASK ('A')) && /* autosize? */
1188 ((sz = sim_fsize (uptr->fileref)) > D16_FILSIZ)) {
1189 if (sz <= D8_FILSIZ)
1190 uptr->flags = (uptr->flags | UNIT_8FMT) & ~UNIT_11FMT;
1191 else uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT);
1192 }
1193 }
1194 uptr->capac = DTU_CAPAC (uptr); /* set capacity */
1195 uptr->filebuf = calloc (uptr->capac, sizeof (uint32));
1196 if (uptr->filebuf == NULL) { /* can't alloc? */
1197 detach_unit (uptr);
1198 return SCPE_MEM;
1199 }
1200 fbuf = (uint32 *) uptr->filebuf; /* file buffer */
1201 printf ("%s%d: ", sim_dname (&dt_dev), u);
1202 if (uptr->flags & UNIT_8FMT) printf ("12b format");
1203 else if (uptr->flags & UNIT_11FMT) printf ("16b format");
1204 else printf ("18b/36b format");
1205 printf (", buffering file in memory\n");
1206 if (uptr->flags & UNIT_8FMT) { /* 12b? */
1207 for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
1208 k = fxread (pdp8b, sizeof (int16), D8_NBSIZE, uptr->fileref);
1209 if (k == 0) break;
1210 for ( ; k < D8_NBSIZE; k++) pdp8b[k] = 0;
1211 for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop thru blk */
1212 fbuf[ba] = ((uint32) (pdp8b[k] & 07777) << 6) |
1213 ((uint32) (pdp8b[k + 1] >> 6) & 077);
1214 fbuf[ba + 1] = ((uint32) (pdp8b[k + 1] & 077) << 12) |
1215 ((uint32) pdp8b[k + 2] & 07777);
1216 ba = ba + 2;
1217 } /* end blk loop */
1218 } /* end file loop */
1219 uptr->hwmark = ba;
1220 } /* end if */
1221 else if (uptr->flags & UNIT_11FMT) { /* 16b? */
1222 for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
1223 k = fxread (pdp11b, sizeof (uint16), D18_BSIZE, uptr->fileref);
1224 if (k == 0) break;
1225 for ( ; k < D18_BSIZE; k++) pdp11b[k] = 0;
1226 for (k = 0; k < D18_BSIZE; k++)
1227 fbuf[ba++] = pdp11b[k];
1228 }
1229 uptr->hwmark = ba;
1230 } /* end elif */
1231 else uptr->hwmark = fxread (uptr->filebuf, sizeof (uint32),
1232 uptr->capac, uptr->fileref);
1233 uptr->flags = uptr->flags | UNIT_BUF; /* set buf flag */
1234 uptr->pos = DT_EZLIN; /* beyond leader */
1235 uptr->LASTT = sim_grtime (); /* last pos update */
1236 return SCPE_OK;
1237 }
1238
1239 /* Detach routine
1240
1241 Cancel in progress operation
1242 If 12b, convert 18b buffer to 12b and write to file
1243 If 16b, convert 18b buffer to 16b and write to file
1244 If 18b/36b, write buffer to file
1245 Deallocate buffer
1246 */
1247
1248 t_stat dt_detach (UNIT* uptr)
1249 {
1250 uint16 pdp8b[D8_NBSIZE];
1251 uint16 pdp11b[D18_BSIZE];
1252 uint32 ba, k, *fbuf;
1253 int32 u = uptr - dt_dev.units;
1254
1255 if (!(uptr->flags & UNIT_ATT)) return SCPE_OK;
1256 if (sim_is_active (uptr)) { /* active? cancel op */
1257 sim_cancel (uptr);
1258 if ((u == CSR_GETUNIT (tccm)) && ((tccm & CSR_DONE) == 0)) {
1259 tcst = tcst | STA_SEL;
1260 tccm = tccm | CSR_ERR | CSR_DONE;
1261 if (tccm & CSR_IE) SET_INT (DTA);
1262 }
1263 uptr->STATE = uptr->pos = 0;
1264 }
1265 fbuf = (uint32 *) uptr->filebuf; /* file buffer */
1266 if (uptr->hwmark && ((uptr->flags & UNIT_RO) == 0)) { /* any data? */
1267 printf ("%s%d: writing buffer to file\n", sim_dname (&dt_dev), u);
1268 rewind (uptr->fileref); /* start of file */
1269 if (uptr->flags & UNIT_8FMT) { /* 12b? */
1270 for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
1271 for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop blk */
1272 pdp8b[k] = (fbuf[ba] >> 6) & 07777;
1273 pdp8b[k + 1] = ((fbuf[ba] & 077) << 6) |
1274 ((fbuf[ba + 1] >> 12) & 077);
1275 pdp8b[k + 2] = fbuf[ba + 1] & 07777;
1276 ba = ba + 2;
1277 } /* end loop blk */
1278 fxwrite (pdp8b, sizeof (uint16), D8_NBSIZE, uptr->fileref);
1279 if (ferror (uptr->fileref)) break;
1280 } /* end loop file */
1281 } /* end if 12b */
1282 else if (uptr->flags & UNIT_11FMT) { /* 16b? */
1283 for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
1284 for (k = 0; k < D18_BSIZE; k++) /* loop blk */
1285 pdp11b[k] = fbuf[ba++] & DMASK;
1286 fxwrite (pdp11b, sizeof (uint16), D18_BSIZE, uptr->fileref);
1287 if (ferror (uptr->fileref)) break;
1288 } /* end loop file */
1289 } /* end if 16b */
1290 else fxwrite (uptr->filebuf, sizeof (uint32), /* write file */
1291 uptr->hwmark, uptr->fileref);
1292 if (ferror (uptr->fileref)) perror ("I/O error");
1293 } /* end if hwmark */
1294 free (uptr->filebuf); /* release buf */
1295 uptr->flags = uptr->flags & ~UNIT_BUF; /* clear buf flag */
1296 uptr->filebuf = NULL; /* clear buf ptr */
1297 uptr->flags = (uptr->flags | UNIT_11FMT) & ~UNIT_8FMT; /* default fmt */
1298 uptr->capac = DT_CAPAC; /* default size */
1299 return detach_unit (uptr);
1300 }
Magically enhanced SIMH