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First Commit of my working state
[simh.git] / PDP11 / pdp11_ts.c
1 /* pdp11_ts.c: TS11/TSV05 magnetic tape simulator
2
3 Copyright (c) 1993-2006, Robert M Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 ts TS11/TSV05 magtape
27
28 16-Feb-06 RMS Added tape capacity checking
29 31-Oct-05 RMS Fixed address width for large files
30 16-Aug-05 RMS Fixed C++ declaration and cast problems
31 07-Jul-05 RMS Removed extraneous externs
32 18-Mar-05 RMS Added attached test to detach routine
33 07-Dec-04 RMS Added read-only file support
34 30-Sep-04 RMS Revised Unibus interface
35 25-Jan-04 RMS Revised for device debug support
36 19-May-03 RMS Revised for new conditional compilation scheme
37 25-Apr-03 RMS Revised for extended file support
38 28-Mar-03 RMS Added multiformat support
39 28-Feb-03 RMS Revised to use magtape library
40 30-Sep-02 RMS Added variable address support to bootstrap
41 Added vector change/display support
42 Fixed CTL unload/clean decode
43 Implemented XS0_MOT in extended status
44 New data structures, revamped error recovery
45 28-Aug-02 RMS Added end of medium support
46 30-May-02 RMS Widened POS to 32b
47 22-Apr-02 RMS Added maximum record length protection
48 04-Apr-02 RMS Fixed bug in residual frame count after space operation
49 16-Feb-02 RMS Fixed bug in message header logic
50 26-Jan-02 RMS Revised bootstrap to conform to M9312
51 06-Jan-02 RMS Revised enable/disable support
52 30-Nov-01 RMS Added read only unit, extended SET/SHOW support
53 09-Nov-01 RMS Added bus map, VAX support
54 15-Oct-01 RMS Integrated debug logging across simulator
55 27-Sep-01 RMS Implemented extended characteristics and status
56 Fixed bug in write characteristics status return
57 19-Sep-01 RMS Fixed bug in bootstrap
58 15-Sep-01 RMS Fixed bug in NXM test
59 07-Sep-01 RMS Revised device disable and interrupt mechanism
60 13-Jul-01 RMS Fixed bug in space reverse (found by Peter Schorn)
61
62 Magnetic tapes are represented as a series of variable 8b records
63 of the form:
64
65 32b record length in bytes - exact number
66 byte 0
67 byte 1
68 :
69 byte n-2
70 byte n-1
71 32b record length in bytes - exact number
72
73 If the byte count is odd, the record is padded with an extra byte
74 of junk. File marks are represented by a single record length of 0.
75 End of tape is two consecutive end of file marks.
76
77 The TS11 functions in three environments:
78
79 - PDP-11 Q22 systems - the I/O map is one for one, so it's safe to
80 go through the I/O map
81 - PDP-11 Unibus 22b systems - the TS11 behaves as an 18b Unibus
82 peripheral and must go through the I/O map
83 - VAX Q22 systems - the TS11 must go through the I/O map
84 */
85
86 #if defined (VM_PDP10) /* PDP10 version */
87 #error "TS11 not supported on PDP10!"
88
89 #elif defined (VM_VAX) /* VAX version */
90 #include "vax_defs.h"
91 #define TS_DIS 0 /* on by default */
92 #define DMASK 0xFFFF
93
94 #else /* PDP-11 version */
95 #include "pdp11_defs.h"
96 #define TS_DIS DEV_DIS /* off by default */
97 extern int32 cpu_opt;
98 #endif
99
100 #include "sim_tape.h"
101 #define ADDRTEST (UNIBUS? 0177774: 0177700)
102
103 /* TSBA/TSDB - 17772520: base address/data buffer register
104
105 read: most recent memory address
106 write word: initiate command
107 write byte: diagnostic use
108 */
109
110 /* TSSR - 17772522: subsystem status register
111 TSDBX - 17772523: extended address register
112
113 read: return status
114 write word: initialize
115 write byte: if odd, set extended packet address register
116 */
117
118 #define TSSR_SC 0100000 /* special condition */
119 #define TSSR_RMR 0010000 /* reg mod refused */
120 #define TSSR_NXM 0004000 /* nxm */
121 #define TSSR_NBA 0002000 /* need buf addr */
122 #define TSSR_V_EMA 8 /* mem addr<17:16> */
123 #define TSSR_EMA 0001400
124 #define TSSR_SSR 0000200 /* subsystem ready */
125 #define TSSR_OFL 0000100 /* offline */
126 #define TSSR_V_TC 1 /* term class */
127 #define TSSR_M_TC 07
128 #define TSSR_TC (TSSR_M_TC << TSSR_V_TC)
129 #define TC0 (0 << TSSR_V_TC) /* ok */
130 #define TC1 (1 << TSSR_V_TC) /* attention */
131 #define TC2 (2 << TSSR_V_TC) /* status alert */
132 #define TC3 (3 << TSSR_V_TC) /* func reject */
133 #define TC4 (4 << TSSR_V_TC) /* retry, moved */
134 #define TC5 (5 << TSSR_V_TC) /* retry */
135 #define TC6 (6 << TSSR_V_TC) /* pos lost */
136 #define TC7 (7 << TSSR_V_TC) /* fatal err */
137 #define TSSR_MBZ 0060060
138 #define GET_TC(x) (((x) >> TSSR_V_TC) & TSSR_M_TC)
139
140 #define TSDBX_M_XA 017 /* ext addr */
141 #define TSDBX_BOOT 0000200 /* boot */
142
143 /* Command packet offsets */
144
145 #define CMD_PLNT 4 /* cmd pkt length */
146 #define cmdhdr tscmdp[0] /* header */
147 #define cmdadl tscmdp[1] /* address low */
148 #define cmdadh tscmdp[2] /* address high */
149 #define cmdlnt tscmdp[3] /* length */
150
151 /* Command packet header */
152
153 #define CMD_ACK 0100000 /* acknowledge */
154 #define CMD_CVC 0040000 /* clear vol chk */
155 #define CMD_OPP 0020000 /* opposite */
156 #define CMD_SWP 0010000 /* swap bytes */
157 #define CMD_V_MODE 8 /* mode */
158 #define CMD_M_MODE 017
159 #define CMD_IE 0000200 /* int enable */
160 #define CMD_V_FNC 0 /* function */
161 #define CMD_M_FNC 037 /* function */
162 #define CMD_N_FNC (CMD_M_FNC + 1)
163 #define FNC_READ 001 /* read */
164 #define FNC_WCHR 004 /* write char */
165 #define FNC_WRIT 005 /* write */
166 #define FNC_WSSM 006 /* write mem */
167 #define FNC_POS 010 /* position */
168 #define FNC_FMT 011 /* format */
169 #define FNC_CTL 012 /* control */
170 #define FNC_INIT 013 /* init */
171 #define FNC_GSTA 017 /* get status */
172 #define CMD_MBZ 0000140
173 #define GET_FNC(x) (((x) >> CMD_V_FNC) & CMD_M_FNC)
174 #define GET_MOD(x) (((x) >> CMD_V_MODE) & CMD_M_MODE)
175
176 /* Function test flags */
177
178 #define FLG_MO 001 /* motion */
179 #define FLG_WR 002 /* write */
180 #define FLG_AD 004 /* addr mem */
181
182 /* Message packet offsets */
183
184 #define MSG_PLNT 8 /* packet length */
185 #define msghdr tsmsgp[0] /* header */
186 #define msglnt tsmsgp[1] /* length */
187 #define msgrfc tsmsgp[2] /* residual frame */
188 #define msgxs0 tsmsgp[3] /* ext status 0 */
189 #define msgxs1 tsmsgp[4] /* ext status 1 */
190 #define msgxs2 tsmsgp[5] /* ext status 2 */
191 #define msgxs3 tsmsgp[6] /* ext status 3 */
192 #define msgxs4 tsmsgp[7] /* ext status 4 */
193
194 /* Message packet header */
195
196 #define MSG_ACK 0100000 /* acknowledge */
197 #define MSG_MATN 0000000 /* attention */
198 #define MSG_MILL 0000400 /* illegal */
199 #define MSG_MNEF 0001000 /* non exec fnc */
200 #define MSG_CEND 0000020 /* end */
201 #define MSG_CFAIL 0000021 /* fail */
202 #define MSG_CERR 0000022 /* error */
203 #define MSG_CATN 0000023 /* attention */
204
205 /* Extended status register 0 */
206
207 #define XS0_TMK 0100000 /* tape mark */
208 #define XS0_RLS 0040000 /* rec lnt short */
209 #define XS0_LET 0020000 /* log end tape */
210 #define XS0_RLL 0010000 /* rec lnt long */
211 #define XS0_WLE 0004000 /* write lock err */
212 #define XS0_NEF 0002000 /* non exec fnc */
213 #define XS0_ILC 0001000 /* illegal cmd */
214 #define XS0_ILA 0000400 /* illegal addr */
215 #define XS0_MOT 0000200 /* tape has moved */
216 #define XS0_ONL 0000100 /* online */
217 #define XS0_IE 0000040 /* int enb */
218 #define XS0_VCK 0000020 /* volume check */
219 #define XS0_PET 0000010 /* 1600 bpi */
220 #define XS0_WLK 0000004 /* write lock */
221 #define XS0_BOT 0000002 /* BOT */
222 #define XS0_EOT 0000001 /* EOT */
223 #define XS0_ALLCLR 0177600 /* clear at start */
224
225 /* Extended status register 1 */
226
227 #define XS1_UCOR 0000002 /* uncorrectable */
228
229 /* Extended status register 2 */
230
231 #define XS2_XTF 0000200 /* ext features */
232
233 /* Extended status register 3 */
234
235 #define XS3_OPI 0000100 /* op incomplete */
236 #define XS3_REV 0000040 /* reverse */
237 #define XS3_RIB 0000001 /* reverse to BOT */
238
239 /* Extended status register 4 */
240
241 #define XS4_HDS 0100000 /* high density */
242
243 /* Write characteristics packet offsets */
244
245 #define WCH_PLNT 5 /* packet length */
246 #define wchadl tswchp[0] /* address low */
247 #define wchadh tswchp[1] /* address high */
248 #define wchlnt tswchp[2] /* length */
249 #define wchopt tswchp[3] /* options */
250 #define wchxopt tswchp[4] /* ext options */
251
252 /* Write characteristics options */
253
254 #define WCH_ESS 0000200 /* stop dbl tmk */
255 #define WCH_ENB 0000100 /* BOT = tmk */
256 #define WCH_EAI 0000040 /* enb attn int */
257 #define WCH_ERI 0000020 /* enb mrls int */
258
259 /* Write characteristics extended options */
260
261 #define WCHX_HDS 0000040 /* high density */
262
263 #define MAX(a,b) (((a) >= (b))? (a): (b))
264 #define MAX_PLNT 8 /* max pkt length */
265
266 extern int32 int_req[IPL_HLVL];
267 extern UNIT cpu_unit;
268 extern FILE *sim_deb;
269
270 uint8 *tsxb = NULL; /* xfer buffer */
271 int32 tssr = 0; /* status register */
272 int32 tsba = 0; /* mem addr */
273 int32 tsdbx = 0; /* data buf ext */
274 int32 tscmdp[CMD_PLNT] = { 0 }; /* command packet */
275 int32 tsmsgp[MSG_PLNT] = { 0 }; /* message packet */
276 int32 tswchp[WCH_PLNT] = { 0 }; /* wr char packet */
277 int32 ts_ownc = 0; /* tape owns cmd */
278 int32 ts_ownm = 0; /* tape owns msg */
279 int32 ts_qatn = 0; /* queued attn */
280 int32 ts_bcmd = 0; /* boot cmd */
281 int32 ts_time = 10; /* record latency */
282 static uint16 cpy_buf[MAX_PLNT]; /* copy buffer */
283
284 DEVICE ts_dev;
285 t_stat ts_rd (int32 *data, int32 PA, int32 access);
286 t_stat ts_wr (int32 data, int32 PA, int32 access);
287 t_stat ts_svc (UNIT *uptr);
288 t_stat ts_reset (DEVICE *dptr);
289 t_stat ts_attach (UNIT *uptr, char *cptr);
290 t_stat ts_detach (UNIT *uptr);
291 t_stat ts_boot (int32 unitno, DEVICE *dptr);
292 int32 ts_updtssr (int32 t);
293 int32 ts_updxs0 (int32 t);
294 void ts_cmpendcmd (int32 s0, int32 s1);
295 void ts_endcmd (int32 ssf, int32 xs0f, int32 msg);
296 int32 ts_map_status (t_stat st);
297
298 /* TS data structures
299
300 ts_dev TS device descriptor
301 ts_unit TS unit list
302 ts_reg TS register list
303 ts_mod TS modifier list
304 */
305
306 DIB ts_dib = {
307 IOBA_TS, IOLN_TS, &ts_rd, &ts_wr,
308 1, IVCL (TS), VEC_TS, { NULL }
309 };
310
311 UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) };
312
313 REG ts_reg[] = {
314 { GRDATA (TSSR, tssr, DEV_RDX, 16, 0) },
315 { GRDATA (TSBA, tsba, DEV_RDX, 22, 0) },
316 { GRDATA (TSDBX, tsdbx, DEV_RDX, 8, 0) },
317 { GRDATA (CHDR, cmdhdr, DEV_RDX, 16, 0) },
318 { GRDATA (CADL, cmdadl, DEV_RDX, 16, 0) },
319 { GRDATA (CADH, cmdadh, DEV_RDX, 16, 0) },
320 { GRDATA (CLNT, cmdlnt, DEV_RDX, 16, 0) },
321 { GRDATA (MHDR, msghdr, DEV_RDX, 16, 0) },
322 { GRDATA (MRFC, msgrfc, DEV_RDX, 16, 0) },
323 { GRDATA (MXS0, msgxs0, DEV_RDX, 16, 0) },
324 { GRDATA (MXS1, msgxs1, DEV_RDX, 16, 0) },
325 { GRDATA (MXS2, msgxs2, DEV_RDX, 16, 0) },
326 { GRDATA (MXS3, msgxs3, DEV_RDX, 16, 0) },
327 { GRDATA (MSX4, msgxs4, DEV_RDX, 16, 0) },
328 { GRDATA (WADL, wchadl, DEV_RDX, 16, 0) },
329 { GRDATA (WADH, wchadh, DEV_RDX, 16, 0) },
330 { GRDATA (WLNT, wchlnt, DEV_RDX, 16, 0) },
331 { GRDATA (WOPT, wchopt, DEV_RDX, 16, 0) },
332 { GRDATA (WXOPT, wchxopt, DEV_RDX, 16, 0) },
333 { FLDATA (INT, IREQ (TS), INT_V_TS) },
334 { FLDATA (ATTN, ts_qatn, 0) },
335 { FLDATA (BOOT, ts_bcmd, 0) },
336 { FLDATA (OWNC, ts_ownc, 0) },
337 { FLDATA (OWNM, ts_ownm, 0) },
338 { DRDATA (TIME, ts_time, 24), PV_LEFT + REG_NZ },
339 { DRDATA (POS, ts_unit.pos, T_ADDR_W), PV_LEFT + REG_RO },
340 { GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO },
341 { GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO },
342 { NULL }
343 };
344
345 MTAB ts_mod[] = {
346 { MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
347 { MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
348 { MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
349 &sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
350 { MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
351 &sim_tape_set_capac, &sim_tape_show_capac, NULL },
352 { MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
353 &set_addr, &show_addr, NULL },
354 { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
355 &set_vec, &show_vec, NULL },
356 { 0 }
357 };
358
359 DEVICE ts_dev = {
360 "TS", &ts_unit, ts_reg, ts_mod,
361 1, 10, T_ADDR_W, 1, DEV_RDX, 8,
362 NULL, NULL, &ts_reset,
363 &ts_boot, &ts_attach, &ts_detach,
364 &ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG
365 };
366
367 /* I/O dispatch routines, I/O addresses 17772520 - 17772522
368
369 17772520 TSBA read/write
370 17772522 TSSR read/write
371 */
372
373 t_stat ts_rd (int32 *data, int32 PA, int32 access)
374 {
375 switch ((PA >> 1) & 01) { /* decode PA<1> */
376
377 case 0: /* TSBA */
378 *data = tsba & DMASK; /* low 16b of ba */
379 break;
380 case 1: /* TSSR */
381 *data = tssr = ts_updtssr (tssr); /* update tssr */
382 break;
383 }
384
385 return SCPE_OK;
386 }
387
388 t_stat ts_wr (int32 data, int32 PA, int32 access)
389 {
390 int32 i, t;
391
392 switch ((PA >> 1) & 01) { /* decode PA<1> */
393
394 case 0: /* TSDB */
395 if ((tssr & TSSR_SSR) == 0) { /* ready? */
396 tssr = tssr | TSSR_RMR; /* no, refuse */
397 break;
398 }
399 tsba = ((tsdbx & TSDBX_M_XA) << 18) | /* form pkt addr */
400 ((data & 03) << 16) | (data & 0177774);
401 tsdbx = 0; /* clr tsdbx */
402 tssr = ts_updtssr (tssr & TSSR_NBA); /* clr ssr, err */
403 msgxs0 = ts_updxs0 (msgxs0 & ~XS0_ALLCLR); /* clr, upd xs0 */
404 msgrfc = msgxs1 = msgxs2 = msgxs3 = msgxs4 = 0; /* clr status */
405 CLR_INT (TS); /* clr int req */
406 t = Map_ReadW (tsba, CMD_PLNT << 1, cpy_buf); /* read cmd pkt */
407 tsba = tsba + ((CMD_PLNT << 1) - t); /* incr tsba */
408 if (t) { /* nxm? */
409 ts_endcmd (TSSR_NXM + TC5, 0, MSG_ACK|MSG_MNEF|MSG_CFAIL);
410 return SCPE_OK;
411 }
412 for (i = 0; i < CMD_PLNT; i++) /* copy packet */
413 tscmdp[i] = cpy_buf[i];
414 ts_ownc = ts_ownm = 1; /* tape owns all */
415 sim_activate (&ts_unit, ts_time); /* activate */
416 break;
417
418 case 1: /* TSSR */
419 if (PA & 1) { /* TSDBX */
420 if (UNIBUS) return SCPE_OK; /* not in TS11 */
421 if (tssr & TSSR_SSR) { /* ready? */
422 tsdbx = data; /* save */
423 if (data & TSDBX_BOOT) {
424 ts_bcmd = 1;
425 sim_activate (&ts_unit, ts_time);
426 }
427 }
428 else tssr = tssr | TSSR_RMR; /* no, err */
429 }
430 else if (access == WRITE) ts_reset (&ts_dev); /* reset */
431 break;
432 }
433
434 return SCPE_OK;
435 }
436
437 /* Tape motion routines */
438
439 #define XTC(x,t) (((unsigned) (x) << 16) | (t))
440 #define GET_X(x) (((x) >> 16) & 0177777)
441 #define GET_T(x) ((x) & 0177777)
442
443 int32 ts_map_status (t_stat st)
444 {
445 switch (st) {
446
447 case MTSE_OK:
448 break;
449
450 case MTSE_TMK:
451 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
452 return (XTC (XS0_TMK | XS0_RLS, TC2));
453
454 case MTSE_RECE: /* record in error */
455 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
456 case MTSE_INVRL: /* invalid rec lnt */
457 case MTSE_IOERR: /* IO error */
458 msgxs1 = msgxs1 | XS1_UCOR; /* uncorrectable */
459 return (XTC (XS0_RLS, TC6)); /* pos lost */
460
461 case MTSE_FMT:
462 case MTSE_UNATT:
463 case MTSE_EOM: /* end of medium */
464 msgxs3 = msgxs3 | XS3_OPI; /* incomplete */
465 return (XTC (XS0_RLS, TC6)); /* pos lost */
466
467 case MTSE_BOT: /* reverse into BOT */
468 msgxs3 = msgxs3 | XS3_RIB; /* set status */
469 return (XTC (XS0_BOT | XS0_RLS, TC2)); /* tape alert */
470
471 case MTSE_WRP: /* write protect */
472 msgxs0 = msgxs0 | XS0_WLE | XS0_NEF; /* can't execute */
473 return (XTC (XS0_WLE | XS0_NEF, TC3));
474 }
475
476 return 0;
477 }
478
479 int32 ts_spacef (UNIT *uptr, int32 fc, t_bool upd)
480 {
481 t_stat st;
482 t_mtrlnt tbc;
483
484 do {
485 fc = (fc - 1) & DMASK; /* decr wc */
486 if (upd) msgrfc = fc;
487 if (st = sim_tape_sprecf (uptr, &tbc)) /* space rec fwd, err? */
488 return ts_map_status (st); /* map status */
489 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
490 } while (fc != 0);
491 return 0;
492 }
493
494 int32 ts_skipf (UNIT *uptr, int32 fc)
495 {
496 t_stat st;
497 t_mtrlnt tbc;
498 t_bool tmkprv = FALSE;
499
500 msgrfc = fc;
501 if (sim_tape_bot (uptr) && (wchopt & WCH_ENB)) tmkprv = TRUE;
502 do {
503 st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */
504 if (st == MTSE_TMK) { /* tape mark? */
505 msgrfc = (msgrfc - 1) & DMASK; /* decr count */
506 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
507 if (tmkprv && (wchopt & WCH_ESS)) /* 2nd tmk & ESS? */
508 return (XTC ((msgrfc? XS0_RLS: 0) |
509 XS0_TMK | XS0_LET, TC2));
510 tmkprv = TRUE; /* flag tmk */
511 }
512 else if (st != MTSE_OK) return ts_map_status (st);
513 else tmkprv = FALSE; /* not a tmk */
514 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
515 } while (msgrfc != 0);
516 return 0;
517 }
518
519 int32 ts_spacer (UNIT *uptr, int32 fc, t_bool upd)
520 {
521 int32 st;
522 t_mtrlnt tbc;
523
524 do {
525 fc = (fc - 1) & DMASK; /* decr wc */
526 if (upd) msgrfc = fc;
527 if (st = sim_tape_sprecr (uptr, &tbc)) /* space rec rev, err? */
528 return ts_map_status (st); /* map status */
529 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
530 } while (fc != 0);
531 return 0;
532 }
533
534 int32 ts_skipr (UNIT *uptr, int32 fc)
535 {
536 t_stat st;
537 t_mtrlnt tbc;
538 t_bool tmkprv = FALSE;
539
540 msgrfc = fc;
541 do {
542 st = sim_tape_sprecr (uptr, &tbc); /* space rec rev */
543 if (st == MTSE_TMK) { /* tape mark? */
544 msgrfc = (msgrfc - 1) & DMASK; /* decr count */
545 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
546 if (tmkprv && (wchopt & WCH_ESS)) /* 2nd tmk & ESS? */
547 return (XTC ((msgrfc? XS0_RLS: 0) |
548 XS0_TMK | XS0_LET, TC2));
549 tmkprv = TRUE; /* flag tmk */
550 }
551 else if (st != MTSE_OK) return ts_map_status (st);
552 else tmkprv = FALSE; /* not a tmk */
553 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
554 } while (msgrfc != 0);
555 return 0;
556 }
557
558 int32 ts_readf (UNIT *uptr, uint32 fc)
559 {
560 t_stat st;
561 t_mtrlnt i, t, tbc, wbc;
562 int32 wa;
563
564 msgrfc = fc;
565 st = sim_tape_rdrecf (uptr, tsxb, &tbc, MT_MAXFR); /* read rec fwd */
566 if (st != MTSE_OK) return ts_map_status (st); /* error? */
567 if (fc == 0) fc = 0200000; /* byte count */
568 tsba = (cmdadh << 16) | cmdadl; /* buf addr */
569 wbc = (tbc > fc)? fc: tbc; /* cap buf size */
570 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
571 if (cmdhdr & CMD_SWP) { /* swapped? */
572 for (i = 0; i < wbc; i++) { /* copy buffer */
573 wa = tsba ^ 1; /* apply OPP */
574 if (Map_WriteB (tsba, 1, &tsxb[i])) { /* store byte, nxm? */
575 tssr = ts_updtssr (tssr | TSSR_NXM); /* set error */
576 return (XTC (XS0_RLS, TC4));
577 }
578 tsba = tsba + 1;
579 msgrfc = (msgrfc - 1) & DMASK;
580 }
581 }
582 else {
583 t = Map_WriteB (tsba, wbc, tsxb); /* store record */
584 tsba = tsba + (wbc - t); /* update tsba */
585 if (t) { /* nxm? */
586 tssr = ts_updtssr (tssr | TSSR_NXM); /* set error */
587 return (XTC (XS0_RLS, TC4));
588 }
589 msgrfc = (msgrfc - (wbc - t)) & DMASK; /* update fc */
590 }
591 if (msgrfc) return (XTC (XS0_RLS, TC2)); /* buf too big? */
592 if (tbc > wbc) return (XTC (XS0_RLL, TC2)); /* rec too big? */
593 return 0;
594 }
595
596 int32 ts_readr (UNIT *uptr, uint32 fc)
597 {
598 t_stat st;
599 t_mtrlnt i, tbc, wbc;
600 int32 wa;
601
602 msgrfc = fc;
603 st = sim_tape_rdrecr (uptr, tsxb, &tbc, MT_MAXFR); /* read rec rev */
604 if (st != MTSE_OK) return ts_map_status (st); /* error? */
605 if (fc == 0) fc = 0200000; /* byte count */
606 tsba = (cmdadh << 16) | cmdadl + fc; /* buf addr */
607 wbc = (tbc > fc)? fc: tbc; /* cap buf size */
608 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
609 for (i = wbc; i > 0; i--) { /* copy buffer */
610 tsba = tsba - 1;
611 wa = (cmdhdr & CMD_SWP)? tsba ^ 1: tsba; /* apply OPP */
612 if (Map_WriteB (wa, 1, &tsxb[i - 1])) { /* store byte, nxm? */
613 tssr = ts_updtssr (tssr | TSSR_NXM);
614 return (XTC (XS0_RLS, TC4));
615 }
616 msgrfc = (msgrfc - 1) & DMASK;
617 }
618 if (msgrfc) return (XTC (XS0_RLS, TC2)); /* buf too big? */
619 if (tbc > wbc) return (XTC (XS0_RLL, TC2)); /* rec too big? */
620 return 0;
621 }
622
623 int32 ts_write (UNIT *uptr, int32 fc)
624 {
625 int32 i, t;
626 uint32 wa;
627 t_stat st;
628
629 msgrfc = fc;
630 if (fc == 0) fc = 0200000; /* byte count */
631 tsba = (cmdadh << 16) | cmdadl; /* buf addr */
632 if (cmdhdr & CMD_SWP) { /* swapped? */
633 for (i = 0; i < fc; i++) { /* copy mem to buf */
634 wa = tsba ^ 1; /* apply OPP */
635 if (Map_ReadB (wa, 1, &tsxb[i])) { /* fetch byte, nxm? */
636 tssr = ts_updtssr (tssr | TSSR_NXM);
637 return TC5;
638 }
639 tsba = tsba + 1;
640 }
641 }
642 else {
643 t = Map_ReadB (tsba, fc, tsxb); /* fetch record */
644 tsba = tsba + (fc - t); /* update tsba */
645 if (t) { /* nxm? */
646 tssr = ts_updtssr (tssr | TSSR_NXM);
647 return TC5;
648 }
649 }
650 if (st = sim_tape_wrrecf (uptr, tsxb, fc)) /* write rec, err? */
651 return ts_map_status (st); /* return status */
652 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
653 msgrfc = 0;
654 if (sim_tape_eot (&ts_unit)) /* EOT on write? */
655 return XTC (XS0_EOT, TC2);
656 return 0;
657 }
658
659 int32 ts_wtmk (UNIT *uptr)
660 {
661 t_stat st;
662
663 if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
664 return ts_map_status (st); /* return status */
665 msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
666 if (sim_tape_eot (&ts_unit)) /* EOT on write? */
667 return XTC (XS0_EOT, TC2);
668 return XTC (XS0_TMK, TC0);
669 }
670
671 /* Unit service */
672
673 t_stat ts_svc (UNIT *uptr)
674 {
675 int32 i, t, bc, fnc, mod, st0, st1;
676
677 static const int32 fnc_mod[CMD_N_FNC] = { /* max mod+1 0 ill */
678 0, 4, 0, 0, 1, 2, 1, 0, /* 00 - 07 */
679 5, 3, 5, 1, 0, 0, 0, 1, /* 10 - 17 */
680 0, 0, 0, 0, 0, 0, 0, 0, /* 20 - 27 */
681 0, 0, 0, 0, 0, 0, 0, 0 /* 30 - 37 */
682 };
683 static const int32 fnc_flg[CMD_N_FNC] = {
684 0, FLG_MO+FLG_AD, 0, 0, 0, FLG_MO+FLG_WR+FLG_AD, FLG_AD, 0,
685 FLG_MO, FLG_MO+FLG_WR, FLG_MO, 0, 0, 0, 0, 0,
686 0, 0, 0, 0, 0, 0, 0, 0, /* 20 - 27 */
687 0, 0, 0, 0, 0, 0, 0, 0 /* 30 - 37 */
688 };
689 static const char *fnc_name[CMD_N_FNC] = {
690 "0", "READ", "2", "3", "WCHR", "WRITE", "WSSM", "7",
691 "POS", "FMT", "CTL", "INIT", "14", "15", "16", "GSTA",
692 "20", "21", "22", "23", "24", "25", "26", "27",
693 "30", "31", "32", "33", "34", "35", "36", "37"
694 };
695
696 if (ts_bcmd) { /* boot? */
697 ts_bcmd = 0; /* clear flag */
698 sim_tape_rewind (uptr); /* rewind */
699 if (uptr->flags & UNIT_ATT) { /* attached? */
700 cmdlnt = cmdadh = cmdadl = 0; /* defang rd */
701 ts_spacef (uptr, 1, FALSE); /* space fwd */
702 ts_readf (uptr, 512); /* read blk */
703 tssr = ts_updtssr (tssr | TSSR_SSR);
704 }
705 else tssr = ts_updtssr (tssr | TSSR_SSR | TC3);
706 if (cmdhdr & CMD_IE) SET_INT (TS);
707 return SCPE_OK;
708 }
709
710 if (!(cmdhdr & CMD_ACK)) { /* no acknowledge? */
711 tssr = ts_updtssr (tssr | TSSR_SSR); /* set rdy, int */
712 if (cmdhdr & CMD_IE) SET_INT (TS);
713 ts_ownc = ts_ownm = 0; /* CPU owns all */
714 return SCPE_OK;
715 }
716 fnc = GET_FNC (cmdhdr); /* get fnc+mode */
717 mod = GET_MOD (cmdhdr);
718 if (DEBUG_PRS (ts_dev))
719 fprintf (sim_deb, ">>TS: cmd=%s, mod=%o, buf=%o, lnt=%d, pos=%d\n",
720 fnc_name[fnc], mod, cmdadl, cmdlnt, ts_unit.pos);
721 if ((fnc != FNC_WCHR) && (tssr & TSSR_NBA)) { /* ~wr chr & nba? */
722 ts_endcmd (TC3, 0, 0); /* error */
723 return SCPE_OK;
724 }
725 if (ts_qatn && (wchopt & WCH_EAI)) { /* attn pending? */
726 ts_endcmd (TC1, 0, MSG_MATN | MSG_CATN); /* send attn msg */
727 SET_INT (TS); /* set interrupt */
728 ts_qatn = 0; /* not pending */
729 return SCPE_OK;
730 }
731 if (cmdhdr & CMD_CVC) /* cvc? clr vck */
732 msgxs0 = msgxs0 & ~XS0_VCK;
733 if ((cmdhdr & CMD_MBZ) || (mod >= fnc_mod[fnc])) { /* test mbz */
734 ts_endcmd (TC3, XS0_ILC, MSG_ACK | MSG_MILL | MSG_CFAIL);
735 return SCPE_OK;
736 }
737 if ((fnc_flg[fnc] & FLG_MO) && /* mot+(vck|!att)? */
738 ((msgxs0 & XS0_VCK) || !(uptr->flags & UNIT_ATT))) {
739 ts_endcmd (TC3, XS0_NEF, MSG_ACK | MSG_MNEF | MSG_CFAIL);
740 return SCPE_OK;
741 }
742 if ((fnc_flg[fnc] & FLG_WR) && /* write? */
743 sim_tape_wrp (uptr)) { /* write lck? */
744 ts_endcmd (TC3, XS0_WLE | XS0_NEF, MSG_ACK | MSG_MNEF | MSG_CFAIL);
745 return SCPE_OK;
746 }
747 if ((((fnc == FNC_READ) && (mod == 1)) || /* read rev */
748 ((fnc == FNC_POS) && (mod & 1))) && /* space rev */
749 sim_tape_bot (uptr)) { /* BOT? */
750 ts_endcmd (TC3, XS0_NEF, MSG_ACK | MSG_MNEF | MSG_CFAIL);
751 return SCPE_OK;
752 }
753 if ((fnc_flg[fnc] & FLG_AD) && (cmdadh & ADDRTEST)) { /* buf addr > 22b? */
754 ts_endcmd (TC3, XS0_ILA, MSG_ACK | MSG_MILL | MSG_CFAIL);
755 return SCPE_OK;
756 }
757
758 st0 = st1 = 0;
759 switch (fnc) { /* case on func */
760
761 case FNC_INIT: /* init */
762 if (!sim_tape_bot (uptr)) msgxs0 = msgxs0 | XS0_MOT; /* set if tape moves */
763 sim_tape_rewind (uptr); /* rewind */
764 case FNC_WSSM: /* write mem */
765 case FNC_GSTA: /* get status */
766 ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND); /* send end packet */
767 return SCPE_OK;
768
769 case FNC_WCHR: /* write char */
770 if ((cmdadh & ADDRTEST) || (cmdadl & 1) || (cmdlnt < 6)) {
771 ts_endcmd (TSSR_NBA | TC3, XS0_ILA, 0);
772 break;
773 }
774 tsba = (cmdadh << 16) | cmdadl;
775 bc = ((WCH_PLNT << 1) > cmdlnt)? cmdlnt: WCH_PLNT << 1;
776 t = Map_ReadW (tsba, bc, cpy_buf); /* fetch packet */
777 tsba = tsba + (bc - t); /* inc tsba */
778 if (t) { /* nxm? */
779 ts_endcmd (TSSR_NBA | TSSR_NXM | TC5, 0, 0);
780 return SCPE_OK;
781 }
782 for (i = 0; i < (bc / 2); i++) /* copy packet */
783 tswchp[i] = cpy_buf[i];
784 if ((wchlnt < ((MSG_PLNT - 1) * 2)) || (wchadh & 0177700) ||
785 (wchadl & 1)) ts_endcmd (TSSR_NBA | TC3, 0, 0);
786 else {
787 msgxs2 = msgxs2 | XS2_XTF | 1;
788 tssr = ts_updtssr (tssr & ~TSSR_NBA);
789 ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND);
790 }
791 return SCPE_OK;
792
793 case FNC_CTL: /* control */
794 switch (mod) { /* case mode */
795
796 case 00: /* msg buf rls */
797 tssr = ts_updtssr (tssr | TSSR_SSR); /* set SSR */
798 if (wchopt & WCH_ERI) SET_INT (TS);
799 ts_ownc = 0; ts_ownm = 1; /* keep msg */
800 break;
801
802 case 01: /* rewind and unload */
803 if (!sim_tape_bot (uptr)) msgxs0 = msgxs0 | XS0_MOT; /* if tape moves */
804 sim_tape_detach (uptr); /* unload */
805 ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND);
806 break;
807
808 case 02: /* clean */
809 ts_endcmd (TC0, 0, MSG_ACK | MSG_CEND); /* nop */
810 break;
811
812 case 03: /* undefined */
813 ts_endcmd (TC3, XS0_ILC, MSG_ACK | MSG_MILL | MSG_CFAIL);
814 return SCPE_OK;
815
816 case 04: /* rewind */
817 if (!sim_tape_bot (uptr)) msgxs0 = msgxs0 | XS0_MOT; /* if tape moves */
818 sim_tape_rewind (uptr);
819 ts_endcmd (TC0, XS0_BOT, MSG_ACK | MSG_CEND);
820 break;
821 }
822 break;
823
824 case FNC_READ: /* read */
825 switch (mod) { /* case mode */
826
827 case 00: /* fwd */
828 st0 = ts_readf (uptr, cmdlnt); /* read */
829 break;
830
831 case 01: /* back */
832 st0 = ts_readr (uptr, cmdlnt); /* read */
833 break;
834
835 case 02: /* reread fwd */
836 if (cmdhdr & CMD_OPP) { /* opposite? */
837 st0 = ts_readr (uptr, cmdlnt);
838 st1 = ts_spacef (uptr, 1, FALSE);
839 }
840 else {
841 st0 = ts_spacer (uptr, 1, FALSE);
842 st1 = ts_readf (uptr, cmdlnt);
843 }
844 break;
845
846 case 03: /* reread back */
847 if (cmdhdr & CMD_OPP) { /* opposite */
848 st0 = ts_readf (uptr, cmdlnt);
849 st1 = ts_spacer (uptr, 1, FALSE);
850 }
851 else {
852 st0 = ts_spacef (uptr, 1, FALSE);
853 st1 = ts_readr (uptr, cmdlnt);
854 }
855 break;
856 }
857 ts_cmpendcmd (st0, st1);
858 break;
859
860 case FNC_WRIT: /* write */
861 switch (mod) { /* case mode */
862
863 case 00: /* write */
864 st0 = ts_write (uptr, cmdlnt);
865 break;
866
867 case 01: /* rewrite */
868 st0 = ts_spacer (uptr, 1, FALSE);
869 st1 = ts_write (uptr, cmdlnt);
870 break;
871 }
872 ts_cmpendcmd (st0, st1);
873 break;
874
875 case FNC_FMT: /* format */
876 switch (mod) { /* case mode */
877
878 case 00: /* write tmk */
879 st0 = ts_wtmk (uptr);
880 break;
881
882 case 01: /* erase */
883 break;
884
885 case 02: /* retry tmk */
886 st0 = ts_spacer (uptr, 1, FALSE);
887 st1 = ts_wtmk (uptr);
888 break;
889 }
890 ts_cmpendcmd (st0, st1);
891 break;
892
893 case FNC_POS: /* position */
894 switch (mod) { /* case mode */
895
896 case 00: /* space fwd */
897 st0 = ts_spacef (uptr, cmdadl, TRUE);
898 break;
899
900 case 01: /* space rev */
901 st0 = ts_spacer (uptr, cmdadl, TRUE);
902 break;
903
904 case 02: /* space ffwd */
905 st0 = ts_skipf (uptr, cmdadl);
906 break;
907
908 case 03: /* space frev */
909 st0 = ts_skipr (uptr, cmdadl);
910 break;
911
912 case 04: /* rewind */
913 if (!sim_tape_bot (uptr)) /* if tape moves */
914 msgxs0 = msgxs0 | XS0_MOT;
915 sim_tape_rewind (uptr);
916 break;
917 }
918 ts_cmpendcmd (st0, 0);
919 break;
920 }
921
922 return SCPE_OK;
923 }
924
925 /* Utility routines */
926
927 int32 ts_updtssr (int32 t)
928 {
929 t = (t & ~TSSR_EMA) | ((tsba >> (16 - TSSR_V_EMA)) & TSSR_EMA);
930 if (ts_unit.flags & UNIT_ATT) t = t & ~TSSR_OFL;
931 else t = t | TSSR_OFL;
932 return (t & ~TSSR_MBZ);
933 }
934
935 int32 ts_updxs0 (int32 t)
936 {
937 t = (t & ~(XS0_ONL | XS0_WLK | XS0_BOT | XS0_IE)) | XS0_PET;
938 if (ts_unit.flags & UNIT_ATT) {
939 t = t | XS0_ONL;
940 if (sim_tape_wrp (&ts_unit)) t = t | XS0_WLK;
941 if (sim_tape_bot (&ts_unit))
942 t = (t | XS0_BOT) & ~XS0_EOT;
943 if (sim_tape_eot (&ts_unit))
944 t = (t | XS0_EOT) & ~XS0_BOT;
945 }
946 else t = t & ~XS0_EOT;
947 if (cmdhdr & CMD_IE) t = t | XS0_IE;
948 return t;
949 }
950
951 void ts_cmpendcmd (int32 s0, int32 s1)
952 {
953 int32 xs0, ssr, tc;
954 static const int32 msg[8] = {
955 MSG_ACK | MSG_CEND, MSG_ACK | MSG_MATN | MSG_CATN,
956 MSG_ACK | MSG_CEND, MSG_ACK | MSG_CFAIL,
957 MSG_ACK | MSG_CERR, MSG_ACK | MSG_CERR,
958 MSG_ACK | MSG_CERR, MSG_ACK | MSG_CERR
959 };
960
961 xs0 = GET_X (s0) | GET_X (s1); /* or XS0 errs */
962 s0 = GET_T (s0); /* get SSR errs */
963 s1 = GET_T (s1);
964 ssr = (s0 | s1) & ~TSSR_TC; /* or SSR errs */
965 tc = MAX (GET_TC (s0), GET_TC (s1)); /* max term code */
966 ts_endcmd (ssr | (tc << TSSR_V_TC), xs0, msg[tc]); /* end cmd */
967 return;
968 }
969
970 void ts_endcmd (int32 tc, int32 xs0, int32 msg)
971 {
972 int32 i, t;
973
974 msgxs0 = ts_updxs0 (msgxs0 | xs0); /* update XS0 */
975 if (wchxopt & WCHX_HDS) msgxs4 = msgxs4 | XS4_HDS; /* update XS4 */
976 if (msg && !(tssr & TSSR_NBA)) { /* send end pkt */
977 msghdr = msg;
978 msglnt = wchlnt - 4; /* exclude hdr, bc */
979 tsba = (wchadh << 16) | wchadl;
980 for (i = 0; (i < MSG_PLNT) && (i < (wchlnt / 2)); i++)
981 cpy_buf[i] = (uint16) tsmsgp[i]; /* copy buffer */
982 t = Map_WriteW (tsba, i << 1, cpy_buf); /* write to mem */
983 tsba = tsba + ((i << 1) - t); /* incr tsba */
984 if (t) { /* nxm? */
985 tssr = tssr | TSSR_NXM;
986 tc = (tc & ~TSSR_TC) | TC4;
987 }
988 }
989 tssr = ts_updtssr (tssr | tc | TSSR_SSR | (tc? TSSR_SC: 0));
990 if (cmdhdr & CMD_IE) SET_INT (TS);
991 ts_ownm = 0; ts_ownc = 0;
992 if (DEBUG_PRS (ts_dev))
993 fprintf (sim_deb, ">>TS: sta=%o, tc=%o, rfc=%d, pos=%d\n",
994 msgxs0, GET_TC (tssr), msgrfc, ts_unit.pos);
995 return;
996 }
997
998 /* Device reset */
999
1000 t_stat ts_reset (DEVICE *dptr)
1001 {
1002 int32 i;
1003
1004 sim_tape_rewind (&ts_unit);
1005 tsba = tsdbx = 0;
1006 ts_ownc = ts_ownm = 0;
1007 ts_bcmd = 0;
1008 ts_qatn = 0;
1009 tssr = ts_updtssr (TSSR_NBA | TSSR_SSR);
1010 for (i = 0; i < CMD_PLNT; i++) tscmdp[i] = 0;
1011 for (i = 0; i < WCH_PLNT; i++) tswchp[i] = 0;
1012 for (i = 0; i < MSG_PLNT; i++) tsmsgp[i] = 0;
1013 msgxs0 = ts_updxs0 (XS0_VCK);
1014 CLR_INT (TS);
1015 if (tsxb == NULL) tsxb = (uint8 *) calloc (MT_MAXFR, sizeof (uint8));
1016 if (tsxb == NULL) return SCPE_MEM;
1017 return SCPE_OK;
1018 }
1019
1020 /* Attach */
1021
1022 t_stat ts_attach (UNIT *uptr, char *cptr)
1023 {
1024 t_stat r;
1025
1026 r = sim_tape_attach (uptr, cptr); /* attach unit */
1027 if (r != SCPE_OK) return r; /* error? */
1028 tssr = tssr & ~TSSR_OFL; /* clr offline */
1029 if ((tssr & TSSR_NBA) || !(wchopt & WCH_EAI)) return r; /* attn msg? */
1030 if (ts_ownm) { /* own msg buf? */
1031 ts_endcmd (TC1, 0, MSG_MATN | MSG_CATN); /* send attn */
1032 SET_INT (TS); /* set interrupt */
1033 ts_qatn = 0; /* don't queue */
1034 }
1035 else ts_qatn = 1; /* else queue */
1036 return r;
1037 }
1038
1039 /* Detach routine */
1040
1041 t_stat ts_detach (UNIT* uptr)
1042 {
1043 t_stat r;
1044
1045 if (!(uptr->flags & UNIT_ATT)) return SCPE_OK; /* attached? */
1046 r = sim_tape_detach (uptr); /* detach unit */
1047 if (r != SCPE_OK) return r; /* error? */
1048 tssr = tssr | TSSR_OFL; /* set offline */
1049 if ((tssr & TSSR_NBA) || !(wchopt & WCH_EAI)) return r; /* attn msg? */
1050 if (ts_ownm) { /* own msg buf? */
1051 ts_endcmd (TC1, 0, MSG_MATN | MSG_CATN); /* send attn */
1052 SET_INT (TS); /* set interrupt */
1053 ts_qatn = 0; /* don't queue */
1054 }
1055 else ts_qatn = 1; /* else queue */
1056 return r;
1057 }
1058
1059 /* Boot */
1060
1061 #if defined (VM_PDP11)
1062 #define BOOT_START 01000
1063 #define BOOT_CSR0 (BOOT_START + 006)
1064 #define BOOT_CSR1 (BOOT_START + 012)
1065 #define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))
1066
1067 static const uint16 boot_rom[] = {
1068 0012706, 0001000, /* mov #boot_start, sp */
1069 0012700, 0172520, /* mov #tsba, r0 */
1070 0012701, 0172522, /* mov #tssr, r1 */
1071 0005011, /* clr (r1) ; init, rew */
1072 0105711, /* tstb (r1) ; wait */
1073 0100376, /* bpl .-2 */
1074 0012710, 0001070, /* mov #pkt1, (r0) ; set char */
1075 0105711, /* tstb (r1) ; wait */
1076 0100376, /* bpl .-2 */
1077 0012710, 0001110, /* mov #pkt2, (r0) ; read, skip */
1078 0105711, /* tstb (r1) ; wait */
1079 0100376, /* bpl .-2 */
1080 0012710, 0001110, /* mov #pkt2, (r0) ; read */
1081 0105711, /* tstb (r1) ; wait */
1082 0100376, /* bpl .-2 */
1083 0005711, /* tst (r1) ; err? */
1084 0100421, /* bmi hlt */
1085 0005000, /* clr r0 */
1086 0012704, 0001066+020, /* mov #sgnt+20, r4 */
1087 0005007, /* clr r7 */
1088 0046523, /* sgnt: "SM" */
1089 0140004, /* pkt1: 140004, wcpk, 0, 8. */
1090 0001100,
1091 0000000,
1092 0000010,
1093 0001122, /* wcpk: msg, 0, 14., 0 */
1094 0000000,
1095 0000016,
1096 0000000,
1097 0140001, /* pkt2: 140001, 0, 0, 512. */
1098 0000000,
1099 0000000,
1100 0001000,
1101 0000000 /* hlt: halt */
1102 /* msg: .blk 4 */
1103 };
1104
1105 t_stat ts_boot (int32 unitno, DEVICE *dptr)
1106 {
1107 int32 i;
1108 extern int32 saved_PC;
1109 extern uint16 *M;
1110
1111 sim_tape_rewind (&ts_unit);
1112 for (i = 0; i < BOOT_LEN; i++)
1113 M[(BOOT_START >> 1) + i] = boot_rom[i];
1114 M[BOOT_CSR0 >> 1] = ts_dib.ba & DMASK;
1115 M[BOOT_CSR1 >> 1] = (ts_dib.ba & DMASK) + 02;
1116 saved_PC = BOOT_START;
1117 return SCPE_OK;
1118 }
1119
1120 #else
1121
1122 t_stat ts_boot (int32 unitno, DEVICE *dptr)
1123 {
1124 return SCPE_NOFNC;
1125 }
1126 #endif
Magically enhanced SIMH