PDP11/pdp11_xq.h

   1 /* pdp11_xq.h: DEQNA/DELQA ethernet controller information
   2   ------------------------------------------------------------------------------
   3
   4    Copyright (c) 2002-2005, David T. Hittner
   5
   6    Permission is hereby granted, free of charge, to any person obtaining a
   7    copy of this software and associated documentation files (the "Software"),
   8    to deal in the Software without restriction, including without limitation
   9    the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10    and/or sell copies of the Software, and to permit persons to whom the
  11    Software is furnished to do so, subject to the following conditions:
  12
  13    The above copyright notice and this permission notice shall be included in
  14    all copies or substantial portions of the Software.
  15
  16    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19    THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  20    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22
  23    Except as contained in this notice, the name of the author shall not be
  24    used in advertising or otherwise to promote the sale, use or other dealings
  25    in this Software without prior written authorization from the author.
  26
  27   ------------------------------------------------------------------------------
  28
  29   Modification history:
  30
  31   07-Jul-05  RMS  Removed extraneous externs
  32   20-Jan-04  DTH  Added new sanity timer and system id timer
  33   19-Jan-04  DTH  Added XQ_SERVICE_INTERVAL, poll
  34   09-Jan-04  DTH  Added Boot PDP diagnostic definition, XI/RI combination
  35   26-Dec-03  DTH  Moved ethernet queue definitions to sim_ether
  36   25-Nov-03  DTH  Added interrupt request flag
  37   02-Jun-03  DTH  Added struct xq_stats
  38   28-May-03  DTH  Made xq_msg_que.item dynamic
  39   28-May-03  MP   Optimized structures, removed rtime variable
  40   06-May-03  DTH  Changed 32-bit t_addr to uint32 for v3.0
  41   28-Apr-03  DTH  Added callbacks for multicontroller identification
  42   25-Mar-03  DTH  Removed bootrom field - no longer needed; Updated copyright
  43   15-Jan-03  DTH  Merged Mark Pizzolato's changes into main source
  44   13-Jan-03  MP   Added countdown for System Id multicast packets
  45   10-Jan-03  DTH  Added bootrom field
  46   30-Dec-02  DTH  Added setup valid field
  47   21-Oct-02  DTH  Corrected copyright again
  48   15-Oct-02  DTH  Fixed copyright, added sanity timer support
  49   10-Oct-02  DTH  Added more setup fields and bitmasks
  50   08-Oct-02  DTH  Integrated with 2.10-0p4, added variable vector and copyrights
  51   03-Oct-02  DTH  Beta version of xq/sim_ether released for SIMH 2.09-11
  52   15-Aug-02  DTH  Started XQ simulation
  53
  54   ------------------------------------------------------------------------------
  55 */
  56
  57 #ifndef _PDP11_XQ_H
  58 #define _PDP11_XQ_H
  59
  60 #if defined (VM_PDP10)                                  /* PDP10 version */
  61 #error "DEQNA/DELQA not supported on PDP10!"
  62
  63 #elif defined (VM_VAX)                                  /* VAX version */
  64 #include "vax_defs.h"
  65 #define XQ_RDX          16
  66 #define XQ_WID          32
  67 extern int32 PSL;                                       /* PSL */
  68 extern int32 fault_PC;                                  /* fault PC */
  69 extern int32 int_req[IPL_HLVL];
  70
  71 #else                                                   /* PDP-11 version */
  72 #include "pdp11_defs.h"
  73 #define XQ_RDX          8
  74 #define XQ_WID          16
  75 extern int32 int_req[IPL_HLVL];
  76 #endif
  77
  78 #include "sim_ether.h"
  79
  80 #define XQ_QUE_MAX           500                        /* read queue size in packets */
  81 #define XQ_FILTER_MAX         14                        /* number of filters allowed */
  82 #define XQ_SERVICE_INTERVAL  100                        /* polling interval - X per second */
  83 #define XQ_SYSTEM_ID_SECS    540                        /* seconds before system ID timer expires */
  84 #define XQ_HW_SANITY_SECS    240                        /* seconds before HW sanity timer expires */
  85 #define XQ_MAX_CONTROLLERS     2                        /* maximum controllers allowed */
  86
  87 enum xq_type {XQ_T_DEQNA, XQ_T_DELQA};
  88
  89 struct xq_sanity {
  90   int       enabled;                                    /* sanity timer enabled? 2=HW, 1=SW, 0=off */
  91   int       quarter_secs;                               /* sanity timer value in 1/4 seconds */
  92   int       max;                                        /* maximum timeout (based on poll) */
  93   int       timer;                                      /* countdown timer */
  94 };
  95
  96 struct xq_setup {
  97   int               valid;                              /* is the setup block valid? */
  98   int               promiscuous;                        /* promiscuous mode enabled */
  99   int               multicast;                          /* enable all multicast addresses */
 100   int               l1;                                 /* first  diagnostic led state */
 101   int               l2;                                 /* second diagnostic led state */
 102   int               l3;                                 /* third  diagnostic led state */
 103   int               sanity_timer;                       /* sanity timer value (encoded) */
 104   ETH_MAC           macs[XQ_FILTER_MAX];                /* MAC addresses to respond to */
 105 };
 106
 107 struct xq_stats {
 108   int               recv;                               /* received packets */
 109   int               filter;                             /* filtered packets */
 110   int               xmit;                               /* transmitted packets */
 111   int               fail;                               /* transmit failed */
 112   int               runt;                               /* runts */
 113   int               giant;                              /* oversize packets */
 114   int               setup;                              /* setup packets */
 115   int               loop;                               /* loopback packets */
 116 };
 117
 118 struct xq_meb {                                         /* MEB block */
 119   uint8   type;
 120   uint8   add_lo;
 121   uint8   add_mi;
 122   uint8   add_hi;
 123   uint8   siz_lo;
 124   uint8   siz_hi;
 125 };
 126
 127 struct xq_device {
 128                                                         /*+ initialized values - DO NOT MOVE */
 129   ETH_PCALLBACK     rcallback;                          /* read callback routine */
 130   ETH_PCALLBACK     wcallback;                          /* write callback routine */
 131   ETH_MAC           mac;                                /* MAC address */
 132   enum xq_type      type;                               /* controller type */
 133   int               poll;                               /* poll ethernet times/sec */
 134   struct xq_sanity  sanity;                             /* sanity timer information */
 135                                                         /*- initialized values - DO NOT MOVE */
 136
 137                                                         /* I/O register storage */
 138   uint16            addr[6];
 139   uint16            rbdl[2];
 140   uint16            xbdl[2];
 141   uint16            var;
 142   uint16            csr;
 143   uint32            irq;                                /* interrupt request flag */
 144
 145                                                         /* buffers, etc. */
 146   struct xq_setup   setup;
 147   struct xq_stats   stats;
 148   uint8             mac_checksum[2];
 149   uint16            rbdl_buf[6];
 150   uint16            xbdl_buf[6];
 151   uint32            rbdl_ba;
 152   uint32            xbdl_ba;
 153   ETH_DEV*          etherface;
 154   int               receiving;
 155   ETH_PACK          read_buffer;
 156   ETH_PACK          write_buffer;
 157   ETH_QUE           ReadQ;
 158   int               idtmr;                              /* countdown for ID Timer */
 159 };
 160
 161 struct xq_controller {
 162   DEVICE*           dev;                                /* device block */
 163   UNIT*             unit;                               /* unit block */
 164   DIB*              dib;                                /* device interface block */
 165   struct xq_device* var;                                /* controller-specific variables */
 166 };
 167
 168 typedef struct xq_controller CTLR;
 169
 170
 171 #define XQ_CSR_RI 0x8000                                /* Receive Interrupt Request     (RI) [RO/W1] */
 172 #define XQ_CSR_PE 0x4000                                /* Parity Error in Host Memory   (PE) [RO] */
 173 #define XQ_CSR_CA 0x2000                                /* Carrier from Receiver Enabled (CA) [RO] */
 174 #define XQ_CSR_OK 0x1000                                /* Ethernet Transceiver Power    (OK) [RO] */
 175 #define XQ_CSR_RR 0x0800                                /* Reserved : Set to Zero        (RR) [RO] */
 176 #define XQ_CSR_SE 0x0400                                /* Sanity Timer Enable           (SE) [RW] */
 177 #define XQ_CSR_EL 0x0200                                /* External Loopback             (EL) [RW] */
 178 #define XQ_CSR_IL 0x0100                                /* Internal Loopback             (IL) [RW] */
 179 #define XQ_CSR_XI 0x0080                                /* Transmit Interrupt Request    (XI) [RO/W1] */
 180 #define XQ_CSR_IE 0x0040                                /* Interrupt Enable              (IE) [RW] */
 181 #define XQ_CSR_RL 0x0020                                /* Receive List Invalid/Empty    (RL) [RO] */
 182 #define XQ_CSR_XL 0x0010                                /* Transmit List Invalid/Empty   (XL) [RO] */
 183 #define XQ_CSR_BD 0x0008                                /* Boot/Diagnostic ROM Load      (BD) [RW] */
 184 #define XQ_CSR_NI 0x0004                                /* NonExistant Memory Timeout   (NXM) [RO] */
 185 #define XQ_CSR_SR 0x0002                                /* Software Reset                (SR) [RW] */
 186 #define XQ_CSR_RE 0x0001                                /* Receiver Enable               (RE) [RW] */
 187
 188 /* special access bitmaps */
 189 #define XQ_CSR_RO   0xF8B4                              /* Read-Only bits */
 190 #define XQ_CSR_RW   0x074B                              /* Read/Write bits */
 191 #define XQ_CSR_W1   0x8080                              /* Write-one-to-clear bits */
 192 #define XQ_CSR_BP   0x0208                              /* Boot PDP diagnostic ROM */
 193 #define XQ_CSR_XIRI 0X8080                              /* Transmit & Receive Interrupts */
 194
 195 #define XQ_VEC_MS 0x8000                                /* Mode Select                   (MO) [RW]  */
 196 #define XQ_VEC_OS 0x4000                                /* Option Switch Setting         (OS) [RO]  */
 197 #define XQ_VEC_RS 0x2000                                /* Request Self-Test             (RS) [RW]  */
 198 #define XQ_VEC_S3 0x1000                                /* Self-Test Status              (S3) [RO]  */
 199 #define XQ_VEC_S2 0x0800                                /* Self-Test Status              (S2) [RO]  */
 200 #define XQ_VEC_S1 0x0400                                /* Self-Test Status              (S1) [RO]  */
 201 #define XQ_VEC_ST 0x1C00                                /* Self-Test (S1 + S2 + S3)           [RO]  */
 202 #define XQ_VEC_IV 0x03FC                                /* Interrupt Vector              (IV) [RW]  */
 203 #define XQ_VEC_RR 0x0002                                /* Reserved                      (RR) [RO]  */
 204 #define XQ_VEC_ID 0x0001                                /* Identity Test Bit             (ID) [RW]  */
 205
 206 /* special access bitmaps */
 207 #define XQ_VEC_RO 0x5C02                                /* Read-Only bits */
 208 #define XQ_VEC_RW 0xA3FD                                /* Read/Write bits */
 209
 210 #define XQ_DSC_V  0x8000                                /* Valid bit */
 211 #define XQ_DSC_C  0x4000                                /* Chain bit */
 212 #define XQ_DSC_E  0x2000                                /* End of Message bit       [Transmit only] */
 213 #define XQ_DSC_S  0x1000                                /* Setup bit                [Transmit only] */
 214 #define XQ_DSC_L  0x0080                                /* Low Byte Termination bit [Transmit only] */
 215 #define XQ_DSC_H  0x0040                                /* High Byte Start bit      [Transmit only] */
 216
 217 #define XQ_SETUP_MC 0x0001                              /* multicast bit */
 218 #define XQ_SETUP_PM 0x0002                              /* promiscuous bit */
 219 #define XQ_SETUP_LD 0x000C                              /* led bits */
 220 #define XQ_SETUP_ST 0x0070                              /* sanity timer bits */
 221
 222 /* debugging bitmaps */
 223 #define DBG_TRC  0x0001                                 /* trace routine calls */
 224 #define DBG_REG  0x0002                                 /* trace read/write registers */
 225 #define DBG_CSR  0x0004                                 /* watch CSR */
 226 #define DBG_VAR  0x0008                                 /* watch VAR */
 227 #define DBG_WRN  0x0010                                 /* display warnings */
 228 #define DBG_SAN  0x0020                                 /* display sanity timer info */
 229 #define DBG_SET  0x0040                                 /* display setup info */
 230 #define DBG_PCK  0x0080                                 /* display packets */
 231 #define DBG_ETH  0x8000                                 /* debug ethernet device */
 232
 233 #endif                                                  /* _PDP11_XQ_H */