PDP18B/pdp18b_drm.c

   1 /* pdp18b_drm.c: drum/fixed head disk simulator
   2
   3    Copyright (c) 1993-2005, Robert M Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    drm          (PDP-4,PDP-7) Type 24 serial drum
  27
  28    14-Jan-04    RMS     Revised IO device call interface
  29    26-Oct-03    RMS     Cleaned up buffer copy code
  30    05-Dec-02    RMS     Updated from Type 24 documentation
  31    22-Nov-02    RMS     Added PDP-4 support
  32    05-Feb-02    RMS     Added DIB, device number support
  33    03-Feb-02    RMS     Fixed bug in reset routine (found by Robert Alan Byer)
  34    06-Jan-02    RMS     Revised enable/disable support
  35    25-Nov-01    RMS     Revised interrupt structure
  36    10-Jun-01    RMS     Cleaned up IOT decoding to reflect hardware
  37    26-Apr-01    RMS     Added device enable/disable support
  38    14-Apr-99    RMS     Changed t_addr to unsigned
  39 */
  40
  41 #include "pdp18b_defs.h"
  42 #include <math.h>
  43
  44 /* Constants */
  45
  46 #define DRM_NUMWDS      256                             /* words/sector */
  47 #define DRM_NUMSC       2                               /* sectors/track */
  48 #define DRM_NUMTR       256                             /* tracks/drum */
  49 #define DRM_NUMDK       1                               /* drum/controller */
  50 #define DRM_NUMWDT      (DRM_NUMWDS * DRM_NUMSC)        /* words/track */
  51 #define DRM_SIZE        (DRM_NUMDK * DRM_NUMTR * DRM_NUMWDT) /* words/drum */
  52 #define DRM_SMASK       ((DRM_NUMTR * DRM_NUMSC) - 1)   /* sector mask */
  53
  54 /* Parameters in the unit descriptor */
  55
  56 #define FUNC            u4                              /* function */
  57 #define DRM_READ        000                             /* read */
  58 #define DRM_WRITE       040                             /* write */
  59
  60 #define GET_POS(x)      ((int) fmod (sim_gtime() / ((double) (x)), \
  61                         ((double) DRM_NUMWDT)))
  62
  63 extern int32 M[];
  64 extern int32 int_hwre[API_HLVL+1];
  65 extern UNIT cpu_unit;
  66
  67 int32 drm_da = 0;                                       /* track address */
  68 int32 drm_ma = 0;                                       /* memory address */
  69 int32 drm_err = 0;                                      /* error flag */
  70 int32 drm_wlk = 0;                                      /* write lock */
  71 int32 drm_time = 10;                                    /* inter-word time */
  72 int32 drm_stopioe = 1;                                  /* stop on error */
  73
  74 DEVICE drm_dev;
  75 int32 drm60 (int32 dev, int32 pulse, int32 AC);
  76 int32 drm61 (int32 dev, int32 pulse, int32 AC);
  77 int32 drm62 (int32 dev, int32 pulse, int32 AC);
  78 int32 drm_iors (void);
  79 t_stat drm_svc (UNIT *uptr);
  80 t_stat drm_reset (DEVICE *dptr);
  81 t_stat drm_boot (int32 unitno, DEVICE *dptr);
  82
  83 /* DRM data structures
  84
  85    drm_dev      DRM device descriptor
  86    drm_unit     DRM unit descriptor
  87    drm_reg      DRM register list
  88 */
  89
  90 DIB drm_dib = { DEV_DRM, 3 ,&drm_iors, { &drm60, &drm61, &drm62 } };
  91
  92 UNIT drm_unit = {
  93     UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
  94            DRM_SIZE)
  95     };
  96
  97 REG drm_reg[] = {
  98     { ORDATA (DA, drm_da, 9) },
  99     { ORDATA (MA, drm_ma, 16) },
 100     { FLDATA (INT, int_hwre[API_DRM], INT_V_DRM) },
 101     { FLDATA (DONE, int_hwre[API_DRM], INT_V_DRM) },
 102     { FLDATA (ERR, drm_err, 0) },
 103     { ORDATA (WLK, drm_wlk, 32) },
 104     { DRDATA (TIME, drm_time, 24), REG_NZ + PV_LEFT },
 105     { FLDATA (STOP_IOE, drm_stopioe, 0) },
 106     { ORDATA (DEVNO, drm_dib.dev, 6), REG_HRO },
 107     { NULL }
 108     };
 109
 110 MTAB drm_mod[] = {
 111     { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
 112     { 0 }
 113     };
 114
 115 DEVICE drm_dev = {
 116     "DRM", &drm_unit, drm_reg, drm_mod,
 117     1, 8, 20, 1, 8, 18,
 118     NULL, NULL, &drm_reset,
 119     &drm_boot, NULL, NULL,
 120     &drm_dib, DEV_DISABLE
 121     };
 122
 123 /* IOT routines */
 124
 125 int32 drm60 (int32 dev, int32 pulse, int32 AC)
 126 {
 127 if ((pulse & 027) == 06) {                              /* DRLR, DRLW */
 128     drm_ma = AC & 0177777;                              /* load mem addr */
 129     drm_unit.FUNC = pulse & DRM_WRITE;                  /* save function */
 130     }
 131 return AC;
 132 }
 133
 134 int32 drm61 (int32 dev, int32 pulse, int32 AC)
 135 {
 136 int32 t;
 137
 138 if (pulse & 001) {                                      /* DRSF */
 139     if (TST_INT (DRM)) AC = AC | IOT_SKP;
 140     }
 141 if (pulse & 002) {                                      /* DRCF */
 142     CLR_INT (DRM);                                      /* clear done */
 143     drm_err = 0;                                        /* clear error */
 144     }
 145 if (pulse & 004) {                                      /* DRSS */
 146     drm_da = AC & DRM_SMASK;                            /* load sector # */
 147     t = ((drm_da % DRM_NUMSC) * DRM_NUMWDS) - GET_POS (drm_time);
 148     if (t <= 0) t = t + DRM_NUMWDT;                     /* wrap around? */
 149     sim_activate (&drm_unit, t * drm_time);             /* schedule op */
 150     }
 151 return AC;
 152 }
 153
 154 int32 drm62 (int32 dev, int32 pulse, int32 AC)
 155 {
 156 int32 t;
 157
 158 if (pulse & 001) {                                      /* DRSN */
 159     if (drm_err == 0) AC = AC | IOT_SKP;
 160     }
 161 if (pulse & 004) {                                      /* DRCS */
 162     CLR_INT (DRM);                                      /* clear done */
 163     drm_err = 0;                                        /* clear error */
 164     t = ((drm_da % DRM_NUMSC) * DRM_NUMWDS) - GET_POS (drm_time);
 165     if (t <= 0) t = t + DRM_NUMWDT;                     /* wrap around? */
 166     sim_activate (&drm_unit, t * drm_time);             /* schedule op */
 167     }
 168 return AC;
 169 }
 170
 171 /* Unit service
 172
 173    This code assumes the entire drum is buffered.
 174 */
 175
 176 t_stat drm_svc (UNIT *uptr)
 177 {
 178 int32 i;
 179 uint32 da;
 180 int32 *fbuf = uptr->filebuf;
 181
 182 if ((uptr->flags & UNIT_BUF) == 0) {                    /* not buf? abort */
 183     drm_err = 1;                                        /* set error */
 184     SET_INT (DRM);                                      /* set done */
 185     return IORETURN (drm_stopioe, SCPE_UNATT);
 186     }
 187
 188 da = drm_da * DRM_NUMWDS;                               /* compute dev addr */
 189 for (i = 0; i < DRM_NUMWDS; i++, da++) {                /* do transfer */
 190     if (uptr->FUNC == DRM_READ) {                       /* read? */
 191         if (MEM_ADDR_OK (drm_ma))                       /* if !nxm */
 192             M[drm_ma] = fbuf[da];                       /* read word */
 193         }
 194     else {                                              /* write */
 195         if ((drm_wlk >> (drm_da >> 4)) & 1) drm_err = 1;
 196         else {                                          /* not locked */
 197             fbuf[da] = M[drm_ma];                       /* write word */
 198             if (da >= uptr->hwmark) uptr->hwmark = da + 1;
 199             }
 200         }
 201     drm_ma = (drm_ma + 1) & 0177777;                    /* incr mem addr */
 202     }
 203 drm_da = (drm_da + 1) & DRM_SMASK;                      /* incr dev addr */
 204 SET_INT (DRM);                                          /* set done */
 205 return SCPE_OK;
 206 }
 207
 208 /* Reset routine */
 209
 210 t_stat drm_reset (DEVICE *dptr)
 211 {
 212 drm_da = drm_ma = drm_err = 0;
 213 CLR_INT (DRM);                                          /* clear done */
 214 sim_cancel (&drm_unit);
 215 return SCPE_OK;
 216 }
 217
 218 /* IORS routine */
 219
 220 int32 drm_iors (void)
 221 {
 222 return (TST_INT (DRM)? IOS_DRM: 0);
 223 }
 224
 225 /* Bootstrap routine */
 226
 227 #define BOOT_START 02000
 228 #define BOOT_LEN (sizeof (boot_rom) / sizeof (int))
 229
 230 static const int32 boot_rom[] = {
 231     0750000,                        /* CLA              ; dev, mem addr */
 232     0706006,                        /* DRLR             ; load ma */
 233     0706106,                        /* DRSS             ; load da, start */
 234     0706101,                        /* DRSF             ; wait for done */
 235     0602003,                        /* JMP .-1 */
 236     0600000                         /* JMP 0            ; enter boot */
 237         };
 238
 239 t_stat drm_boot (int32 unitno, DEVICE *dptr)
 240 {
 241 int32 i;
 242 extern int32 PC;
 243
 244 if (drm_dib.dev != DEV_DRM) return STOP_NONSTD;         /* non-std addr? */
 245 for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
 246 PC = BOOT_START;
 247 return SCPE_OK;
 248 }