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First Commit of my working state
[simh.git] / PDP18B / pdp18b_sys.c
1 /* pdp18b_sys.c: 18b PDP's simulator interface
2
3 Copyright (c) 1993-2006, Robert M Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 30-Oct-06 RMS Added infinite loop stop
27 18-Oct-06 RMS Re-ordered device list
28 02-Oct-06 RMS Added RDCLK instruction
29 12-Jun-06 RMS Added Fiodec, Baudot display
30 RMS Generalized LOAD to handle HRI, RIM, or BIN files
31 22-Jul-05 RMS Removed AAS, error in V1 reference manual
32 09-Jan-04 RMS Fixed instruction table errors
33 18-Oct-03 RMS Added DECtape off reel message
34 30-Jul-03 RMS Fixed FPM class mask
35 18-Jul-03 RMS Added FP15 support
36 02-Mar-03 RMS Split loaders apart for greater flexibility
37 09-Feb-03 RMS Fixed bug in FMTASC (found by Hans Pufal)
38 31-Jan-03 RMS Added support for RB09
39 05-Oct-02 RMS Added variable device number support
40 25-Jul-02 RMS Added PDP-4 DECtape support
41 10-Feb-02 RMS Added PDP-7 DECtape IOT's
42 03-Feb-02 RMS Fixed typo (found by Robert Alan Byer)
43 17-Sep-01 RMS Removed multiconsole support
44 27-May-01 RMS Added second Teletype support
45 18-May-01 RMS Added PDP-9,-15 API IOT's
46 12-May-01 RMS Fixed bug in RIM loaders
47 14-Mar-01 RMS Added extension detection of RIM format tapes
48 21-Jan-01 RMS Added DECtape support
49 30-Nov-00 RMS Added PDP-9,-15 RIM/BIN loader format
50 30-Oct-00 RMS Added support for examine to file
51 27-Oct-98 RMS V2.4 load interface
52 20-Oct-97 RMS Fixed endian dependence in RIM loader
53 (found by Michael Somos)
54 */
55
56 #include "pdp18b_defs.h"
57 #include <ctype.h>
58
59 extern DEVICE cpu_dev;
60 #if defined (PDP15)
61 extern DEVICE fpp_dev;
62 #endif
63 extern DEVICE ptr_dev, ptp_dev;
64 extern DEVICE tti_dev, tto_dev;
65 extern UNIT tti_unit, tto_unit;
66 extern DEVICE clk_dev;
67 #if defined (TYPE62)
68 extern DEVICE lp62_dev;
69 #endif
70 #if defined (TYPE647)
71 extern DEVICE lp647_dev;
72 #endif
73 #if defined (LP09)
74 extern DEVICE lp09_dev;
75 #endif
76 #if defined (LP15)
77 extern DEVICE lp15_dev;
78 #endif
79 extern DEVICE dt_dev;
80 #if defined (DRM)
81 extern DEVICE drm_dev;
82 #endif
83 #if defined (RB)
84 extern DEVICE rb_dev;
85 #endif
86 #if defined (RF)
87 extern DEVICE rf_dev;
88 #endif
89 #if defined (RP)
90 extern DEVICE rp_dev;
91 #endif
92 #if defined (MTA)
93 extern DEVICE mt_dev;
94 #endif
95 #if defined (TTY1)
96 extern DEVICE tti1_dev, tto1_dev;
97 extern UNIT tti1_unit, tto1_unit;
98 #endif
99 extern UNIT cpu_unit;
100 extern REG cpu_reg[];
101 extern int32 M[];
102 extern int32 memm;
103 extern int32 PC;
104 extern const char asc_to_baud[128];
105 extern const char baud_to_asc[64];
106 extern const char fio_to_asc[64];
107
108 /* SCP data structures and interface routines
109
110 sim_name simulator name string
111 sim_PC pointer to saved PC register descriptor
112 sim_emax number of words for examine
113 sim_devices array of pointers to simulated devices
114 sim_stop_messages array of pointers to stop messages
115 sim_load binary loader
116 */
117
118 #if defined (PDP4)
119 char sim_name[] = "PDP-4";
120 #elif defined (PDP7)
121 char sim_name[] = "PDP-7";
122 #elif defined (PDP9)
123 char sim_name[] = "PDP-9";
124 #elif defined (PDP15)
125 char sim_name[] = "PDP-15";
126 #endif
127
128 REG *sim_PC = &cpu_reg[0];
129
130 int32 sim_emax = 2;
131
132 DEVICE *sim_devices[] = {
133 &cpu_dev,
134 &clk_dev,
135 #if defined (PDP15)
136 &fpp_dev,
137 #endif
138 &ptr_dev,
139 &ptp_dev,
140 &tti_dev,
141 &tto_dev,
142 #if defined (TYPE62)
143 &lp62_dev,
144 #endif
145 #if defined (TYPE647)
146 &lp647_dev,
147 #endif
148 #if defined (LP09)
149 &lp09_dev,
150 #endif
151 #if defined (LP15)
152 &lp15_dev,
153 #endif
154 #if defined (DRM)
155 &drm_dev,
156 #endif
157 #if defined (RB)
158 &rb_dev,
159 #endif
160 #if defined (RF)
161 &rf_dev,
162 #endif
163 #if defined (RP)
164 &rp_dev,
165 #endif
166 &dt_dev,
167 #if defined (MTA)
168 &mt_dev,
169 #endif
170 #if defined (TTY1)
171 &tti1_dev, &tto1_dev,
172 #endif
173 NULL
174 };
175
176 const char *sim_stop_messages[] = {
177 "Unknown error",
178 "Undefined instruction",
179 "HALT instruction",
180 "Breakpoint",
181 "Nested XCT's",
182 "Invalid API interrupt",
183 "Non-standard device number",
184 "Memory management error",
185 "FP15 instruction disabled",
186 "DECtape off reel",
187 "Infinite loop"
188 };
189
190 /* Binary loaders */
191
192 int32 getword (FILE *fileref, int32 *hi)
193 {
194 int32 word, bits, st, ch;
195
196 word = st = bits = 0;
197 do {
198 if ((ch = getc (fileref)) == EOF) return -1;
199 if (ch & 0200) {
200 word = (word << 6) | (ch & 077);
201 bits = (bits << 1) | ((ch >> 6) & 1);
202 st++;
203 }
204 } while (st < 3);
205 if (hi != NULL) *hi = bits;
206 return word;
207 }
208
209 /* PDP-4/PDP-7 RIM format loader
210
211 Tape format
212 dac addr
213 data
214 :
215 dac addr
216 data
217 jmp addr or hlt
218 */
219
220 t_stat rim_load_47 (FILE *fileref, char *cptr)
221 {
222 int32 origin, val;
223
224 if (*cptr != 0) return SCPE_2MARG;
225 origin = 0200;
226 for (;;) {
227 if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
228 if ((val & 0760000) == 0040000) { /* DAC? */
229 origin = val & 017777;
230 if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
231 if (MEM_ADDR_OK (origin)) M[origin++] = val;
232 }
233 else if ((val & 0760000) == OP_JMP) { /* JMP? */
234 PC = ((origin - 1) & 060000) | (val & 017777);
235 return SCPE_OK;
236 }
237 else if (val == OP_HLT) break; /* HLT? */
238 else return SCPE_FMT; /* error */
239 }
240 return SCPE_OK; /* done */
241 }
242
243 /* PDP-7/9/15 hardware read-in format loader
244
245 Tape format (read in address specified externally)
246 data
247 :
248 data
249 word to execute (bit 1 of last character set)
250 */
251
252 t_stat hri_load_7915 (FILE *fileref, char *cptr)
253 {
254 int32 bits, origin, val;
255 char gbuf[CBUFSIZE];
256 t_stat r;
257
258 if (*cptr != 0) { /* more input? */
259 cptr = get_glyph (cptr, gbuf, 0); /* get origin */
260 origin = get_uint (gbuf, 8, AMASK, &r);
261 if (r != SCPE_OK) return r;
262 if (*cptr != 0) return SCPE_ARG; /* no more */
263 }
264 else origin = 0200; /* default 200 */
265
266 for (;;) { /* word loop */
267 if ((val = getword (fileref, &bits)) < 0) return SCPE_FMT;
268 if (bits & 1) { /* end of tape? */
269 if ((val & 0760000) == OP_JMP) PC =
270 ((origin - 1) & 060000) | (val & 017777);
271 else if (val != OP_HLT) return SCPE_FMT;
272 break;
273 }
274 else if (MEM_ADDR_OK (origin)) M[origin++] = val;
275 }
276 return SCPE_OK;
277 }
278
279 /* PDP-9/15 BIN format loader
280
281 BIN format (starts after RIM bootstrap)
282 block/ origin (>= 0)
283 count
284 checksum
285 data
286 :
287 data
288 block/
289 :
290 endblock/ origin (< 0)
291 */
292
293 t_stat bin_load_915 (FILE *fileref, char *cptr)
294 {
295 int32 i, val, bits, origin, count, cksum;
296
297 if (*cptr != 0) return SCPE_2MARG; /* no arguments */
298 do {
299 val = getword (fileref, & bits); /* find end RIM */
300 } while ((val >= 0) && ((bits & 1) == 0));
301 if (val < 0) rewind (fileref); /* no RIM? rewind */
302 for (;;) { /* block loop */
303 if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
304 if (val & SIGN) {
305 if (val != DMASK) PC = val & 077777;
306 break;
307 }
308 cksum = origin = val; /* save origin */
309 if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
310 cksum = cksum + val; /* add to cksum */
311 count = (-val) & DMASK; /* save count */
312 if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
313 cksum = cksum + val; /* add to cksum */
314 for (i = 0; i < count; i++) {
315 if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
316 cksum = cksum + val;
317 if (MEM_ADDR_OK (origin)) M[origin++] = val;
318 }
319 if ((cksum & DMASK) != 0) return SCPE_CSUM;
320 }
321 return SCPE_OK;
322 }
323
324 /* Binary loader, all formats */
325
326 t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
327 {
328 extern int32 sim_switches;
329
330 if (flag != 0) return SCPE_NOFNC;
331 if (sim_switches & SWMASK ('S')) /* RIM format? */
332 return rim_load_47 (fileref, cptr);
333 if (sim_switches & SWMASK ('R')) /* HRI format? */
334 return hri_load_7915 (fileref, cptr);
335 if (!(sim_switches & SWMASK ('B')) && /* .rim extension? */
336 match_ext (fnam, "RIM")) {
337 int32 val, bits;
338 do { /* look for HRI flag */
339 val = getword (fileref, &bits);
340 } while ((val >= 0) && ((bits & 1) == 0));
341 rewind (fileref); /* rewind file */
342 if (val < 0) return rim_load_47 (fileref, cptr); /* eof reached? */
343 return hri_load_7915 (fileref, cptr); /* no, HRI */
344 }
345 return bin_load_915 (fileref, cptr); /* must be BIN */
346 }
347
348 /* Symbol tables */
349
350 #define I_V_FL 18 /* inst class */
351 #define I_M_FL 017 /* class mask */
352 #define I_V_DC 22 /* default count */
353 #define I_V_NPN 0 /* no operand */
354 #define I_V_NPI 1 /* no operand IOT */
355 #define I_V_IOT 2 /* IOT */
356 #define I_V_MRF 3 /* memory reference */
357 #define I_V_OPR 4 /* OPR */
358 #define I_V_LAW 5 /* LAW */
359 #define I_V_XR 6 /* index */
360 #define I_V_XR9 7 /* index literal */
361 #define I_V_EST 8 /* EAE setup */
362 #define I_V_ESH 9 /* EAE shift */
363 #define I_V_EMD 10 /* EAE mul-div */
364 #define I_V_FPM 11 /* FP15 mem ref */
365 #define I_V_FPI 12 /* FP15 indirect */
366 #define I_V_FPN 13 /* FP15 no operand */
367 #define I_NPN (I_V_NPN << I_V_FL)
368 #define I_NPI (I_V_NPI << I_V_FL)
369 #define I_IOT (I_V_IOT << I_V_FL)
370 #define I_MRF (I_V_MRF << I_V_FL)
371 #define I_OPR (I_V_OPR << I_V_FL)
372 #define I_LAW (I_V_LAW << I_V_FL)
373 #define I_XR (I_V_XR << I_V_FL)
374 #define I_XR9 (I_V_XR9 << I_V_FL)
375 #define I_EST (I_V_EST << I_V_FL)
376 #define I_ESH (I_V_ESH << I_V_FL)
377 #define I_EMD (I_V_EMD << I_V_FL)
378 #define I_FPM (I_V_FPM << I_V_FL)
379 #define I_FPI (I_V_FPI << I_V_FL)
380 #define I_FPN (I_V_FPN << I_V_FL)
381 #define MD(x) ((I_EMD) + ((x) << I_V_DC))
382
383 static const int32 masks[] = {
384 0777777, 0777767, 0770000, 0760000,
385 0763730, 0760000, 0777000, 0777000,
386 0740700, 0760700, 0777700, 0777777,
387 0777777, 0777777
388 };
389
390 /* If both NPN (clear AC) and NPI versions of an IOT are defined,
391 the NPN version must come first */
392
393 static const char *opcode[] = {
394 "CAL", "DAC", "JMS", "DZM", /* mem refs */
395 "LAC", "XOR", "ADD", "TAD",
396 "XCT", "ISZ", "AND", "SAD",
397 "JMP",
398
399 #if defined (PDP9) || defined (PDP15) /* mem ref ind */
400 "CAL*", "DAC*", "JMS*", "DZM*", /* normal */
401 "LAC*", "XOR*", "ADD*", "TAD*",
402 "XCT*", "ISZ*", "AND*", "SAD*",
403 "JMP*",
404 #else
405 "CAL I", "DAC I", "JMS I", "DZM I", /* decode only */
406 "LAC I", "XOR I", "ADD I", "TAD I",
407 "XCT I", "ISZ I", "AND I", "SAD I",
408 "JMP I",
409 #endif
410
411 "LAW", /* LAW */
412
413 "LACQ", "LACS", "ABS", "GSM", "LMQ", /* EAE */
414 "MUL", "MULS", "DIV", "DIVS",
415 "IDIV", "IDIVS", "FRDIV", "FRDIVS",
416 "NORM", "NORMS",
417 "MUY", "LLK MUY", "DVI", "LLK DVI",
418 "NMI", "NMIS", "LRS", "LRSS",
419 "LLS", "LLSS", "ALS", "ALSS",
420 "EAE-setup", "EAE", /* setup, general */
421
422 "CLSF", "IOF", "ION", "CLOF", "CLON", /* standard IO devs */
423 "RSF", "RRB", "RCF", "RSA", "RSB",
424 "PSF", "PCF", "PSA", "PSB", "PLS",
425 "KSF", "KRB", "KCF", "IORS", "IOOS",
426 "TSF", "TCF", "TPC", "TLS",
427 #if defined (TYPE62) /* Type 62 */
428 "LPSF", "LPCF", "LPLD", "LPSE",
429 "LSSF", "LSCF", "LSPR",
430 #endif
431 #if defined (TYPE647) /* Type 647 */
432 "LPSF", "LPCB", "LPCD", "LPCD", "LPCD",
433 "LPL2", "LPLD", "LPL1",
434 "LPEF", "LPCF", "LPCF", "LPCF", "LPCF",
435 "LPPB", "LPLS", "LPPS",
436 #endif
437 #if defined (LP09)
438 "LSDF", "LSEF", "LSCF", "LPLD",
439 "LIOF", "LION",
440 #endif
441 #if defined (LP15) /* LP15 */
442 "LPSF", "LPPM", "LPP1", "LPDI",
443 "LPRS", "LPOS", "LPEI", "LPCD", "LPCF",
444 #endif
445 #if defined (DRM) /* drum */
446 "DRLR", "DRLW", "DRSS", "DRCS",
447 "DRSF", "DRSN", "DRCF",
448 "DRLCRD", "DRLCWR", "DRLBLK", "DRCONT",
449 "DRSF", "DRSOK", "DRCF",
450 #endif
451 #if defined (RB) /* RB09 */
452 "DBCF", "DBRD", "DBLD",
453 "DBSF", "DBRS", "DBLW",
454 "DBCS", "DBLM", "DBLS",
455 #endif
456 #if defined (RF) /* RF09 */
457 "DSSF", "DSCC", "DSCF",
458 "DRBR", "DRAL", "DSFX", "DRAH",
459 "DLBR", "DLAL", "DSCN", "DLAH",
460 "DLOK", "DSCD", "DSRS",
461 "DGHS", "DGSS",
462 #endif
463 #if defined (RP)
464 "DPSF", "DPSA", "DPSJ", "DPSE",
465 "DPRSA", "DPOSA", "DPRSB", "DPOSB",
466 "DPRM", "DPOM",
467 "DPLA", "DPCS", "DPCA", "DPWC",
468 "DPLM", "DPEM", "DPSN",
469 "DPRU", "DPOU", "DPRA", "DPOA",
470 "DPRC", "DPOC", "DPRW", "DPOW",
471 "DPCF", "DPLZ", "DPCN", "DPLO", "DPLF",
472 #endif
473 #if defined (MTA) /* TC59 */
474 "MTTR", "MTCR", "MTSF", "MTRC", "MTAF",
475 "MTRS", "MTGO", "MTCM", "MTLC",
476 #endif
477 #if defined (TYPE550) /* Type 550 */
478 "MMDF", "MMEF", "MMRD", "MMWR",
479 "MMBF", "MMRS", "MMLC", "MMSE",
480 #elif defined (TC02) /* TC02/TC15 */
481 "DTCA", "DTRA", "DTXA", "DTLA",
482 "DTEF", "DTRB", "DTDF",
483 #endif
484 #if defined (TTY1)
485 "KSF1", "KRB1",
486 "TSF1", "TCF1", "TLS1", "TCF1!TLS1",
487 #endif
488 #if defined (PDP7)
489 "ITON", "TTS", "SKP7", "CAF",
490 "SEM", "EEM", "EMIR", "LEM",
491 #endif
492 #if defined (PDP9)
493 "SKP7", "SEM", "EEM", "LEM",
494 "LPDI", "LPEI",
495 #endif
496 #if defined (PDP15)
497 "SPCO", "SKP15", "RES",
498 "SBA", "DBA", "EBA",
499 "RDMM", "ORMM", "LDMM", "MPLR",
500 "ENB", "INH",
501 "RDCLK","MPRC", "IPFH",
502 "PAX", "PAL", "AAC", "PXA",
503 "AXS", "PXL", "PLA", "PLX",
504 "CLAC","CLX", "CLLR", "AXR",
505
506 "FPT", /* FP15 */
507 "ISB", "ESB", /* mem ref */
508 "FSB", "URFSB", "UNFSB", "UUFSB",
509 "DSB", "URDSB", "UNDSB", "UUDSB",
510 "IRS", "ERS",
511 "FRS", "URFRS", "UNFRS", "UUFRS",
512 "DRS", "URDRS", "UNDRS", "UUDRS",
513 "IMP", "EMP",
514 "FMP", "URFMP", "UNFMP", "UUFMP",
515 "DMP", "URDMP", "UNDMP", "UUDMP",
516 "IDV", "EDV",
517 "FDV", "URFDV", "UNFDV", "UUFDV",
518 "DDV", "URDDV", "UNDDV", "UUDDV",
519 "IRD", "ERD",
520 "FRD", "URFRD", "UNFRD", "UUFRD",
521 "DRD", "URDRD", "UNDRD", "UUDRD",
522 "ILD", "ELD",
523 "FLD", "UNFLD", "DLD", "UNDLD",
524 "IST", "EST",
525 "FST", "URFST", "UNFST", "UUFST",
526 "DST", "UNDST",
527 "ILF", "UNILF", "ELF", "UNELF",
528 "FLX", "URFLX", "DLX", "URDLX",
529 "ILQ", "ELQ",
530 "FLQ", "UNFLQ", "DLQ", "UNDLQ",
531 "LJE", "SJE",
532 "IAD", "EAD",
533 "FAD", "URFAD", "UNFAD", "UUFAD",
534 "DAD", "URDAD", "UNDAD", "UUDAD",
535 "BZA", "BMA", "BLE", "BPA",
536 "BRU", "BNA", "BAC",
537 "ISB*", "ESB*", /* indirect */
538 "FSB*", "URFSB*", "UNFSB*", "UUFSB*",
539 "DSB*", "URDSB*", "UNDSB*", "UUDSB*",
540 "IRS*", "ERS*",
541 "FRS*", "URFRS*", "UNFRS*", "UUFRS*",
542 "DRS*", "URDRS*", "UNDRS*", "UUDRS*",
543 "IMP*", "EMP*",
544 "FMP*", "URFMP*", "UNFMP*", "UUFMP*",
545 "DMP*", "URDMP*", "UNDMP*", "UUDMP*",
546 "IDV*", "EDV*",
547 "FDV*", "URFDV*", "UNFDV*", "UUFDV*",
548 "DDV*", "URDDV*", "UNDDV*", "UUDDV*",
549 "IRD*", "ERD",
550 "FRD*", "URFRD*", "UNFRD*", "UUFRD*",
551 "DRD*", "URDRD*", "UNDRD*", "UUDRD*",
552 "ILD*", "ELD",
553 "FLD*", "UNFLD*", "DLD*", "UNDLD*",
554 "IST*", "EST",
555 "FST*", "URFST*", "UNFST*", "UUFST*",
556 "DST*", "UNDST*",
557 "ILF*", "UNILF*", "ELF*", "UNELF*",
558 "FLX*", "URFLX*", "DLX*", "URDLX*",
559 "ILQ*", "ELQ*",
560 "FLQ*", "UNFLQ*", "DLQ*", "UNDLQ*",
561 "LJE*", "SJE*",
562 "IAD*", "EAD*",
563 "FAD*", "URFAD*", "UNFAD*", "UUFAD*",
564 "DAD*", "URDAD*", "UNDAD*", "UUDAD*",
565
566 "FLA", "UNFLA", "FXA", "URFXA", /* no operand */
567 "SWQ", "UNSWQ", "FZR",
568 "FAB", "FNG", "FCM", "FNM",
569 #endif
570 #if defined (PDP9) || defined (PDP15)
571 "MPSK", "MPSNE", "MPCV", "MPEU",
572 "MPLD", "MPCNE", "PFSF",
573 "TTS", "CAF", "DBK", "DBR",
574 "SPI", "RPL", "ISA",
575 #endif
576 "IOT", /* general */
577
578 "NOP", "STL", "RCL", "RCR",
579 "CLC", "LAS", "GLK",
580 "OPR", "SMA", "SZA", "SZA SMA",
581 "SNL", "SNL SMA", "SNL SZA", "SNL SZA SMA",
582 "SKP", "SPA", "SNA", "SNA SPA",
583 "SZL", "SZL SPA", "SZL SNA", "SZL SZA SPA",
584 "RAL", "SMA RAL", "SZA RAL", "SZA SMA RAL",
585 "SNL RAL", "SNL SMA RAL", "SNL SZA RAL", "SNL SZA SMA RAL",
586 "SKP RAL", "SPA RAL", "SNA RAL", "SNA SPA RAL",
587 "SZL RAL", "SZL SPA RAL", "SZL SNA RAL", "SZL SZA SPA RAL",
588 "RAR", "SMA RAR", "SZA RAR", "SZA SMA RAR",
589 "SNL RAR", "SNL SMA RAR", "SNL SZA RAR", "SNL SZA SMA RAR",
590 "SKP RAR", "SPA RAR", "SNA RAR", "SNA SPA RAR",
591 "SZL RAR", "SZL SPA RAR", "SZL SNA RAR", "SZL SZA SPA RAR",
592 #if defined (PDP15)
593 "IAC", "SMA IAC", "SZA IAC", "SZA SMA IAC",
594 "SNL IAC", "SNL SMA IAC", "SNL SZA IAC", "SNL SZA SMA IAC",
595 "SKP IAC", "SPA IAC", "SNA IAC", "SNA SPA IAC",
596 "SZL IAC", "SZL SPA IAC", "SZL SNA IAC", "SZL SZA SPA IAC",
597 #else
598 "RAL RAR", "SMA RAL RAR", "SZA RAL RAR", "SZA SMA RAL RAR",
599 "SNL RAL RAR", "SNL SMA RAL RAR", "SNL SZA RAL RAR", "SNL SZA SMA RAL RAR",
600 "SKP RAL RAR", "SPA RAL RAR", "SNA RAL RAR", "SNA SPA RAL RAR",
601 "SZL RAL RAR", "SZL SPA RAL RAR", "SZL SNA RAL RAR", "SZL SZA SPA RAL RAR",
602 #endif
603 "RTWO", "SMA RTWO", "SZA RTWO", "SZA SMA RTWO",
604 "SNL RTWO", "SNL SMA RTWO", "SNL SZA RTWO", "SNL SZA SMA RTWO",
605 "SKP RTWO", "SPA RTWO", "SNA RTWO", "SNA SPA RTWO",
606 "SZL RTWO", "SZL SPA RTWO", "SZL SNA RTWO", "SZL SZA SPA RTWO",
607 "RTL", "SMA RTL", "SZA RTL", "SZA SMA RTL",
608 "SNL RTL", "SNL SMA RTL", "SNL SZA RTL", "SNL SZA SMA RTL",
609 "SKP RTL", "SPA RTL", "SNA RTL", "SNA SPA RTL",
610 "SZL RTL", "SZL SPA RTL", "SZL SNA RTL", "SZL SZA SPA RTL",
611 "RTR", "SMA RTR", "SZA RTR", "SZA SMA RTR",
612 "SNL RTR", "SNL SMA RTR", "SNL SZA RTR", "SNL SZA SMA RTR",
613 "SKP RTR", "SPA RTR", "SNA RTR", "SNA SPA RTR",
614 "SZL RTR", "SZL SPA RTR", "SZL SNA RTR", "SZL SZA SPA RTR",
615 #if defined (PDP15)
616 "BSW", "SMA BSW", "SZA BSW", "SZA SMA BSW",
617 "SNL BSW", "SNL SMA BSW", "SNL SZA BSW", "SNL SZA SMA BSW",
618 "SKP BSW", "SPA BSW", "SNA BSW", "SNA SPA BSW",
619 "SZL BSW", "SZL SPA BSW", "SZL SNA BSW", "SZL SZA SPA BSW",
620 #else
621 "RTL RTR", "SMA RTL RTR", "SZA RTL RTR", "SZA SMA RTL RTR",
622 "SNL RTL RTR", "SNL SMA RTL RTR", "SNL SZA RTL RTR", "SNL SZA SMA RTL RTR",
623 "SKP RTL RTR", "SPA RTL RTR", "SNA RTL RTR", "SNA SPA RTL RTR",
624 "SZL RTL RTR", "SZL SPA RTL RTR", "SZL SNA RTL RTR", "SZL SZA SPA RTL RTR",
625 #endif
626
627 "LLK", "CLQ", "LSN", "OACQ", "ECLA", /* encode only masks */
628 "CMQ", "OMQ", "OSC",
629 "CLA", "CLL", "CML", "CMA",
630 "OAS", "HLT",
631 NULL
632 };
633
634 static const int32 opc_val[] = {
635 0000000+I_MRF, 0040000+I_MRF, 0100000+I_MRF, 0140000+I_MRF,
636 0200000+I_MRF, 0240000+I_MRF, 0300000+I_MRF, 0340000+I_MRF,
637 0400000+I_MRF, 0440000+I_MRF, 0500000+I_MRF, 0540000+I_MRF,
638 0600000+I_MRF,
639 0020000+I_MRF, 0060000+I_MRF, 0120000+I_MRF, 0160000+I_MRF,
640 0220000+I_MRF, 0260000+I_MRF, 0320000+I_MRF, 0360000+I_MRF,
641 0420000+I_MRF, 0460000+I_MRF, 0520000+I_MRF, 0560000+I_MRF,
642 0620000+I_MRF,
643
644 0760000+I_LAW,
645
646 0641002+I_NPN, 0641001+I_NPN, 0644000+I_NPN, 0664000+I_NPN, 0652000+I_NPN,
647 0653100+MD(022), 0657100+MD(022), 0640300+MD(023), 0644300+MD(023),
648 0653300+MD(023), 0657300+MD(023), 0650300+MD(023), 0654300+MD(023),
649 0640400+MD(044), 0660400+MD(044),
650 0640100+I_ESH, 0660100+I_ESH, 0640300+I_ESH, 0660300+I_ESH,
651 0640400+I_ESH, 0660400+I_ESH, 0640500+I_ESH, 0660500+I_ESH,
652 0640600+I_ESH, 0660600+I_ESH, 0640700+I_ESH, 0660700+I_ESH,
653 0640000+I_EST, 0640000+I_IOT,
654
655 0700001+I_NPI, 0700002+I_NPI, 0700042+I_NPI, 0700004+I_NPI, 0700044+I_NPI,
656 0700101+I_NPI, 0700112+I_NPN, 0700102+I_NPI, 0700104+I_NPI, 0700144+I_NPI,
657 0700201+I_NPI, 0700202+I_NPI, 0700204+I_NPI, 0700244+I_NPI, 0700206+I_NPI,
658 0700301+I_NPI, 0700312+I_NPN, 0700302+I_NPI, 0700314+I_NPN, 0700304+I_NPI,
659 0700401+I_NPI, 0700402+I_NPI, 0700404+I_NPI, 0700406+I_NPI,
660 #if defined (TYPE62)
661 0706501+I_NPI, 0706502+I_NPI, 0706542+I_NPI, 0706506+I_NPI,
662 0706601+I_NPI, 0706602+I_NPI, 0706606+I_NPI,
663 #endif
664 #if defined (TYPE647)
665 0706501+I_NPI, 0706502+I_NPI, 0706522+I_NPI, 0706542+I_NPI, 0706562+I_NPI,
666 0706526+I_NPI, 0706546+I_NPI, 0706566+I_NPI,
667 0706601+I_NPI, 0706602+I_NPI, 0706622+I_NPI, 0706642+I_NPI, 0706662+I_NPI,
668 0706606+I_NPI, 0706626+I_NPI, 0706646+I_NPI,
669 #endif
670 #if defined (LP09)
671 0706601+I_NPI, 0706621+I_NPI, 0706602+I_NPI, 0706622+I_NPI,
672 0706604+I_NPI, 0706644+I_NPI,
673 #endif
674 #if defined (LP15)
675 0706501+I_NPI, 0706521+I_NPI, 0706541+I_NPI, 0706561+I_NPI,
676 0706552+I_NPN, 0706542+I_NPI, 0706544+I_NPI, 0706621+I_NPI, 0706641+I_NPI,
677 #endif
678 #if defined (DRM)
679 0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,
680 0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,
681 0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,
682 0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,
683 #endif
684 #if defined (RB)
685 0707101+I_NPI, 0707112+I_NPN, 0707104+I_NPI,
686 0707121+I_NPI, 0707132+I_NPN, 0707124+I_NPI,
687 0707141+I_NPI, 0707142+I_NPI, 0707144+I_NPI,
688 #endif
689 #if defined (RF)
690 0707001+I_NPI, 0707021+I_NPI, 0707041+I_NPI,
691 0707002+I_NPI, 0707022+I_NPI, 0707042+I_NPI, 0707062+I_NPI,
692 0707004+I_NPI, 0707024+I_NPI, 0707044+I_NPI, 0707064+I_NPI,
693 0707202+I_NPI, 0707242+I_NPI, 0707262+I_NPI,
694 0707204+I_NPI, 0707224+I_NPI,
695 #endif
696 #if defined (RP)
697 0706301+I_NPI, 0706321+I_NPI, 0706341+I_NPI, 0706361+I_NPI,
698 0706312+I_NPN, 0706302+I_NPI, 0706332+I_NPN, 0706322+I_NPI,
699 0706352+I_NPN, 0706342+I_NPI,
700 0706304+I_NPI, 0706324+I_NPI, 0706344+I_NPI, 0706364+I_NPI,
701 0706411+I_NPN, 0706401+I_NPI, 0706421+I_NPI,
702 0706412+I_NPN, 0706402+I_NPI, 0706432+I_NPN, 0706422+I_NPI,
703 0706452+I_NPN, 0706442+I_NPI, 0706472+I_NPN, 0706462+I_NPI,
704 0706404+I_NPI, 0706424+I_NPI, 0706454+I_NPN, 0706444+I_NPI, 0706464+I_NPI,
705 #endif
706 #if defined (MTA)
707 0707301+I_NPI, 0707321+I_NPI, 0707341+I_NPI, 0707312+I_NPN, 0707322+I_NPI,
708 0707352+I_NPN, 0707304+I_NPI, 0707324+I_NPI, 0707326+I_NPI,
709 #endif
710 #if defined (TYPE550) /* Type 550 */
711 0707501+I_NPI, 0707541+I_NPI, 0707512+I_NPN, 0707504+I_NPI,
712 0707601+I_NPI, 0707612+I_NPN, 0707604+I_NPI, 0707644+I_NPI,
713 #elif defined (TC02) /* TC02/TC15 */
714 0707541+I_NPI, 0707552+I_NPN, 0707544+I_NPI, 0707545+I_NPI,
715 0707561+I_NPI, 0707572+I_NPN, 0707601+I_NPI,
716 #endif
717 #if defined (TTY1)
718 0704101+I_NPI, 0704112+I_NPN,
719 0704001+I_NPI, 0704002+I_NPI, 0704004+I_NPI, 0704006+I_NPI,
720 #endif
721 #if defined (PDP7)
722 0703201+I_NPI, 0703301+I_NPI, 0703341+I_NPI, 0703302+I_NPI,
723 0707701+I_NPI, 0707702+I_NPI, 0707742+I_NPI, 0707704+I_NPI,
724 #endif
725 #if defined (PDP9)
726 0703341+I_NPI, 0707701+I_NPI, 0707702+I_NPI, 0707704+I_NPI,
727 0706504+I_NPI, 0706604+I_NPI,
728 #endif
729 #if defined (PDP15)
730 0703341+I_NPI, 0707741+I_NPI, 0707742+I_NPI,
731 0707761+I_NPI, 0707762+I_NPI, 0707764+I_NPI,
732 0700032+I_NPN, 0700022+I_NPI, 0700024+I_NPI, 0701724+I_NPI,
733 0705521+I_NPI, 0705522+I_NPI,
734 0701772+I_NPN, 0701762+I_NPI, 0701764+I_NPI,
735 0721000+I_XR, 0722000+I_XR, 0723000+I_XR9, 0724000+I_XR,
736 0725000+I_XR9, 0726000+I_XR, 0730000+I_XR, 0731000+I_XR,
737 0734000+I_XR, 0735000+I_XR, 0736000+I_XR, 0737000+I_XR9,
738
739 0710314+I_FPN,
740 0710400+I_FPM, 0710500+I_FPM,
741 0710440+I_FPM, 0710450+I_FPM, 0710460+I_FPM, 0710470+I_FPM,
742 0710540+I_FPM, 0710550+I_FPM, 0710560+I_FPM, 0710570+I_FPM,
743 0711000+I_FPM, 0711100+I_FPM,
744 0711040+I_FPM, 0711050+I_FPM, 0711060+I_FPM, 0711070+I_FPM,
745 0711140+I_FPM, 0711150+I_FPM, 0711160+I_FPM, 0711170+I_FPM,
746 0711400+I_FPM, 0711500+I_FPM,
747 0711440+I_FPM, 0711450+I_FPM, 0711460+I_FPM, 0711470+I_FPM,
748 0711540+I_FPM, 0711550+I_FPM, 0711560+I_FPM, 0711570+I_FPM,
749 0712000+I_FPM, 0712100+I_FPM,
750 0712040+I_FPM, 0712050+I_FPM, 0712060+I_FPM, 0712070+I_FPM,
751 0712140+I_FPM, 0712150+I_FPM, 0712160+I_FPM, 0712170+I_FPM,
752 0712400+I_FPM, 0712500+I_FPM,
753 0712440+I_FPM, 0712450+I_FPM, 0712460+I_FPM, 0712470+I_FPM,
754 0712540+I_FPM, 0712550+I_FPM, 0712560+I_FPM, 0712570+I_FPM,
755 0713000+I_FPM, 0713100+I_FPM,
756 0713050+I_FPM, 0713070+I_FPM, 0713150+I_FPM, 0713170+I_FPM,
757 0713600+I_FPM, 0713700+I_FPM,
758 0713640+I_FPM, 0713650+I_FPM, 0713660+I_FPM, 0713670+I_FPM,
759 0713750+I_FPM, 0713770+I_FPM,
760 0714010+I_FPM, 0714030+I_FPM, 0714110+I_FPM, 0714130+I_FPM,
761 0714460+I_FPM, 0714470+I_FPM, 0714560+I_FPM, 0714570+I_FPM,
762 0715000+I_FPM, 0715100+I_FPM,
763 0715050+I_FPM, 0715070+I_FPM, 0715150+I_FPM, 0715170+I_FPM,
764 0715400+I_FPM, 0715600+I_FPM,
765 0716000+I_FPM, 0716100+I_FPM,
766 0716040+I_FPM, 0716050+I_FPM, 0716060+I_FPM, 0716070+I_FPM,
767 0716140+I_FPM, 0716150+I_FPM, 0716160+I_FPM, 0716170+I_FPM,
768 0716601+I_FPM, 0716602+I_FPM, 0716603+I_FPM,
769 0716604+I_FPM, 0716606+I_FPM, 0716610+I_FPM, 0716620+I_FPM,
770 0710400+I_FPI, 0710500+I_FPI, /* indirect */
771 0710440+I_FPI, 0710450+I_FPI, 0710460+I_FPI, 0710470+I_FPI,
772 0710540+I_FPI, 0710550+I_FPI, 0710560+I_FPI, 0710570+I_FPI,
773 0711000+I_FPI, 0711100+I_FPI,
774 0711040+I_FPI, 0711050+I_FPI, 0711060+I_FPI, 0711070+I_FPI,
775 0711140+I_FPI, 0711150+I_FPI, 0711160+I_FPI, 0711170+I_FPI,
776 0711400+I_FPI, 0711500+I_FPI,
777 0711440+I_FPI, 0711450+I_FPI, 0711460+I_FPI, 0711470+I_FPI,
778 0711540+I_FPI, 0711550+I_FPI, 0711560+I_FPI, 0711570+I_FPI,
779 0712000+I_FPI, 0712100+I_FPI,
780 0712040+I_FPI, 0712050+I_FPI, 0712060+I_FPI, 0712070+I_FPI,
781 0712140+I_FPI, 0712150+I_FPI, 0712160+I_FPI, 0712170+I_FPI,
782 0712400+I_FPI, 0712500+I_FPI,
783 0712440+I_FPI, 0712450+I_FPI, 0712460+I_FPI, 0712470+I_FPI,
784 0712540+I_FPI, 0712550+I_FPI, 0712560+I_FPI, 0712570+I_FPI,
785 0713000+I_FPI, 0713100+I_FPI,
786 0713050+I_FPI, 0713070+I_FPI, 0713150+I_FPI, 0713170+I_FPI,
787 0713600+I_FPI, 0713700+I_FPI,
788 0713640+I_FPI, 0713650+I_FPI, 0713660+I_FPI, 0713670+I_FPI,
789 0713750+I_FPI, 0713770+I_FPI,
790 0714010+I_FPI, 0714030+I_FPI, 0714110+I_FPI, 0714130+I_FPI,
791 0714460+I_FPI, 0714470+I_FPI, 0714560+I_FPI, 0714570+I_FPI,
792 0715000+I_FPI, 0715100+I_FPI,
793 0715050+I_FPI, 0715070+I_FPI, 0715150+I_FPI, 0715170+I_FPI,
794 0715400+I_FPI, 0715600+I_FPI,
795 0716000+I_FPI, 0716100+I_FPI,
796 0716040+I_FPI, 0716050+I_FPI, 0716060+I_FPI, 0716070+I_FPI,
797 0716140+I_FPI, 0716150+I_FPI, 0716160+I_FPI, 0716170+I_FPI,
798 0714210+I_FPN, 0714230+I_FPN, 0714660+I_FPN, 0714670+I_FPN,
799 0715250+I_FPN, 0715270+I_FPN, 0711200+I_FPN,
800 0713271+I_FPN, 0713272+I_FPN, 0713273+I_FPN, 0713250+I_FPN,
801 #endif
802 #if defined (PDP9) || defined (PDP15)
803 0701701+I_NPI, 0701741+I_NPI, 0701702+I_NPI, 0701742+I_NPI,
804 0701704+I_NPI, 0701744+I_NPI, 0703201+I_NPI,
805 0703301+I_NPI, 0703302+I_NPI, 0703304+I_NPI, 0703344+I_NPI,
806 0705501+I_NPI, 0705512+I_NPN, 0705504+I_NPI,
807 #endif
808 0700000+I_IOT,
809
810 0740000+I_NPN, 0744002+I_NPN, 0744010+I_NPN, 0744020+I_NPN,
811 0750001+I_NPN, 0750004+I_NPN, 0750010+I_NPN,
812 0740000+I_OPR, 0740100+I_OPR, 0740200+I_OPR, 0740300+I_OPR,
813 0740400+I_OPR, 0740500+I_OPR, 0740600+I_OPR, 0740700+I_OPR,
814 0741000+I_OPR, 0741100+I_OPR, 0741200+I_OPR, 0741300+I_OPR,
815 0741400+I_OPR, 0741500+I_OPR, 0741600+I_OPR, 0741700+I_OPR,
816 0740010+I_OPR, 0740110+I_OPR, 0740210+I_OPR, 0740310+I_OPR,
817 0740410+I_OPR, 0740510+I_OPR, 0740610+I_OPR, 0740710+I_OPR,
818 0741010+I_OPR, 0741110+I_OPR, 0741210+I_OPR, 0741310+I_OPR,
819 0741410+I_OPR, 0741510+I_OPR, 0741610+I_OPR, 0741710+I_OPR,
820 0740020+I_OPR, 0740120+I_OPR, 0740220+I_OPR, 0740320+I_OPR,
821 0740420+I_OPR, 0740520+I_OPR, 0740620+I_OPR, 0740720+I_OPR,
822 0741020+I_OPR, 0741120+I_OPR, 0741220+I_OPR, 0741320+I_OPR,
823 0741420+I_OPR, 0741520+I_OPR, 0741620+I_OPR, 0741720+I_OPR,
824 0740030+I_OPR, 0740130+I_OPR, 0740230+I_OPR, 0740330+I_OPR,
825 0740430+I_OPR, 0740530+I_OPR, 0740630+I_OPR, 0740730+I_OPR,
826 0741030+I_OPR, 0741130+I_OPR, 0741230+I_OPR, 0741330+I_OPR,
827 0741430+I_OPR, 0741530+I_OPR, 0741630+I_OPR, 0741730+I_OPR,
828 0742000+I_OPR, 0742100+I_OPR, 0742200+I_OPR, 0742300+I_OPR,
829 0742400+I_OPR, 0742500+I_OPR, 0742600+I_OPR, 0742700+I_OPR,
830 0743000+I_OPR, 0743100+I_OPR, 0743200+I_OPR, 0743300+I_OPR,
831 0743400+I_OPR, 0743500+I_OPR, 0743600+I_OPR, 0743700+I_OPR,
832 0742010+I_OPR, 0742110+I_OPR, 0742210+I_OPR, 0742310+I_OPR,
833 0742410+I_OPR, 0742510+I_OPR, 0742610+I_OPR, 0742710+I_OPR,
834 0743010+I_OPR, 0743110+I_OPR, 0743210+I_OPR, 0743310+I_OPR,
835 0743410+I_OPR, 0743510+I_OPR, 0743610+I_OPR, 0743710+I_OPR,
836 0742020+I_OPR, 0742120+I_OPR, 0742220+I_OPR, 0742320+I_OPR,
837 0742420+I_OPR, 0742520+I_OPR, 0742620+I_OPR, 0742720+I_OPR,
838 0743020+I_OPR, 0743120+I_OPR, 0743220+I_OPR, 0743320+I_OPR,
839 0743420+I_OPR, 0743520+I_OPR, 0743620+I_OPR, 0743720+I_OPR,
840 0742030+I_OPR, 0742130+I_OPR, 0742230+I_OPR, 0742330+I_OPR,
841 0742430+I_OPR, 0742530+I_OPR, 0742630+I_OPR, 0742730+I_OPR,
842 0743030+I_OPR, 0743130+I_OPR, 0743230+I_OPR, 0743330+I_OPR,
843 0743430+I_OPR, 0743530+I_OPR, 0743630+I_OPR, 0743730+I_OPR,
844
845 0660000+I_EST, 0650000+I_EST, 0644000+I_EST, 0642000+I_EST, 0641000+I_EST,
846 0640004+I_EST, 0640002+I_EST, 0640001+I_EST,
847 0750000+I_OPR, 0744000+I_OPR, 0740002+I_OPR, 0740001+I_OPR,
848 0740004+I_OPR, 0740040+I_OPR,
849 -1
850 };
851
852 /* Operate or EAE decode
853
854 Inputs:
855 *of = output stream
856 inst = mask bits
857 class = instruction class code
858 sp = space needed?
859 Outputs:
860 status = space needed?
861 */
862
863 int32 fprint_opr (FILE *of, int32 inst, int32 class, int32 sp)
864 {
865 int32 i, j;
866
867 for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
868 j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
869 if ((j == class) && (opc_val[i] & inst)) { /* same class? */
870 inst = inst & ~opc_val[i]; /* mask bit set? */
871 fprintf (of, (sp? " %s": "%s"), opcode[i]);
872 sp = 1;
873 }
874 }
875 return sp;
876 }
877
878 static int32 rar (int32 c)
879 {
880 c = c & 077;
881 return (c >> 1) | (c << 5);
882 }
883
884 /* Symbolic decode
885
886 Inputs:
887 *of = output stream
888 addr = current PC
889 *val = pointer to values
890 *uptr = pointer to unit
891 sw = switches
892 Outputs:
893 return = status code
894 */
895
896 #define FMTASC(x) (((x) < 040)? "<%03o>": "%c"), (x)
897 #define SIXTOASC(x) (((x) >= 040)? (x): ((x) + 0100))
898
899 t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
900 UNIT *uptr, int32 sw)
901 {
902 int32 cflag, i, j, k, sp, inst, disp, ma;
903
904 inst = val[0];
905 cflag = (uptr == NULL) || (uptr == &cpu_unit);
906 if (sw & SWMASK ('A')) { /* ASCII? */
907 if (inst > 0377) return SCPE_ARG;
908 fprintf (of, FMTASC (inst & 0177));
909 return SCPE_OK;
910 }
911 if (sw & SWMASK ('C')) { /* character? */
912 fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077));
913 fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));
914 fprintf (of, "%c", SIXTOASC (inst & 077));
915 return SCPE_OK;
916 }
917 #if defined (PDP4) || defined (PDP7)
918 if (sw & SWMASK ('F')) { /* FIODEC? */
919 fprintf (of, "%c", fio_to_asc[(inst >> 12) & 077]);
920 fprintf (of, "%c", fio_to_asc[(inst >> 6) & 077]);
921 fprintf (of, "%c", fio_to_asc[inst & 077]);
922 return SCPE_OK;
923 }
924 if (sw & SWMASK ('B')) { /* Baudot? */
925 fprintf (of, "%c", baud_to_asc[rar (inst >> 12) & 077]);
926 fprintf (of, "%c", baud_to_asc[rar (inst >> 6) & 077]);
927 fprintf (of, "%c", baud_to_asc[rar (inst) & 077]);
928 return SCPE_OK;
929 }
930 #endif
931 #if defined (PDP15)
932 if (sw & SWMASK ('P')) { /* packed ASCII? */
933 i = val[1];
934 fprintf (of, FMTASC ((inst >> 11) & 0177));
935 fprintf (of, FMTASC ((inst >> 4) & 0177));
936 fprintf (of, FMTASC (((inst << 3) | (i >> 15)) & 0177));
937 fprintf (of, FMTASC ((i >> 8) & 0177));
938 fprintf (of, FMTASC ((i >> 1) & 0177));
939 return -1;
940 }
941 #endif
942 if (!(sw & SWMASK ('M'))) return SCPE_ARG;
943
944 /* Instruction decode */
945
946 for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
947 j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
948 if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
949
950 switch (j) { /* case on class */
951
952 case I_V_NPN: /* no operands */
953 case I_V_XR: /* index no opers */
954 fprintf (of, "%s", opcode[i]); /* opcode */
955 break;
956
957 case I_V_NPI: /* IOT no operand */
958 fprintf (of, "%s", opcode[i]); /* opcode */
959 if (inst & 010) fprintf (of, " +10");
960 break;
961
962 case I_V_IOT: /* IOT or EAE */
963 fprintf (of, "%s %-o", opcode[i], inst & 037777);
964 break;
965
966 case I_V_MRF: /* mem ref */
967 #if defined (PDP15)
968 if (memm) {
969 disp = inst & B_DAMASK;
970 ma = (addr & (AMASK & ~B_DAMASK)) | disp;
971 }
972 else {
973 disp = inst & P_DAMASK;
974 ma = (addr & (AMASK & ~P_DAMASK)) | disp;
975 }
976 fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));
977 if (!memm && (inst & I_IDX)) fprintf (of, ",X");
978 #else
979 disp = inst & B_DAMASK;
980 ma = (addr & (AMASK & ~B_DAMASK)) | disp;
981 fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));
982 #endif
983 break;
984
985 case I_V_OPR: /* operate */
986 if (sp = (inst & 03730)) fprintf (of, "%s", opcode[i]);
987 fprint_opr (of, inst & 014047, I_V_OPR, sp);
988 break;
989
990 case I_V_LAW: /* LAW */
991 fprintf (of, "%s %-o", opcode[i], inst & 017777);
992 break;
993
994 case I_V_XR9: /* index with lit */
995 disp = inst & 0777;
996 if (disp & 0400) fprintf (of, "%s -%-o", opcode[i], 01000 - disp);
997 else fprintf (of, "%s %-o", opcode[i], disp);
998 break;
999
1000 case I_V_EST: /* EAE setup */
1001 fprint_opr (of, inst & 037007, I_V_EST, 0);
1002 break;
1003
1004 case I_V_ESH: /* EAE shift */
1005 sp = fprint_opr (of, inst & 017000, I_V_EST, 0);
1006 fprintf (of, (sp? " %s %-o": "%s %-o"), opcode[i], inst & 077);
1007 break;
1008
1009 case I_V_EMD: /* EAE mul-div */
1010 disp = inst & 077; /* get actual val */
1011 k = (opc_val[i] >> I_V_DC) & 077; /* get default val */
1012 if (disp == k) fprintf (of, "%s", opcode[i]);
1013 else if (disp < k) fprintf (of, "%s -%-o", opcode[i], k - disp);
1014 else fprintf (of, "%s +%-o", opcode[i], disp - k);
1015 break;
1016
1017 case I_V_FPM: case I_V_FPI: /* FP15 mem ref */
1018 fprintf (of, "%s", opcode[i]);
1019 if (val[1] & SIGN) fputc ('*', of);
1020 fprintf (of, " %-o", val[1] & ~SIGN);
1021 return -1;
1022
1023 case I_V_FPN: /* FP15 no operand */
1024 fprintf (of, "%s", opcode[i]);
1025 return -1;
1026 } /* end case */
1027 return SCPE_OK;
1028 } /* end if */
1029 } /* end for */
1030 return SCPE_ARG;
1031 }
1032
1033 /* Get 18b signed number
1034
1035 Inputs:
1036 *cptr = pointer to input string
1037 *sign = pointer to sign
1038 *status = pointer to error status
1039 Outputs:
1040 val = output value
1041 */
1042
1043 t_value get_sint (char *cptr, int32 *sign, t_stat *status)
1044 {
1045 *sign = 0;
1046 if (*cptr == '+') {
1047 *sign = 1;
1048 cptr++;
1049 }
1050 else if (*cptr == '-') {
1051 *sign = -1;
1052 cptr++;
1053 }
1054 return get_uint (cptr, 8, 0777777, status);
1055 }
1056
1057 /* Symbolic input
1058
1059 Inputs:
1060 *cptr = pointer to input string
1061 addr = current PC
1062 uptr = pointer to unit
1063 *val = pointer to output values
1064 sw = switches
1065 Outputs:
1066 status = error status
1067 */
1068
1069 t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
1070 {
1071 int32 cflag, d, i, j, k, sign, damask, epcmask;
1072 t_stat r, sta = SCPE_OK;
1073 char gbuf[CBUFSIZE];
1074
1075 cflag = (uptr == NULL) || (uptr == &cpu_unit);
1076 while (isspace (*cptr)) cptr++;
1077 for (i = 1; (i < 5) && (cptr[i] != 0); i++)
1078 if (cptr[i] == 0) for (j = i + 1; j <= 5; j++) cptr[j] = 0;
1079 if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
1080 if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
1081 val[0] = (t_value) cptr[0] | 0200;
1082 return SCPE_OK;
1083 }
1084 if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */
1085 if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
1086 val[0] = (((t_value) cptr[0] & 077) << 12) |
1087 (((t_value) cptr[1] & 077) << 6) |
1088 ((t_value) cptr[2] & 077);
1089 return SCPE_OK;
1090 }
1091 #if defined (PDP15)
1092 if ((sw & SWMASK ('P')) || ((*cptr == '#') && cptr++)) { /* packed string? */
1093 if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
1094 val[0] = (((t_value) cptr[0] & 0177) << 11) |
1095 (((t_value) cptr[1] & 0177) << 4) |
1096 (((t_value) cptr[2] & 0170) >> 3);
1097 val[1] = (((t_value) cptr[2] & 0007) << 15) |
1098 (((t_value) cptr[3] & 0177) << 8) |
1099 (((t_value) cptr[4] & 0177) << 1);
1100 return -1;
1101 }
1102 #endif
1103
1104 cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
1105 for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
1106 if (opcode[i] == NULL) return SCPE_ARG;
1107 val[0] = opc_val[i] & DMASK; /* get value */
1108 j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
1109
1110 switch (j) { /* case on class */
1111
1112 case I_V_XR: /* index */
1113 break;
1114
1115 case I_V_XR9: /* index literal */
1116 cptr = get_glyph (cptr, gbuf, 0); /* get next field */
1117 d = get_sint (gbuf, &sign, &r);
1118 if (r != SCPE_OK) return SCPE_ARG;
1119 if (((sign >= 0) && (d > 0377)) || ((sign < 0) && (d > 0400)))
1120 return SCPE_ARG;
1121 val[0] = val[0] | ((sign >= 0)? d: (01000 - d));
1122 break;
1123
1124 case I_V_LAW: /* law */
1125 cptr = get_glyph (cptr, gbuf, 0); /* get next field */
1126 d = get_uint (gbuf, 8, 017777, &r);
1127 if (r != SCPE_OK) return SCPE_ARG;
1128 val[0] = val[0] | d;
1129 break;
1130
1131 case I_V_MRF: /* mem ref */
1132 #if defined (PDP15)
1133 if (memm) damask = B_DAMASK;
1134 else damask = P_DAMASK;
1135 cptr = get_glyph (cptr, gbuf, ','); /* get glyph */
1136 #else
1137 damask = B_DAMASK;
1138 cptr = get_glyph (cptr, gbuf, 0); /* get next field */
1139 #endif
1140 #if defined (PDP4) || defined (PDP7)
1141 if (strcmp (gbuf, "I") == 0) { /* indirect? */
1142 val[0] = val[0] | I_IND;
1143 cptr = get_glyph (cptr, gbuf, 0);
1144 }
1145 #endif
1146 epcmask = AMASK & ~damask; /* get ePC */
1147 d = get_uint (gbuf, 8, AMASK, &r); /* get addr */
1148 if (r != SCPE_OK) return SCPE_ARG;
1149 if (d <= damask) val[0] = val[0] | d; /* fit in 12/13b? */
1150 else if (cflag && (((addr ^ d) & epcmask) == 0))
1151 val[0] = val[0] | (d & damask); /* hi bits = ePC? */
1152 else return SCPE_ARG;
1153 #if defined (PDP15)
1154 if (!memm) {
1155 cptr = get_glyph (cptr, gbuf, 0);
1156 if (gbuf[0] != 0) {
1157 if (strcmp (gbuf, "X") != 0) return SCPE_ARG;
1158 val[0] = val[0] | I_IDX;
1159 }
1160 }
1161 #endif
1162 break;
1163
1164 case I_V_EMD: /* or'able */
1165 val[0] = val[0] | ((opc_val[i] >> I_V_DC) & 077); /* default shift */
1166 case I_V_EST: case I_V_ESH:
1167 case I_V_NPN: case I_V_NPI:
1168 case I_V_IOT: case I_V_OPR:
1169 for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
1170 cptr = get_glyph (cptr, gbuf, 0)) {
1171 for (i = 0; (opcode[i] != NULL) &&
1172 (strcmp (opcode[i], gbuf) != 0) ; i++) ;
1173 if (opcode[i] != NULL) {
1174 k = opc_val[i] & DMASK;
1175 if (((k ^ val[0]) & 0740000) != 0) return SCPE_ARG;
1176 val[0] = val[0] | k;
1177 }
1178 else {
1179 d = get_sint (gbuf, & sign, &r);
1180 if (r != SCPE_OK) return SCPE_ARG;
1181 if (sign > 0) val[0] = val[0] + d;
1182 else if (sign < 0) val[0] = val[0] - d;
1183 else val[0] = val[0] | d;
1184 }
1185 }
1186 break;
1187
1188 case I_V_FPM: /* FP15 mem ref */
1189 cptr = get_glyph (cptr, gbuf, 0); /* get next field */
1190 val[1] = get_uint (gbuf, 8, AMASK, &r); /* get addr */
1191 if (r != SCPE_OK) return SCPE_ARG;
1192 sta = -1;
1193 break;
1194
1195 case I_V_FPI: /* FP15 ind mem ref */
1196 cptr = get_glyph (cptr, gbuf, 0); /* get next field */
1197 val[1] = get_uint (gbuf, 8, AMASK, &r) | SIGN; /* get @addr */
1198 if (r != SCPE_OK) return SCPE_ARG;
1199 sta = -1;
1200 break;
1201
1202 case I_V_FPN: /* FP15 no operand */
1203 val[1] = 0;
1204 sta = -1;
1205 break;
1206 } /* end case */
1207
1208 if (*cptr != 0) return SCPE_ARG; /* junk at end? */
1209 return sta;
1210 }
Magically enhanced SIMH