PDP8/pdp8_rf.c

   1 /* pdp8_rf.c: RF08 fixed head disk simulator
   2
   3    Copyright (c) 1993-2006, Robert M Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    rf           RF08 fixed head disk
  27
  28    15-May-06    RMS     Fixed bug in autosize attach (reported by Dave Gesswein)
  29    07-Jan-06    RMS     Fixed unaligned register access bug (found by Doug Carman)
  30    04-Jan-04    RMS     Changed sim_fsize calling sequence
  31    26-Oct-03    RMS     Cleaned up buffer copy code
  32    26-Jul-03    RMS     Fixed bug in set size routine
  33    14-Mar-03    RMS     Fixed variable platter interaction with save/restore
  34    03-Mar-03    RMS     Fixed autosizing
  35    02-Feb-03    RMS     Added variable platter and autosizing support
  36    04-Oct-02    RMS     Added DIB, device number support
  37    28-Nov-01    RMS     Added RL8A support
  38    25-Apr-01    RMS     Added device enable/disable support
  39    19-Mar-01    RMS     Added disk monitor bootstrap, fixed IOT decoding
  40    15-Feb-01    RMS     Fixed 3 cycle data break sequence
  41    14-Apr-99    RMS     Changed t_addr to unsigned
  42    30-Mar-98    RMS     Fixed bug in RF bootstrap
  43
  44    The RF08 is a head-per-track disk.  It uses the three cycle data break
  45    facility.  To minimize overhead, the entire RF08 is buffered in memory.
  46
  47    Two timing parameters are provided:
  48
  49    rf_time      Interword timing, must be non-zero
  50    rf_burst     Burst mode, if 0, DMA occurs cycle by cycle; otherwise,
  51                 DMA occurs in a burst
  52 */
  53
  54 #include "pdp8_defs.h"
  55 #include <math.h>
  56
  57 #define UNIT_V_AUTO     (UNIT_V_UF + 0)                 /* autosize */
  58 #define UNIT_V_PLAT     (UNIT_V_UF + 1)                 /* #platters - 1 */
  59 #define UNIT_M_PLAT     03
  60 #define UNIT_GETP(x)    ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)
  61 #define UNIT_AUTO       (1 << UNIT_V_AUTO)
  62 #define UNIT_PLAT       (UNIT_M_PLAT << UNIT_V_PLAT)
  63
  64 /* Constants */
  65
  66 #define RF_NUMWD        2048                            /* words/track */
  67 #define RF_NUMTR        128                             /* tracks/disk */
  68 #define RF_DKSIZE       (RF_NUMTR * RF_NUMWD)           /* words/disk */
  69 #define RF_NUMDK        4                               /* disks/controller */
  70 #define RF_WC           07750                           /* word count */
  71 #define RF_MA           07751                           /* mem address */
  72 #define RF_WMASK        (RF_NUMWD - 1)                  /* word mask */
  73
  74 /* Parameters in the unit descriptor */
  75
  76 #define FUNC            u4                              /* function */
  77 #define RF_READ         2                               /* read */
  78 #define RF_WRITE        4                               /* write */
  79
  80 /* Status register */
  81
  82 #define RFS_PCA         04000                           /* photocell status */
  83 #define RFS_DRE         02000                           /* data req enable */
  84 #define RFS_WLS         01000                           /* write lock status */
  85 #define RFS_EIE         00400                           /* error int enable */
  86 #define RFS_PIE         00200                           /* photocell int enb */
  87 #define RFS_CIE         00100                           /* done int enable */
  88 #define RFS_MEX         00070                           /* memory extension */
  89 #define RFS_DRL         00004                           /* data late error */
  90 #define RFS_NXD         00002                           /* non-existent disk */
  91 #define RFS_PER         00001                           /* parity error */
  92 #define RFS_ERR         (RFS_WLS + RFS_DRL + RFS_NXD + RFS_PER)
  93 #define RFS_V_MEX       3
  94
  95 #define GET_MEX(x)      (((x) & RFS_MEX) << (12 - RFS_V_MEX))
  96 #define GET_POS(x)      ((int) fmod (sim_gtime() / ((double) (x)), \
  97                         ((double) RF_NUMWD)))
  98 #define UPDATE_PCELL    if (GET_POS(rf_time) < 6) rf_sta = rf_sta | RFS_PCA; \
  99                         else rf_sta = rf_sta & ~RFS_PCA
 100 #define RF_INT_UPDATE   if ((rf_done && (rf_sta & RFS_CIE)) || \
 101                             ((rf_sta & RFS_ERR) && (rf_sta & RFS_EIE)) || \
 102                             ((rf_sta & RFS_PCA) && (rf_sta & RFS_PIE))) \
 103                             int_req = int_req | INT_RF; \
 104                         else int_req = int_req & ~INT_RF
 105
 106 extern uint16 M[];
 107 extern int32 int_req, stop_inst;
 108 extern UNIT cpu_unit;
 109
 110 int32 rf_sta = 0;                                       /* status register */
 111 int32 rf_da = 0;                                        /* disk address */
 112 int32 rf_done = 0;                                      /* done flag */
 113 int32 rf_wlk = 0;                                       /* write lock */
 114 int32 rf_time = 10;                                     /* inter-word time */
 115 int32 rf_burst = 1;                                     /* burst mode flag */
 116 int32 rf_stopioe = 1;                                   /* stop on error */
 117
 118 DEVICE rf_dev;
 119 int32 rf60 (int32 IR, int32 AC);
 120 int32 rf61 (int32 IR, int32 AC);
 121 int32 rf62 (int32 IR, int32 AC);
 122 int32 rf64 (int32 IR, int32 AC);
 123 t_stat rf_svc (UNIT *uptr);
 124 t_stat pcell_svc (UNIT *uptr);
 125 t_stat rf_reset (DEVICE *dptr);
 126 t_stat rf_boot (int32 unitno, DEVICE *dptr);
 127 t_stat rf_attach (UNIT *uptr, char *cptr);
 128 t_stat rf_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
 129
 130 /* RF08 data structures
 131
 132    rf_dev       RF device descriptor
 133    rf_unit      RF unit descriptor
 134    pcell_unit   photocell timing unit (orphan)
 135    rf_reg       RF register list
 136 */
 137
 138 DIB rf_dib = { DEV_RF, 5, { &rf60, &rf61, &rf62, NULL, &rf64 } };
 139
 140 UNIT rf_unit = {
 141     UDATA (&rf_svc, UNIT_FIX+UNIT_ATTABLE+
 142            UNIT_BUFABLE+UNIT_MUSTBUF, RF_DKSIZE)
 143     };
 144
 145 UNIT pcell_unit = { UDATA (&pcell_svc, 0, 0) };
 146
 147 REG rf_reg[] = {
 148     { ORDATA (STA, rf_sta, 12) },
 149     { ORDATA (DA, rf_da, 20) },
 150     { ORDATA (WC, M[RF_WC], 12), REG_FIT },
 151     { ORDATA (MA, M[RF_MA], 12), REG_FIT },
 152     { FLDATA (DONE, rf_done, 0) },
 153     { FLDATA (INT, int_req, INT_V_RF) },
 154     { ORDATA (WLK, rf_wlk, 32) },
 155     { DRDATA (TIME, rf_time, 24), REG_NZ + PV_LEFT },
 156     { FLDATA (BURST, rf_burst, 0) },
 157     { FLDATA (STOP_IOE, rf_stopioe, 0) },
 158     { DRDATA (CAPAC, rf_unit.capac, 21), REG_HRO },
 159     { ORDATA (DEVNUM, rf_dib.dev, 6), REG_HRO },
 160     { NULL }
 161     };
 162
 163 MTAB rf_mod[] = {
 164     { UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &rf_set_size },
 165     { UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &rf_set_size },
 166     { UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &rf_set_size },
 167     { UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &rf_set_size },
 168     { UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },
 169     { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
 170       &set_dev, &show_dev, NULL },
 171     { 0 }
 172     };
 173
 174 DEVICE rf_dev = {
 175     "RF", &rf_unit, rf_reg, rf_mod,
 176     1, 8, 20, 1, 8, 12,
 177     NULL, NULL, &rf_reset,
 178     &rf_boot, &rf_attach, NULL,
 179     &rf_dib, DEV_DISABLE | DEV_DIS
 180     };
 181
 182 /* IOT routines */
 183
 184 int32 rf60 (int32 IR, int32 AC)
 185 {
 186 int32 t;
 187 int32 pulse = IR & 07;
 188
 189 UPDATE_PCELL;                                           /* update photocell */
 190 if (pulse & 1) {                                        /* DCMA */
 191     rf_da = rf_da & ~07777;                             /* clear DAR<8:19> */
 192     rf_done = 0;                                        /* clear done */
 193     rf_sta = rf_sta & ~RFS_ERR;                         /* clear errors */
 194     RF_INT_UPDATE;                                      /* update int req */
 195     }
 196 if (pulse & 6) {                                        /* DMAR, DMAW */
 197     rf_da = rf_da | AC;                                 /* DAR<8:19> |= AC */
 198     rf_unit.FUNC = pulse & ~1;                          /* save function */
 199     t = (rf_da & RF_WMASK) - GET_POS (rf_time);         /* delta to new loc */
 200     if (t < 0) t = t + RF_NUMWD;                        /* wrap around? */
 201     sim_activate (&rf_unit, t * rf_time);               /* schedule op */
 202     AC = 0;                                             /* clear AC */
 203     }
 204 return AC;
 205 }
 206
 207 int32 rf61 (int32 IR, int32 AC)
 208 {
 209 int32 pulse = IR & 07;
 210
 211 UPDATE_PCELL;                                           /* update photocell */
 212 switch (pulse) {                                        /* decode IR<9:11> */
 213
 214     case 1:                                             /* DCIM */
 215         rf_sta = rf_sta & 07007;                        /* clear STA<3:8> */
 216         int_req = int_req & ~INT_RF;                    /* clear int req */
 217         sim_cancel (&pcell_unit);                       /* cancel photocell */
 218         return AC;
 219
 220     case 2:                                             /* DSAC */
 221         return ((rf_da & RF_WMASK) == GET_POS (rf_time))? IOT_SKP: 0;
 222
 223     case 5:                                             /* DIML */
 224         rf_sta = (rf_sta & 07007) | (AC & 0770);        /* STA<3:8> <- AC */
 225         if (rf_sta & RFS_PIE)                           /* photocell int? */
 226             sim_activate (&pcell_unit, (RF_NUMWD - GET_POS (rf_time)) *
 227                 rf_time);
 228         else sim_cancel (&pcell_unit);
 229         RF_INT_UPDATE;                                  /* update int req */
 230         return 0;                                       /* clear AC */
 231
 232     case 6:                                             /* DIMA */
 233         return rf_sta;                                  /* AC <- STA<0:11> */
 234         }
 235
 236 return AC;
 237 }
 238
 239 int32 rf62 (int32 IR, int32 AC)
 240 {
 241 int32 pulse = IR & 07;
 242
 243 UPDATE_PCELL;                                           /* update photocell */
 244 if (pulse & 1) {                                        /* DFSE */
 245     if (rf_sta & RFS_ERR) AC = AC | IOT_SKP;
 246     }
 247 if (pulse & 2) {                                        /* DFSC */
 248     if (pulse & 4) AC = AC & ~07777;                    /* for DMAC */
 249     else if (rf_done) AC = AC | IOT_SKP;
 250     }
 251 if (pulse & 4) AC = AC | (rf_da & 07777);               /* DMAC */
 252 return AC;
 253 }
 254
 255 int32 rf64 (int32 IR, int32 AC)
 256 {
 257 int32 pulse = IR & 07;
 258
 259 UPDATE_PCELL;                                           /* update photocell */
 260 switch (pulse) {                                        /* decode IR<9:11> */
 261
 262     case 1:                                             /* DCXA */
 263         rf_da = rf_da & 07777;                          /* clear DAR<0:7> */
 264         break;
 265
 266     case 3:                                             /* DXAL */
 267         rf_da = rf_da & 07777;                          /* clear DAR<0:7> */
 268     case 2:                                             /* DXAL w/o clear */
 269         rf_da = rf_da | ((AC & 0377) << 12);            /* DAR<0:7> |= AC */
 270         AC = 0;                                         /* clear AC */
 271         break;
 272
 273     case 5:                                             /* DXAC */
 274         AC = 0;                                         /* clear AC */
 275     case 4:                                             /* DXAC w/o clear */
 276         AC = AC | ((rf_da >> 12) & 0377);               /* AC |= DAR<0:7> */
 277         break;
 278
 279     default:
 280         AC = (stop_inst << IOT_V_REASON) + AC;
 281         break;
 282         }                                               /* end switch */
 283
 284 if ((uint32) rf_da >= rf_unit.capac) rf_sta = rf_sta | RFS_NXD;
 285 else rf_sta = rf_sta & ~RFS_NXD;
 286 RF_INT_UPDATE;
 287 return AC;
 288 }
 289
 290 /* Unit service
 291
 292    Note that for reads and writes, memory addresses wrap around in the
 293    current field.  This code assumes the entire disk is buffered.
 294 */
 295
 296 t_stat rf_svc (UNIT *uptr)
 297 {
 298 int32 pa, t, mex;
 299 int16 *fbuf = uptr->filebuf;
 300
 301 UPDATE_PCELL;                                           /* update photocell */
 302 if ((uptr->flags & UNIT_BUF) == 0) {                    /* not buf? abort */
 303     rf_sta = rf_sta | RFS_NXD;
 304     rf_done = 1;
 305     RF_INT_UPDATE;                                      /* update int req */
 306     return IORETURN (rf_stopioe, SCPE_UNATT);
 307     }
 308
 309 mex = GET_MEX (rf_sta);
 310 do {
 311     if ((uint32) rf_da >= rf_unit.capac) {              /* disk overflow? */
 312         rf_sta = rf_sta | RFS_NXD;
 313         break;
 314         }
 315     M[RF_WC] = (M[RF_WC] + 1) & 07777;                  /* incr word count */
 316     M[RF_MA] = (M[RF_MA] + 1) & 07777;                  /* incr mem addr */
 317     pa = mex | M[RF_MA];                                /* add extension */
 318     if (uptr->FUNC == RF_READ) {                        /* read? */
 319         if (MEM_ADDR_OK (pa))                           /* if !nxm */
 320             M[pa] = fbuf[rf_da];                        /* read word */
 321         }
 322     else {                                              /* write */
 323         t = ((rf_da >> 15) & 030) | ((rf_da >> 14) & 07);
 324         if ((rf_wlk >> t) & 1)                          /* write locked? */
 325             rf_sta = rf_sta | RFS_WLS;
 326         else {                                          /* not locked */
 327             fbuf[rf_da] = M[pa];                                                /* write word */
 328             if (((uint32) rf_da) >= uptr->hwmark) uptr->hwmark = rf_da + 1;
 329             }
 330         }
 331     rf_da = (rf_da + 1) & 03777777;                     /* incr disk addr */
 332     } while ((M[RF_WC] != 0) && (rf_burst != 0));       /* brk if wc, no brst */
 333
 334 if ((M[RF_WC] != 0) && ((rf_sta & RFS_ERR) == 0))       /* more to do? */
 335     sim_activate (&rf_unit, rf_time);                   /* sched next */
 336 else {
 337     rf_done = 1;                                        /* done */
 338     RF_INT_UPDATE;                                      /* update int req */
 339     }
 340 return SCPE_OK;
 341 }
 342
 343 /* Photocell unit service */
 344
 345 t_stat pcell_svc (UNIT *uptr)
 346 {
 347 rf_sta = rf_sta | RFS_PCA;                              /* set photocell */
 348 if (rf_sta & RFS_PIE) {                                 /* int enable? */
 349     sim_activate (&pcell_unit, RF_NUMWD * rf_time);
 350     int_req = int_req | INT_RF;
 351     }
 352 return SCPE_OK;
 353 }
 354
 355 /* Reset routine */
 356
 357 t_stat rf_reset (DEVICE *dptr)
 358 {
 359 rf_sta = rf_da = 0;
 360 rf_done = 1;
 361 int_req = int_req & ~INT_RF;                            /* clear interrupt */
 362 sim_cancel (&rf_unit);
 363 sim_cancel (&pcell_unit);
 364 return SCPE_OK;
 365 }
 366
 367 /* Bootstrap routine */
 368
 369 #define OS8_START       07750
 370 #define OS8_LEN         (sizeof (os8_rom) / sizeof (int16))
 371 #define DM4_START       00200
 372 #define DM4_LEN         (sizeof (dm4_rom) / sizeof (int16))
 373
 374 static const uint16 os8_rom[] = {
 375     07600,                      /* 7750, CLA CLL        ; also word count */
 376     06603,                      /* 7751, DMAR           ; also address */
 377     06622,                      /* 7752, DFSC           ; done? */
 378     05352,                      /* 7753, JMP .-1        ; no */
 379     05752                       /* 7754, JMP @.-2       ; enter boot */
 380     };
 381
 382 static const uint16 dm4_rom[] = {
 383     00200, 07600,               /* 0200, CLA CLL */
 384     00201, 06603,               /* 0201, DMAR           ; read */
 385     00202, 06622,               /* 0202, DFSC           ; done? */
 386     00203, 05202,               /* 0203, JMP .-1        ; no */
 387     00204, 05600,               /* 0204, JMP @.-4       ; enter boot */
 388     07750, 07576,               /* 7750, 7576           ; word count */
 389     07751, 07576                /* 7751, 7576           ; address */
 390     };
 391
 392 t_stat rf_boot (int32 unitno, DEVICE *dptr)
 393 {
 394 int32 i;
 395 extern int32 sim_switches, saved_PC;
 396
 397 if (rf_dib.dev != DEV_RF) return STOP_NOTSTD;           /* only std devno */
 398 if (sim_switches & SWMASK ('D')) {
 399     for (i = 0; i < DM4_LEN; i = i + 2)
 400         M[dm4_rom[i]] = dm4_rom[i + 1];
 401     saved_PC = DM4_START;
 402     }
 403 else {
 404     for (i = 0; i < OS8_LEN; i++)
 405         M[OS8_START + i] = os8_rom[i];
 406     saved_PC = OS8_START;
 407     }
 408 return SCPE_OK;
 409 }
 410
 411 /* Attach routine */
 412
 413 t_stat rf_attach (UNIT *uptr, char *cptr)
 414 {
 415 uint32 sz, p;
 416 uint32 ds_bytes = RF_DKSIZE * sizeof (int16);
 417
 418 if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {
 419     p = (sz + ds_bytes - 1) / ds_bytes;
 420     if (p >= RF_NUMDK) p = RF_NUMDK - 1;
 421     uptr->flags = (uptr->flags & ~UNIT_PLAT) |
 422         (p << UNIT_V_PLAT);
 423     }
 424 uptr->capac = UNIT_GETP (uptr->flags) * RF_DKSIZE;
 425 return attach_unit (uptr, cptr);
 426 }
 427
 428 /* Change disk size */
 429
 430 t_stat rf_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
 431 {
 432 if (val < 0) return SCPE_IERR;
 433 if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
 434 uptr->capac = UNIT_GETP (val) * RF_DKSIZE;
 435 uptr->flags = uptr->flags & ~UNIT_AUTO;
 436 return SCPE_OK;
 437 }