SDS/sds_defs.h

   1 /* sds_defs.h: SDS 940 simulator definitions
   2
   3    Copyright (c) 2001-2005, Robert M. Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    25-Apr-03    RMS     Revised for extended file support
  27 */
  28
  29 #ifndef _SDS_DEFS_H_
  30 #define _SDS_DEFS_H_    0
  31
  32 #include "sim_defs.h"                                   /* simulator defns */
  33
  34 /* Simulator stop codes */
  35
  36 #define STOP_IONRDY     1                               /* I/O dev not ready */
  37 #define STOP_HALT       2                               /* HALT */
  38 #define STOP_IBKPT      3                               /* breakpoint */
  39 #define STOP_INVDEV     4                               /* invalid dev */
  40 #define STOP_INVINS     5                               /* invalid instr */
  41 #define STOP_INVIOP     6                               /* invalid I/O op */
  42 #define STOP_INDLIM     7                               /* indirect limit */
  43 #define STOP_EXULIM     8                               /* EXU limit */
  44 #define STOP_MMINT      9                               /* mm in intr */
  45 #define STOP_MMTRP      10                              /* mm in trap */
  46 #define STOP_TRPINS     11                              /* trap inst not BRM */
  47 #define STOP_RTCINS     12                              /* rtc inst not MIN/SKR */
  48 #define STOP_ILLVEC     13                              /* zero vector */
  49 #define STOP_CCT        14                              /* runaway CCT */
  50
  51 /* Trap codes */
  52
  53 #define MM_PRVINS       -040                            /* privileged */
  54 #define MM_NOACC        -041                            /* no access */
  55 #define MM_WRITE        -043                            /* write protect */
  56 #define MM_MONUSR       -044                            /* mon to user */
  57
  58 /* Conditional error returns */
  59
  60 #define CRETINS         return ((stop_invins)? STOP_INVINS: SCPE_OK)
  61 #define CRETDEV         return ((stop_invdev)? STOP_INVDEV: SCPE_OK)
  62 #define CRETIOP         return ((stop_inviop)? STOP_INVIOP: SCPE_OK)
  63 #define CRETIOE(f,c)    return ((f)? c: SCPE_OK)
  64
  65 /* Architectural constants */
  66
  67 #define SIGN            040000000                       /* sign */
  68 #define DMASK           077777777                       /* data mask */
  69 #define EXPS            0400                            /* exp sign */
  70 #define EXPMASK         0777                            /* exp mask */
  71 #define SXT(x)          ((int32) (((x) & SIGN)? ((x) | ~DMASK): \
  72                         ((x) & DMASK)))
  73 #define SXT_EXP(x)      ((int32) (((x) & EXPS)? ((x) | ~EXPMASK): \
  74                         ((x) & EXPMASK)))
  75
  76 /* Memory */
  77
  78 #define MAXMEMSIZE      (1 << 16)                       /* max memory size */
  79 #define PAMASK          (MAXMEMSIZE - 1)                /* physical addr mask */
  80 #define MEMSIZE         (cpu_unit.capac)                /* actual memory size */
  81 #define MEM_ADDR_OK(x)  (((uint32) (x)) < MEMSIZE)
  82 #define ReadP(x)        M[x]
  83 #define WriteP(x,y)     if (MEM_ADDR_OK (x)) M[x] = y
  84
  85 /* Virtual addressing */
  86
  87 #define VA_SIZE         (1 << 14)                       /* virtual addr size */
  88 #define VA_MASK         (VA_SIZE - 1)                   /* virtual addr mask */
  89 #define VA_V_PN         11                              /* page number */
  90 #define VA_M_PN         07
  91 #define VA_GETPN(x)     (((x) >> VA_V_PN) & VA_M_PN)
  92 #define VA_POFF         ((1 << VA_V_PN) - 1)            /* offset */
  93 #define VA_USR          (I_USR)                         /* user flag in addr */
  94 #define XVA_MASK        (VA_USR | VA_MASK)
  95
  96 /* Arithmetic */
  97
  98 #define TSTS(x)         ((x) & SIGN)
  99 #define NEG(x)          (-((int32) (x)) & DMASK)
 100 #define ABS(x)          (TSTS (x)? NEG(x): (x))
 101
 102 /* Memory map */
 103
 104 #define MAP_PROT        (040 << VA_V_PN)                /* protected */
 105 #define MAP_PAGE        (037 << VA_V_PN)                /* phys page number */
 106
 107 /* Instruction format */
 108
 109 #define I_USR           (1 << 23)                       /* user */
 110 #define I_IDX           (1 << 22)                       /* indexed */
 111 #define I_POP           (1 << 21)                       /* programmed op */
 112 #define I_V_TAG         21                              /* tag */
 113 #define I_V_OP          15                              /* opcode */
 114 #define I_M_OP          077
 115 #define I_GETOP(x)      (((x) >> I_V_OP) & I_M_OP)
 116 #define I_IND           (1 << 14)                       /* indirect */
 117 #define I_V_SHFOP       11                              /* shift op */
 118 #define I_M_SHFOP       07
 119 #define I_GETSHFOP(x)   (((x) >> I_V_SHFOP) & I_M_SHFOP)
 120 #define I_SHFMSK        0777                            /* shift count */
 121 #define I_V_IOMD        12                              /* IO inst mode */
 122 #define I_M_IOMD        03
 123 #define I_GETIOMD(x)    (((x) >> I_V_IOMD) & I_M_IOMD)
 124 #define I_V_SKCND       7                               /* SKS skip cond */
 125 #define I_M_SKCND       037
 126 #define I_GETSKCND(x)   (((x) >> I_V_SKCND) & I_M_SKCND)
 127 #define I_EOB2          000400000                       /* chan# bit 2 */
 128 #define I_SKB2          000040000                       /* skschan# bit 2 */
 129 #define I_EOB1          020000000                       /* chan# bit 1 */
 130 #define I_EOB0          000000100                       /* chan# bit 0 */
 131 #define I_GETEOCH(x)    ((((x) & I_EOB2)? 4: 0) | \
 132                         (((x) & I_EOB1)? 2: 0) | \
 133                         (((x) & I_EOB0)? 1: 0))
 134 #define I_SETEOCH(x)    ((((x) & 4)? I_EOB2: 0) | \
 135                         (((x) & 2)? I_EOB1: 0) | \
 136                         (((x) & 1)? I_EOB0: 0))
 137 #define I_GETSKCH(x)    ((((x) & I_SKB2)? 4: 0) | \
 138                         (((x) & I_EOB1)? 2: 0) | \
 139                         (((x) & I_EOB0)? 1: 0))
 140 #define I_SETSKCH(x)    ((((x) & 4)? I_SKB2: 0) | \
 141                         (((x) & 2)? I_EOB1: 0) | \
 142                         (((x) & 1)? I_EOB0: 0))
 143
 144 /* Globally visible flags */
 145
 146 #define UNIT_V_GENIE    (UNIT_V_UF + 0)
 147 #define UNIT_GENIE      (1 << UNIT_V_GENIE)
 148
 149 /* Timers */
 150
 151 #define TMR_RTC         0                               /* clock */
 152 #define TMR_MUX         1                               /* mux */
 153
 154 /* I/O routine functions */
 155
 156 #define IO_CONN         0                               /* connect */
 157 #define IO_EOM1         1                               /* EOM mode 1 */
 158 #define IO_DISC         2                               /* disconnect */
 159 #define IO_READ         3                               /* read */
 160 #define IO_WRITE        4                               /* write */
 161 #define IO_WREOR        5                               /* write eor */
 162 #define IO_SKS          6                               /* skip signal */
 163
 164 /* Dispatch template */
 165
 166 struct sdsdspt {
 167     uint32      num;                                    /* # entries */
 168     uint32      off;                                    /* offset from base */
 169     };
 170
 171 typedef struct sdsdspt DSPT;
 172
 173 /* Device information block */
 174
 175 struct sdsdib {
 176     int32       chan;                                   /* channel */
 177     int32       dev;                                    /* base dev no */
 178     int32       xfr;                                    /* xfer flag */
 179     DSPT        *tplt;                                  /* dispatch templates */
 180     t_stat      (*iop) (uint32 fnc, uint32 dev, uint32 *dat);
 181     };
 182
 183 typedef struct sdsdib DIB;
 184
 185 /* Channels */
 186
 187 #define NUM_CHAN        8                               /* max num chan */
 188 #define CHAN_W          0                               /* TMCC */
 189 #define CHAN_Y          1
 190 #define CHAN_C          2
 191 #define CHAN_D          3
 192 #define CHAN_E          4                               /* DACC */
 193 #define CHAN_F          5
 194 #define CHAN_G          6
 195 #define CHAN_H          7
 196
 197 /* I/O control EOM */
 198
 199 #define CHC_REV         04000                           /* reverse */
 200 #define CHC_NLDR        02000                           /* no leader */
 201 #define CHC_BIN         01000                           /* binary */
 202 #define CHC_V_CPW       7                               /* char/word */
 203 #define CHC_M_CPW       03
 204 #define CHC_GETCPW(x)   (((x) >> CHC_V_CPW) & CHC_M_CPW)
 205
 206 /* Buffer control (extended) EOM */
 207
 208 #define CHM_CE          04000                           /* compat/ext */
 209 #define CHM_ER          02000                           /* end rec int */
 210 #define CHM_ZC          01000                           /* zero wc int */
 211 #define CHM_V_FNC       7                               /* term func */
 212 #define CHM_M_FNC       03
 213 #define CHM_GETFNC(x)   (((x) & CHM_CE)? (((x) >> CHM_V_FNC) & CHM_M_FNC): CHM_COMP)
 214 #define  CHM_IORD       0                               /* record, disc */
 215 #define  CHM_IOSD       1                               /* signal, disc */
 216 #define  CHM_IORP       2                               /* record, proc */
 217 #define  CHM_IOSP       3                               /* signal, proc */
 218 #define  CHM_COMP       5                               /* compatible */
 219 #define  CHM_SGNL       1                               /* signal bit */
 220 #define  CHM_PROC       2                               /* proceed bit */
 221 #define CHM_V_HMA       5                               /* hi mem addr */
 222 #define CHM_M_HMA       03
 223 #define CHM_GETHMA(x)   (((x) >> CHM_V_HMA) & CHM_M_HMA)
 224 #define CHM_V_HWC       0                               /* hi word count */
 225 #define CHM_M_HWC       037
 226 #define CHM_GETHWC(x)   (((x) >> CHM_V_HWC) & CHM_M_HWC)
 227
 228 /* Channel flags word */
 229
 230 #define CHF_ERR         00001                           /* error */
 231 #define CHF_IREC        00002                           /* interrecord */
 232 #define CHF_ILCE        00004                           /* interlace */
 233 #define CHF_DCHN        00010                           /* data chain */
 234 #define CHF_EOR         00020                           /* end of record */
 235 #define CHF_12B         00040                           /* 12 bit mode */
 236 #define CHF_24B         00100                           /* 24 bit mode */
 237 #define CHF_OWAK        00200                           /* output wake */
 238 #define CHF_SCAN        00400                           /* scan */
 239 #define CHF_TOP         01000                           /* TOP pending */
 240 #define CHF_N_FLG       9                               /* <= 16 */
 241
 242 /* Interrupts and vectors (0 is reserved), highest bit is highest priority */
 243
 244 #define INT_V_PWRO      31                              /* power on */
 245 #define INT_V_PWRF      30                              /* power off */
 246 #define INT_V_CPAR      29                              /* CPU parity err */
 247 #define INT_V_IPAR      28                              /* IO parity err */
 248 #define INT_V_RTCS      27                              /* clock sync */
 249 #define INT_V_RTCP      26                              /* clock pulse */
 250 #define INT_V_YZWC      25                              /* chan Y zero wc */
 251 #define INT_V_WZWC      24                              /* chan W zero wc */
 252 #define INT_V_YEOR      23                              /* chan Y end rec */
 253 #define INT_V_WEOR      22                              /* chan W end rec */
 254 #define INT_V_CZWC      21                              /* chan C */
 255 #define INT_V_CEOR      20
 256 #define INT_V_DZWC      19                              /* chan D */
 257 #define INT_V_DEOR      18
 258 #define INT_V_EZWC      17                              /* chan E */
 259 #define INT_V_EEOR      16
 260 #define INT_V_FZWC      15                              /* chan F */
 261 #define INT_V_FEOR      14
 262 #define INT_V_GZWC      13                              /* chan G */
 263 #define INT_V_GEOR      12
 264 #define INT_V_HZWC      11                              /* chan H */
 265 #define INT_V_HEOR      10
 266 #define INT_V_MUXR      9                               /* mux receive */
 267 #define INT_V_MUXT      8                               /* mux transmit */
 268 #define INT_V_MUXCO     7                               /* SDS carrier on */
 269 #define INT_V_MUXCF     6                               /* SDS carrier off */
 270 #define INT_V_DRM       5                               /* Genie drum */
 271 #define INT_V_FORK      4                               /* fork */
 272
 273 #define INT_PWRO        (1 << INT_V_PWRO)
 274 #define INT_PWRF        (1 << INT_V_PWRF)
 275 #define INT_CPAR        (1 << INT_V_CPAR)
 276 #define INT_IPAR        (1 << INT_V_IPAR)
 277 #define INT_RTCS        (1 << INT_V_RTCS)
 278 #define INT_RTCP        (1 << INT_V_RTCP)
 279 #define INT_YZWC        (1 << INT_V_YZWC)
 280 #define INT_WZWC        (1 << INT_V_WZWC)
 281 #define INT_YEOR        (1 << INT_V_YEOR)
 282 #define INT_WEOR        (1 << INT_V_WEOR)
 283 #define INT_CZWC        (1 << INT_V_CZWC)
 284 #define INT_CEOR        (1 << INT_V_CEOR)
 285 #define INT_DZWC        (1 << INT_V_DZWC)
 286 #define INT_DEOR        (1 << INT_V_DEOR)
 287 #define INT_EZWC        (1 << INT_V_EZWC)
 288 #define INT_EEOR        (1 << INT_V_EEOR)
 289 #define INT_FZWC        (1 << INT_V_FZWC)
 290 #define INT_FEOR        (1 << INT_V_FEOR)
 291 #define INT_GZWC        (1 << INT_V_GZWC)
 292 #define INT_GEOR        (1 << INT_V_GEOR)
 293 #define INT_HZWC        (1 << INT_V_HZWC)
 294 #define INT_HEOR        (1 << INT_V_HEOR)
 295 #define INT_MUXR        (1 << INT_V_MUXR)
 296 #define INT_MUXT        (1 << INT_V_MUXT)
 297 #define INT_MUXCO       (1 << INT_V_MUXCO)
 298 #define INT_MUXCF       (1 << INT_V_MUXCF)
 299 #define INT_DRM         (1 << INT_V_DRM)
 300 #define INT_FORK        (1 << INT_V_FORK)
 301
 302 #define VEC_PWRO        0036
 303 #define VEC_PWRF        0037
 304 #define VEC_CPAR        0056
 305 #define VEC_IPAR        0057
 306 #define VEC_RTCS        0074
 307 #define VEC_RTCP        0075
 308 #define VEC_YZWC        0030
 309 #define VEC_WZWC        0031
 310 #define VEC_YEOR        0032
 311 #define VEC_WEOR        0033
 312 #define VEC_CZWC        0060
 313 #define VEC_CEOR        0061
 314 #define VEC_DZWC        0062
 315 #define VEC_DEOR        0063
 316 #define VEC_EZWC        0064
 317 #define VEC_EEOR        0065
 318 #define VEC_FZWC        0066
 319 #define VEC_FEOR        0067
 320 #define VEC_GZWC        0070
 321 #define VEC_GEOR        0071
 322 #define VEC_HZWC        0072
 323 #define VEC_HEOR        0073
 324 #define VEC_MUXR        0200                            /* term mux rcv */
 325 #define VEC_MUXT        0201                            /* term mux xmt */
 326 #define VEC_MUXCO       0202                            /* SDS: mux carrier on */
 327 #define VEC_MUXCF       0203                            /* SDS: mux carrier off */
 328 #define VEC_DRM         0202                            /* Genie: drum */
 329 #define VEC_FORK        0216                            /* "fork" */
 330
 331 /* Device constants */
 332
 333 #define DEV_MASK        077                             /* device mask */
 334 #define DEV_TTI         001                             /* teletype */
 335 #define DEV_PTR         004                             /* paper tape rdr */
 336 #define DEV_MT          010                             /* magtape */
 337 #define DEV_RAD         026                             /* fixed head disk */
 338 #define DEV_DSK         026                             /* moving head disk */
 339 #define DEV_TTO         041                             /* teletype */
 340 #define DEV_PTP         044                             /* paper tape punch */
 341 #define DEV_LPT         060                             /* line printer */
 342 #define DEV_MTS         020                             /* MT scan/erase */
 343 #define DEV_OUT         040                             /* output flag */
 344 #define DEV3_GDRM       004                             /* Genie drum */
 345 #define DEV3_GMUX       001                             /* Genie mux */
 346 #define DEV3_SMUX       (DEV_MASK)                      /* standard mux */
 347
 348 #define LPT_WIDTH       132                             /* line print width */
 349 #define CCT_LNT         132                             /* car ctrl length */
 350
 351 /* Transfer request flags for devices (0 is reserved) */
 352
 353 #define XFR_V_TTI       1                               /* console */
 354 #define XFR_V_TTO       2
 355 #define XFR_V_PTR       3                               /* paper tape */
 356 #define XFR_V_PTP       4
 357 #define XFR_V_LPT       5                               /* line printer */
 358 #define XFR_V_RAD       6                               /* fixed hd disk */
 359 #define XFR_V_DSK       7                               /* mving hd disk */
 360 #define XFR_V_MT0       8                               /* magtape */
 361
 362 #define XFR_TTI         (1 << XFR_V_TTI)
 363 #define XFR_TTO         (1 << XFR_V_TTO)
 364 #define XFR_PTR         (1 << XFR_V_PTR)
 365 #define XFR_PTP         (1 << XFR_V_PTP)
 366 #define XFR_LPT         (1 << XFR_V_LPT)
 367 #define XFR_RAD         (1 << XFR_V_RAD)
 368 #define XFR_DSK         (1 << XFR_V_DSK)
 369 #define XFR_MT0         (1 << XFR_V_MT0)
 370
 371 /* PIN/POT ordinals (0 is reserved) */
 372
 373 #define POT_ILCY        1                               /* interlace */
 374 #define POT_DCRY        (POT_ILCY + NUM_CHAN)           /* data chain */
 375 #define POT_ADRY        (POT_DCRY + NUM_CHAN)           /* address reg */
 376 #define POT_RL1         (POT_ADRY + NUM_CHAN)           /* RL1 */
 377 #define POT_RL2         (POT_RL1 + 1)                   /* RL2 */
 378 #define POT_RL4         (POT_RL2 + 1)                   /* RL4 */
 379 #define POT_RADS        (POT_RL4 + 1)                   /* fhd sector */
 380 #define POT_RADA        (POT_RADS + 1)                  /* fhd addr */
 381 #define POT_DSK         (POT_RADA + 1)                  /* mhd sec/addr */
 382 #define POT_SYSI        (POT_DSK + 1)                   /* sys intr */
 383 #define POT_MUX         (POT_SYSI + 1)                  /* multiplexor */
 384
 385 /* Opcodes */
 386
 387 enum opcodes {
 388     HLT, BRU, EOM, EOD = 006,
 389     MIY = 010, BRI, MIW, POT, ETR, MRG = 016, EOR,
 390     NOP, OVF = 022, EXU,
 391     YIM = 030, WIM = 032, PIN, STA = 035, STB, STX,
 392     SKS, BRX, BRM = 043, RCH = 046,
 393     SKE = 050, BRR, SKB, SKN, SUB, ADD, SUC, ADC,
 394     SKR, MIN, XMA, ADM, MUL, DIV, RSH, LSH,
 395     SKM, LDX, SKA, SKG, SKD, LDB, LDA, EAX
 396     };
 397
 398 /* Channel function prototypes */
 399
 400 void chan_set_flag (int32 ch, uint32 fl);
 401 void chan_set_ordy (int32 ch);
 402 void chan_disc (int32 ch);
 403 void chan_set_uar (int32 ch, uint32 dev);
 404 t_stat set_chan (UNIT *uptr, int32 val, char *cptr, void *desc);
 405 t_stat show_chan (FILE *st, UNIT *uptr, int32 val, void *desc);
 406 t_stat chan_process (void);
 407 t_bool chan_testact (void);
 408
 409 #endif