First Commit of my working state
[simh.git] / SDS / sds_mux.c
1 /* sds_mux.c: SDS 940 terminal multiplexor simulator
2
3 Copyright (c) 2001-2006, Robert M Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 mux terminal multiplexor
27
28 29-Dec-06 RMS Revised to use console conversion routines
29 29-Jun-05 RMS Added SET MUXLn DISCONNECT
30 21-Jun-05 RMS Fixed bug in SHOW CONN/STATS
31 05-Jan-04 RMS Revised for tmxr library changes
32 09-May-03 RMS Added network device flag
33
34 This module implements up to 32 individual serial interfaces, representing
35 either the project Genie terminal multiplexor or the SDS 940 CTE option.
36 */
37
38 #include "sds_defs.h"
39 #include "sim_sock.h"
40 #include "sim_tmxr.h"
41 #include <ctype.h>
42
43 #define PROJ_GENIE (cpu_unit.flags & UNIT_GENIE)
44 #define MUX_NUMLIN mux_desc.lines
45
46 #define MUX_LINES 32 /* lines */
47 #define MUX_FLAGS 4 /* intr per line */
48 #define MUX_FLAGMASK (MUX_FLAGS - 1)
49 #define MUX_SCANMAX (MUX_LINES * MUX_FLAGS) /* flags to scan */
50 #define MUX_SCANMASK (MUX_SCANMAX - 1)
51 #define MUX_INIT_POLL 8000
52 #define MUXL_WAIT 500
53 #define MUX_SETFLG(l,x) mux_flags[((l) * MUX_FLAGS) + (x)] = 1
54 #define MUX_SETINT(x) int_req = int_req | (INT_MUXR >> (x))
55 #define MUX_CLRINT(x) int_req = int_req & ~(INT_MUXR >> (x))
56
57 /* PIN/POT */
58
59 #define P_V_CHAR 16 /* char */
60 #define P_M_CHAR 0377
61 #define P_CHAR(x) (((x) >> P_V_CHAR) & P_M_CHAR)
62 #define PIN_OVR 000100000 /* overrun */
63 #define POT_NOX 000100000 /* no xmit */
64 #define POT_XMI 000040000 /* xmit int */
65 #define POT_GLNE 000020000 /* Genie: enable */
66 #define POT_SCDT 000020000 /* 940: clr DTR */
67 #define P_V_CHAN 0 /* channel */
68 #define P_M_CHAN (MUX_LINES - 1)
69 #define P_CHAN(x) (((x) >> P_V_CHAN) & P_M_CHAN)
70
71 /* SKS 940 */
72
73 #define SKS_XBE 000001000 /* xmt buf empty */
74 #define SKS_CRO 000000400 /* carrier on */
75 #define SKS_DSR 000000200 /* data set ready */
76 #define SKS_CHAN(x) P_CHAN(x)
77
78 /* SKS Genie */
79
80 #define SKG_V_CHAN 7
81 #define SKG_M_CHAN (MUX_LINES - 1)
82 #define SKG_CHAN(x) (((x) >> SKG_V_CHAN) & SKG_M_CHAN)
83
84 /* Flags */
85
86 #define MUX_FRCV 0 /* receive */
87 #define MUX_FXMT 1 /* transmit */
88 #define MUX_FCRN 2 /* carrier on */
89 #define MUX_FCRF 3 /* carrier off */
90
91 /* Line status */
92
93 #define MUX_SCHP 001 /* char pending */
94 #define MUX_SOVR 002 /* overrun */
95 #define MUX_SLNE 004 /* line enabled */
96 #define MUX_SXIE 010 /* xmt int enab */
97 #define MUX_SCRO 020 /* carrier on */
98 #define MUX_SDSR 040 /* data set ready */
99
100 /* Data */
101
102 extern uint32 alert, int_req;
103 extern int32 stop_invins, stop_invdev, stop_inviop;
104 extern UNIT cpu_unit;
105
106 uint8 mux_rbuf[MUX_LINES]; /* rcv buf */
107 uint8 mux_xbuf[MUX_LINES]; /* xmt buf */
108 uint8 mux_sta[MUX_LINES]; /* status */
109 uint8 mux_flags[MUX_SCANMAX]; /* flags */
110 uint32 mux_tps = 100; /* polls/second */
111 uint32 mux_scan = 0; /* scanner */
112 uint32 mux_slck = 0; /* scanner locked */
113
114 TMLN mux_ldsc[MUX_LINES] = { 0 }; /* line descriptors */
115 TMXR mux_desc = { MUX_LINES, 0, 0, mux_ldsc }; /* mux descriptor */
116
117 t_stat mux (uint32 fnc, uint32 inst, uint32 *dat);
118 t_stat muxi_svc (UNIT *uptr);
119 t_stat muxo_svc (UNIT *uptr);
120 t_stat mux_reset (DEVICE *dptr);
121 t_stat mux_attach (UNIT *uptr, char *cptr);
122 t_stat mux_detach (UNIT *uptr);
123 t_stat mux_summ (FILE *st, UNIT *uptr, int32 val, void *desc);
124 t_stat mux_show (FILE *st, UNIT *uptr, int32 val, void *desc);
125 t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc);
126 void mux_reset_ln (int32 ln);
127 void mux_scan_next (void);
128
129 /* MUX data structures
130
131 mux_dev MUX device descriptor
132 mux_unit MUX unit descriptor
133 mux_reg MUX register list
134 mux_mod MUX modifiers list
135 */
136
137 DIB mux_dib = { -1, DEV3_GMUX, 0, NULL, &mux };
138
139 REG mux_nlreg = { DRDATA (NLINES, MUX_NUMLIN, 6), PV_LEFT };
140
141 UNIT mux_unit = { UDATA (&muxi_svc, UNIT_ATTABLE, 0), MUX_INIT_POLL };
142
143 REG mux_reg[] = {
144 { BRDATA (STA, mux_sta, 8, 6, MUX_LINES) },
145 { BRDATA (RBUF, mux_rbuf, 8, 8, MUX_LINES) },
146 { BRDATA (XBUF, mux_xbuf, 8, 8, MUX_LINES) },
147 { BRDATA (INT, mux_flags, 8, 1, MUX_SCANMAX) },
148 { ORDATA (SCAN, mux_scan, 7) },
149 { FLDATA (SLCK, mux_slck, 0) },
150 { DRDATA (TPS, mux_tps, 8), REG_NZ + PV_LEFT },
151 { NULL }
152 };
153
154 MTAB mux_mod[] = {
155 { MTAB_XTD | MTAB_VDV | MTAB_VAL, 0, "lines", "LINES",
156 &mux_vlines, NULL, &mux_nlreg },
157 { MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
158 &tmxr_dscln, NULL, &mux_desc },
159 { UNIT_ATT, UNIT_ATT, "connections", NULL, NULL, &mux_summ },
160 { MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
161 NULL, &mux_show, NULL },
162 { MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
163 NULL, &mux_show, NULL },
164 { 0 }
165 };
166
167 DEVICE mux_dev = {
168 "MUX", &mux_unit, mux_reg, mux_mod,
169 1, 10, 31, 1, 8, 8,
170 &tmxr_ex, &tmxr_dep, &mux_reset,
171 NULL, &mux_attach, &mux_detach,
172 &mux_dib, DEV_NET | DEV_DISABLE
173 };
174
175 /* MUXL data structures
176
177 muxl_dev MUXL device descriptor
178 muxl_unit MUXL unit descriptor
179 muxl_reg MUXL register list
180 muxl_mod MUXL modifiers list
181 */
182
183 UNIT muxl_unit[] = {
184 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
185 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
186 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
187 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
188 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
189 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
190 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
191 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
192 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
193 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
194 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
195 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
196 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
197 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
198 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
199 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
200 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
201 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
202 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
203 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
204 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
205 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
206 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
207 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
208 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
209 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
210 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
211 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
212 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
213 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
214 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT },
215 { UDATA (&muxo_svc, TT_MODE_UC, 0), MUXL_WAIT }
216 };
217
218 MTAB muxl_mod[] = {
219 { TT_MODE, TT_MODE_UC, "UC", "UC", NULL },
220 { TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
221 { TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
222 { TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
223 { MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",
224 &tmxr_dscln, NULL, &mux_desc },
225 { MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
226 &tmxr_set_log, &tmxr_show_log, &mux_desc },
227 { MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
228 &tmxr_set_nolog, NULL, &mux_desc },
229 { 0 }
230 };
231
232 REG muxl_reg[] = {
233 { URDATA (TIME, muxl_unit[0].wait, 10, 24, 0,
234 MUX_LINES, REG_NZ + PV_LEFT) },
235 { NULL }
236 };
237
238 DEVICE muxl_dev = {
239 "MUXL", muxl_unit, muxl_reg, muxl_mod,
240 MUX_LINES, 10, 31, 1, 8, 8,
241 NULL, NULL, &mux_reset,
242 NULL, NULL, NULL,
243 NULL, 0
244 };
245
246 /* MUX: IO routine */
247
248 /* Mux routine - EOM 30001 or EOM 77777,2 */
249
250 t_stat mux (uint32 fnc, uint32 inst, uint32 *dat)
251 {
252 uint32 ln;
253
254 switch (fnc) {
255
256 case IO_CONN: /* connect */
257 if ((PROJ_GENIE && (inst == 000230001)) || /* set alert */
258 (!PROJ_GENIE && (inst == 020277777))) alert = POT_MUX;
259 else CRETINS;
260 break;
261
262 case IO_SKS: /* skip */
263 if (PROJ_GENIE && ((inst & 077770077) == 004030001)) {
264 ln = SKG_CHAN (inst); /* get line */
265 if (!sim_is_active (&muxl_unit[ln])) *dat = 1;
266 }
267 else if (!PROJ_GENIE && ((inst & 077776000) == 024076000)) {
268 ln = SKS_CHAN (inst); /* get line */
269 if (inst & (SKS_XBE|SKS_CRO|SKS_DSR)) *dat = 1;
270 if (((inst & SKS_XBE) && sim_is_active (&muxl_unit[ln])) ||
271 ((inst & SKS_CRO) && !(mux_sta[ln] & MUX_SCRO)) ||
272 ((inst & SKS_DSR) && !(mux_sta[ln] & MUX_SDSR)))
273 *dat = 0; /* no skip if fail */
274 }
275 else CRETINS;
276
277 default:
278 return SCPE_IERR;
279 } /* end case */
280
281 return SCPE_OK;
282 }
283
284 /* PIN routine */
285
286 t_stat pin_mux (uint32 num, uint32 *dat)
287 {
288 uint32 ln = mux_scan >> 2;
289 uint32 flag = mux_scan & MUX_FLAGMASK;
290
291 mux_scan = mux_scan & MUX_SCANMASK; /* mask scan */
292 mux_flags[mux_scan] = 0; /* clear flag */
293 if (flag == MUX_FRCV) { /* rcv event? */
294 *dat = ln | ((uint32) mux_rbuf[ln] << P_V_CHAR) | /* line + char + */
295 ((mux_sta[ln] & MUX_SOVR)? PIN_OVR: 0); /* overrun */
296 mux_sta[ln] = mux_sta[ln] & ~(MUX_SCHP | MUX_SOVR);
297 }
298 else *dat = ln; /* just line */
299 mux_slck = 0; /* unlock scanner */
300 mux_scan_next (); /* kick scanner */
301 return SCPE_OK;
302 }
303
304 t_stat pot_mux (uint32 num, uint32 *dat)
305 {
306 uint32 ln = P_CHAN (*dat);
307 uint32 chr = P_CHAR (*dat);
308
309 if (PROJ_GENIE && ((*dat & POT_GLNE) == 0)) { /* Genie disable? */
310 mux_sta[ln] = mux_sta[ln] & ~MUX_SLNE; /* clear status */
311 mux_ldsc[ln].rcve = 0;
312 }
313 else if (!PROJ_GENIE && (*dat & POT_SCDT)) { /* SDS disable? */
314 if (mux_ldsc[ln].conn) { /* connected? */
315 tmxr_linemsg (&mux_ldsc[ln], "\r\nLine hangup\r\n");
316 tmxr_reset_ln (&mux_ldsc[ln]); /* reset line */
317 mux_reset_ln (ln); /* reset state */
318 MUX_SETFLG (ln, MUX_FCRF); /* set carrier off */
319 mux_scan_next (); /* kick scanner */
320 }
321 mux_sta[ln] = mux_sta[ln] & ~MUX_SLNE; /* clear status */
322 mux_ldsc[ln].rcve = 0;
323 }
324 else { /* enabled */
325 if ((*dat & POT_NOX) == 0) { /* output char? */
326 mux_xbuf[ln] = chr; /* store char */
327 sim_activate (&muxl_unit[ln], muxl_unit[ln].wait);
328 }
329 if (*dat & POT_XMI) mux_sta[ln] = mux_sta[ln] | MUX_SXIE;
330 else mux_sta[ln] = mux_sta[ln] & ~MUX_SXIE;
331 mux_sta[ln] = mux_sta[ln] | MUX_SLNE; /* line is enabled */
332 mux_ldsc[ln].rcve = 1;
333 }
334 return SCPE_OK;
335 }
336
337 /* Unit service - receive side
338
339 Poll all active lines for input
340 Poll for new connections
341 */
342
343 t_stat muxi_svc (UNIT *uptr)
344 {
345 int32 ln, c, t;
346
347 if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK; /* attached? */
348 t = sim_rtcn_calb (mux_tps, TMR_MUX); /* calibrate */
349 sim_activate (uptr, t); /* continue poll */
350 ln = tmxr_poll_conn (&mux_desc); /* look for connect */
351 if (ln >= 0) { /* got one? */
352 if (!PROJ_GENIE && (mux_sta[ln] & MUX_SLNE)) { /* modem & DTR? */
353 mux_sta[ln] = mux_sta[ln] | (MUX_SCRO|MUX_SDSR);/* carrier on */
354 MUX_SETFLG (ln, MUX_FCRN); /* set carr on flag */
355 mux_scan_next (); /* kick scanner */
356 }
357 mux_ldsc[ln].rcve = 1; /* set rcv enable */
358 }
359 tmxr_poll_rx (&mux_desc); /* poll for input */
360 for (ln = 0; ln < MUX_NUMLIN; ln++) { /* loop thru lines */
361 if (mux_ldsc[ln].conn) { /* connected? */
362 if (c = tmxr_getc_ln (&mux_ldsc[ln])) { /* get char */
363 if (mux_sta[ln] & MUX_SCHP) /* already got one? */
364 mux_sta[ln] = mux_sta[ln] | MUX_SOVR; /* overrun */
365 else mux_sta[ln] = mux_sta[ln] | MUX_SCHP; /* char pending */
366 if (c & SCPE_BREAK) c = 0; /* break? */
367 else c = sim_tt_inpcvt (c, TT_GET_MODE (muxl_unit[ln].flags));
368 mux_rbuf[ln] = c; /* save char */
369 MUX_SETFLG (ln, MUX_FRCV); /* set rcv flag */
370 mux_scan_next (); /* kick scanner */
371 }
372 }
373 else mux_sta[ln] = 0; /* disconnected */
374 } /* end for */
375 return SCPE_OK;
376 }
377
378 /* Unit service - transmit side */
379
380 t_stat muxo_svc (UNIT *uptr)
381 {
382 int32 c;
383 uint32 ln = uptr - muxl_unit; /* line # */
384
385 if (mux_ldsc[ln].conn) { /* connected? */
386 if (mux_ldsc[ln].xmte) { /* xmt enabled? */
387 c = sim_tt_outcvt (mux_xbuf[ln], TT_GET_MODE (muxl_unit[ln].flags));
388 if (c >= 0) tmxr_putc_ln (&mux_ldsc[ln], c); /* output char */
389 tmxr_poll_tx (&mux_desc); /* poll xmt */
390 }
391 else { /* buf full */
392 tmxr_poll_tx (&mux_desc); /* poll xmt */
393 sim_activate (uptr, muxl_unit[ln].wait); /* wait */
394 return SCPE_OK;
395 }
396 }
397 if (mux_sta[ln] & MUX_SXIE) {
398 MUX_SETFLG (ln, MUX_FXMT); /* set flag */
399 mux_scan_next (); /* kick scanner */
400 }
401 return SCPE_OK;
402 }
403
404 /* Kick scanner */
405
406 void mux_scan_next (void)
407 {
408 int32 i;
409
410 if (mux_slck) return; /* locked? */
411 for (i = 0; i < MUX_SCANMAX; i++) { /* scan flags */
412 mux_scan = (mux_scan + 1) & MUX_SCANMASK; /* next flag */
413 if (mux_flags[mux_scan]) { /* flag set? */
414 mux_slck = 1; /* lock scanner */
415 MUX_SETINT (mux_scan & MUX_FLAGMASK); /* request int */
416 return;
417 }
418 }
419 return;
420 }
421
422 /* Reset routine */
423
424 t_stat mux_reset (DEVICE *dptr)
425 {
426 int32 i, t;
427
428 if (mux_dev.flags & DEV_DIS) /* master disabled? */
429 muxl_dev.flags = muxl_dev.flags | DEV_DIS; /* disable lines */
430 else muxl_dev.flags = muxl_dev.flags & ~DEV_DIS;
431 if (mux_unit.flags & UNIT_ATT) { /* master att? */
432 if (!sim_is_active (&mux_unit)) {
433 t = sim_rtcn_init (mux_unit.wait, TMR_MUX);
434 sim_activate (&mux_unit, t); /* activate */
435 }
436 }
437 else sim_cancel (&mux_unit); /* else stop */
438 for (i = 0; i < MUX_LINES; i++) mux_reset_ln (i);
439 for (i = 0; i < MUX_FLAGS; i++) MUX_CLRINT (i); /* clear all ints */
440 return SCPE_OK;
441 }
442
443 /* Attach master unit */
444
445 t_stat mux_attach (UNIT *uptr, char *cptr)
446 {
447 t_stat r;
448 int32 t;
449
450 r = tmxr_attach (&mux_desc, uptr, cptr); /* attach */
451 if (r != SCPE_OK) return r; /* error */
452 t = sim_rtcn_init (mux_unit.wait, TMR_MUX);
453 sim_activate (uptr, t); /* start poll */
454 return SCPE_OK;
455 }
456
457 /* Detach master unit */
458
459 t_stat mux_detach (UNIT *uptr)
460 {
461 int32 i;
462 t_stat r;
463
464 r = tmxr_detach (&mux_desc, uptr); /* detach */
465 for (i = 0; i < MUX_LINES; i++) mux_ldsc[i].rcve = 0; /* disable rcv */
466 sim_cancel (uptr); /* stop poll */
467 return r;
468 }
469
470 /* Show summary processor */
471
472 t_stat mux_summ (FILE *st, UNIT *uptr, int32 val, void *desc)
473 {
474 int32 i, t;
475
476 for (i = t = 0; i < MUX_LINES; i++) t = t + (mux_ldsc[i].conn != 0);
477 if (t == 1) fprintf (st, "1 connection");
478 else fprintf (st, "%d connections", t);
479 return SCPE_OK;
480 }
481
482 /* SHOW CONN/STAT processor */
483
484 t_stat mux_show (FILE *st, UNIT *uptr, int32 val, void *desc)
485 {
486 int32 i, t;
487
488 for (i = t = 0; i < MUX_LINES; i++) t = t + (mux_ldsc[i].conn != 0);
489 if (t) {
490 for (i = 0; i < MUX_LINES; i++) {
491 if (mux_ldsc[i].conn) {
492 if (val) tmxr_fconns (st, &mux_ldsc[i], i);
493 else tmxr_fstats (st, &mux_ldsc[i], i);
494 }
495 }
496 }
497 else fprintf (st, "all disconnected\n");
498 return SCPE_OK;
499 }
500
501 /* Change number of lines */
502
503 t_stat mux_vlines (UNIT *uptr, int32 val, char *cptr, void *desc)
504 {
505 int32 newln, i, t;
506 t_stat r;
507
508 if (cptr == NULL) return SCPE_ARG;
509 newln = get_uint (cptr, 10, MUX_LINES, &r);
510 if ((r != SCPE_OK) || (newln == MUX_NUMLIN)) return r;
511 if (newln == 0) return SCPE_ARG;
512 if (newln < MUX_NUMLIN) {
513 for (i = newln, t = 0; i < MUX_NUMLIN; i++) t = t | mux_ldsc[i].conn;
514 if (t && !get_yn ("This will disconnect users; proceed [N]?", FALSE))
515 return SCPE_OK;
516 for (i = newln; i < MUX_NUMLIN; i++) {
517 if (mux_ldsc[i].conn) {
518 tmxr_linemsg (&mux_ldsc[i], "\r\nOperator disconnected line\r\n");
519 tmxr_reset_ln (&mux_ldsc[i]); /* reset line */
520 }
521 muxl_unit[i].flags = muxl_unit[i].flags | UNIT_DIS;
522 mux_reset_ln (i);
523 }
524 }
525 else {
526 for (i = MUX_NUMLIN; i < newln; i++) {
527 muxl_unit[i].flags = muxl_unit[i].flags & ~UNIT_DIS;
528 mux_reset_ln (i);
529 }
530 }
531 MUX_NUMLIN = newln;
532 return SCPE_OK;
533 }
534
535 /* Reset an individual line */
536
537 void mux_reset_ln (int32 ln)
538 {
539 int32 flg = ln * MUX_FLAGS;
540
541 if (mux_ldsc[ln].conn) mux_sta[ln] = MUX_SCRO | MUX_SDSR;
542 else mux_sta[ln] = 0;
543 sim_cancel (&muxl_unit[ln]);
544 mux_flags[flg + MUX_FRCV] = 0;
545 mux_flags[flg + MUX_FXMT] = 0;
546 mux_flags[flg + MUX_FCRN] = 0;
547 mux_flags[flg + MUX_FCRF] = 0;
548 return;
549 }