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First Commit of my working state
[simh.git] / VAX / vax780_defs.h
1
2 /* vax780_defs.h: VAX 780 model-specific definitions file
3
4 Copyright (c) 2004-2007, Robert M Supnik
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
20 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22
23 Except as contained in this notice, the name of Robert M Supnik shall not be
24 used in advertising or otherwise to promote the sale, use or other dealings
25 in this Software without prior written authorization from Robert M Supnik.
26
27 29-Apr-07 RMS Modified model-specific reserved operand check macros
28 to reflect 780 microcode patches (found by Naoki Hamada)
29 29-Oct-06 RMS Added clock coscheduler function
30 17-May-06 RMS Added CR11/CD11 support (from John Dundas)
31 10-May-06 RMS Added model-specific reserved operand check macros
32
33 This file covers the VAX 11/780, the first VAX.
34
35 System memory map
36
37 0000 0000 - 1FFF FFFF main memory
38
39 2000 0000 - 2001 FFFF nexus register space
40 2002 0000 - 200F FFFF reserved
41 2010 0000 - 2013 FFFF Unibus address space, Unibus 0
42 2014 0000 - 2017 FFFF Unibus address space, Unibus 1
43 2018 0000 - 201B FFFF Unibus address space, Unibus 2
44 201C 0000 - 201F FFFF Unibus address space, Unibus 3
45 2020 0000 - 3FFF FFFF reserved
46 */
47
48 #ifndef FULL_VAX
49 #define FULL_VAX 1
50 #endif
51
52 #ifndef _VAX_780_DEFS_H_
53 #define _VAX_780_DEFS_H_ 1
54
55 /* Microcode constructs */
56
57 #define VAX780_SID (1 << 24) /* system ID */
58 #define VAX780_ECO (7 << 19) /* ucode revision */
59 #define VAX780_PLANT (0 << 12) /* plant (Salem NH) */
60 #define VAX780_SN (1234)
61 #define CON_HLTPIN 0x0200 /* external CPU halt */
62 #define CON_HLTINS 0x0600 /* HALT instruction */
63 #define MCHK_RD_F 0x00 /* read fault */
64 #define MCHK_RD_A 0xF4 /* read abort */
65 #define MCHK_IBUF 0x0D /* read istream */
66 #define VER_FPLA 0x0C /* FPLA version */
67 #define VER_WCSP (VER_FPLA) /* WCS primary version */
68 #define VER_WCSS 0x12 /* WCS secondary version */
69 #define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */
70
71 /* Interrupts */
72
73 #define IPL_HMAX 0x17 /* highest hwre level */
74 #define IPL_HMIN 0x14 /* lowest hwre level */
75 #define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
76 #define IPL_SMAX 0xF /* highest swre level */
77
78 /* Nexus constants */
79
80 #define NEXUS_NUM 16 /* number of nexus */
81 #define MCTL_NUM 2 /* number of mem ctrl */
82 #define MBA_NUM 2 /* number of MBA's */
83 #define TR_MCTL0 1 /* nexus assignments */
84 #define TR_MCTL1 2
85 #define TR_UBA 3
86 #define TR_MBA0 8
87 #define TR_MBA1 9
88 #define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1)
89 #define SCB_NEXUS 0x100 /* nexus intr base */
90 #define SBI_FAULTS 0xFC000000 /* SBI fault flags */
91
92 /* Internal I/O interrupts - relative except for clock and console */
93
94 #define IPL_CLKINT 0x18 /* clock IPL */
95 #define IPL_TTINT 0x14 /* console IPL */
96
97 #define IPL_MCTL0 (0x15 - IPL_HMIN)
98 #define IPL_MCTL1 (0x15 - IPL_HMIN)
99 #define IPL_UBA (0x15 - IPL_HMIN)
100 #define IPL_MBA0 (0x15 - IPL_HMIN)
101 #define IPL_MBA1 (0x15 - IPL_HMIN)
102
103 /* Nexus interrupt macros */
104
105 #define SET_NEXUS_INT(dv) nexus_req[IPL_##dv] |= (1 << TR_##dv)
106 #define CLR_NEXUS_INT(dv) nexus_req[IPL_##dv] &= ~(1 << TR_##dv)
107
108 /* Machine specific IPRs */
109
110 #define MT_ACCS 40 /* FPA control */
111 #define MT_ACCR 41 /* FPA maint */
112 #define MT_WCSA 44 /* WCS address */
113 #define MT_WCSD 45 /* WCS data */
114 #define MT_SBIFS 48 /* SBI fault status */
115 #define MT_SBIS 49 /* SBI silo */
116 #define MT_SBISC 50 /* SBI silo comparator */
117 #define MT_SBIMT 51 /* SBI maint */
118 #define MT_SBIER 52 /* SBI error */
119 #define MT_SBITA 53 /* SBI timeout addr */
120 #define MT_SBIQC 54 /* SBI timeout clear */
121 #define MT_MBRK 60 /* microbreak */
122
123 /* Machine specific reserved operand tests */
124
125 /* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
126
127 #define ML_LR_TEST(r) if ((uint32)((r) & 0xFFFFFF) > 0x200000) RSVD_OPND_FAULT
128
129 /* 780 microcode patch 38 - only test PxBR<31>=1 and xBR<1:0> = 0 */
130
131 #define ML_PXBR_TEST(r) if ((((r) & 0x80000000) == 0) || \
132 ((r) & 0x00000003)) RSVD_OPND_FAULT
133 #define ML_SBR_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT
134
135 /* 780 microcode patch 78 - only test xCBB<1:0> = 0 */
136
137 #define ML_PA_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT
138
139 #define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
140 #define LP_MBZ84_TEST(r) if ((r) & 0xF8C00000) RSVD_OPND_FAULT
141 #define LP_MBZ92_TEST(r) if ((r) & 0x7FC00000) RSVD_OPND_FAULT
142
143 /* Memory */
144
145 #define MAXMEMWIDTH 23 /* max mem, MS780C */
146 #define MAXMEMSIZE (1 << MAXMEMWIDTH)
147 #define MAXMEMWIDTH_X 27 /* max mem, MS780E */
148 #define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
149 #define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
150 #define MEMSIZE (cpu_unit.capac)
151 #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
152
153 /* Unibus I/O registers */
154
155 #define UBADDRWIDTH 18 /* Unibus addr width */
156 #define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */
157 #define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */
158 #define IOPAGEAWIDTH 13 /* IO addr width */
159 #define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */
160 #define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */
161 #define UBADDRBASE 0x20100000 /* Unibus addr base */
162 #define IOPAGEBASE 0x2013E000 /* IO page base */
163 #define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \
164 (((uint32) (x)) < (UBADDRBASE + UBADDRSIZE)))
165 #define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE)
166
167 /* Nexus register space */
168
169 #define REGAWIDTH 17 /* REG addr width */
170 #define REG_V_NEXUS 13 /* nexus number */
171 #define REG_M_NEXUS 0xF
172 #define REG_V_OFS 2 /* register number */
173 #define REG_M_OFS 0x7FF
174 #define REGSIZE (1u << REGAWIDTH) /* REG length */
175 #define REGBASE 0x20000000 /* REG addr base */
176 #define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \
177 (((uint32) (x)) < (REGBASE + REGSIZE)))
178 #define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS)
179 #define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS)
180
181 /* ROM address space in memory controllers */
182
183 #define ROMAWIDTH 12 /* ROM addr width */
184 #define ROMSIZE (1u << ROMAWIDTH) /* ROM size */
185 #define ROM0BASE (REGBASE + (TR_MCTL0 << REG_V_NEXUS) + 0x1000)
186 #define ROM1BASE (REGBASE + (TR_MCTL1 << REG_V_NEXUS) + 0x1000)
187 #define ADDR_IS_ROM0(x) ((((uint32) (x)) >= ROM0BASE) && \
188 (((uint32) (x)) < (ROM0BASE + ROMSIZE)))
189 #define ADDR_IS_ROM1(x) ((((uint32) (x)) >= ROM1BASE) && \
190 (((uint32) (x)) < (ROM1BASE + ROMSIZE)))
191 #define ADDR_IS_ROM(x) (ADDR_IS_ROM0 (x) || ADDR_IS_ROM1 (x))
192
193 /* Other address spaces */
194
195 #define ADDR_IS_CDG(x) (0)
196 #define ADDR_IS_NVR(x) (0)
197
198 /* Unibus I/O modes */
199
200 #define READ 0 /* PDP-11 compatibility */
201 #define WRITE (L_WORD)
202 #define WRITEB (L_BYTE)
203
204 /* Common CSI flags */
205
206 #define CSR_V_GO 0 /* go */
207 #define CSR_V_IE 6 /* interrupt enable */
208 #define CSR_V_DONE 7 /* done */
209 #define CSR_V_BUSY 11 /* busy */
210 #define CSR_V_ERR 15 /* error */
211 #define CSR_GO (1u << CSR_V_GO)
212 #define CSR_IE (1u << CSR_V_IE)
213 #define CSR_DONE (1u << CSR_V_DONE)
214 #define CSR_BUSY (1u << CSR_V_BUSY)
215 #define CSR_ERR (1u << CSR_V_ERR)
216
217 /* Timers */
218
219 #define TMR_CLK 0 /* 100Hz clock */
220
221 /* I/O system definitions */
222
223 #define DZ_MUXES 4 /* max # of DZV muxes */
224 #define DZ_LINES 8 /* lines per DZV mux */
225 #define VH_MUXES 4 /* max # of DHQ muxes */
226 #define MT_MAXFR (1 << 16) /* magtape max rec */
227
228 #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
229 #define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */
230 #define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */
231 #define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */
232 #define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */
233 #define DEV_UBUS (1u << DEV_V_UBUS)
234 #define DEV_MBUS (1u << DEV_V_MBUS)
235 #define DEV_NEXUS (1u << DEV_V_NEXUS)
236 #define DEV_FLTA (1u << DEV_V_FLTA)
237 #define DEV_QBUS (0)
238 #define DEV_Q18 (0)
239
240 #define UNIBUS TRUE /* Unibus only */
241
242 #define DEV_RDX 16 /* default device radix */
243
244 /* Device information block
245
246 For Massbus devices,
247 ba = Massbus number
248 lnt = Massbus ctrl type
249 ack[0] = abort routine
250
251 For Nexus devices,
252 ba = Nexus number
253 lnt = number of consecutive nexi */
254
255 #define VEC_DEVMAX 4 /* max device vec */
256
257 typedef struct {
258 uint32 ba; /* base addr */
259 uint32 lnt; /* length */
260 t_stat (*rd)(int32 *dat, int32 ad, int32 md);
261 t_stat (*wr)(int32 dat, int32 ad, int32 md);
262 int32 vnum; /* vectors: number */
263 int32 vloc; /* locator */
264 int32 vec; /* value */
265 int32 (*ack[VEC_DEVMAX])(void); /* ack routine */
266 } DIB;
267
268 /* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's
269 Massbus devices (RP, TU) do not appear in the Unibus IO page */
270
271 #define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */
272 #define IOLN_DZ 010
273 #define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
274 #define IOLN_XUB 010
275 #define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))
276 #define IOLN_RQB 004
277 #define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
278 #define IOLN_RQC 004
279 #define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
280 #define IOLN_RQD 004
281 #define IOBA_RQ (IOPAGEBASE + 012150) /* UDA50 */
282 #define IOLN_RQ 004
283 #define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */
284 #define IOLN_TS 004
285 #define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */
286 #define IOLN_RL 012
287 #define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */
288 #define IOLN_XQ 020
289 #define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */
290 #define IOLN_XQB 020
291 #define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */
292 #define IOLN_TQ 004
293 #define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */
294 #define IOLN_XU 010
295 #define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */
296 #define IOLN_CR 010
297 #define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */
298 #define IOLN_RX 004
299 #define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */
300 #define IOLN_RY 004
301 #define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */
302 #define IOLN_QDSS 002
303 #define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */
304 #define IOLN_HK 040
305 #define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */
306 #define IOLN_LPT 004
307 #define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */
308 #define IOLN_PTR 004
309 #define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
310 #define IOLN_PTP 004
311
312 /* Interrupt assignments; within each level, priority is right to left */
313
314 #define INT_V_DZRX 0 /* BR5 */
315 #define INT_V_DZTX 1
316 #define INT_V_HK 2
317 #define INT_V_RL 3
318 #define INT_V_RQ 4
319 #define INT_V_TQ 5
320 #define INT_V_TS 6
321 #define INT_V_RY 7
322 #define INT_V_XU 8
323
324 #define INT_V_LPT 0 /* BR4 */
325 #define INT_V_PTR 1
326 #define INT_V_PTP 2
327 #define INT_V_CR 3
328
329 #define INT_DZRX (1u << INT_V_DZRX)
330 #define INT_DZTX (1u << INT_V_DZTX)
331 #define INT_HK (1u << INT_V_HK)
332 #define INT_RL (1u << INT_V_RL)
333 #define INT_RQ (1u << INT_V_RQ)
334 #define INT_TQ (1u << INT_V_TQ)
335 #define INT_TS (1u << INT_V_TS)
336 #define INT_RY (1u << INT_V_RY)
337 #define INT_XU (1u << INT_V_XU)
338 #define INT_LPT (1u << INT_V_LPT)
339 #define INT_PTR (1u << INT_V_PTR)
340 #define INT_PTP (1u << INT_V_PTP)
341 #define INT_CR (1u << INT_V_CR)
342
343 #define IPL_DZRX (0x15 - IPL_HMIN)
344 #define IPL_DZTX (0x15 - IPL_HMIN)
345 #define IPL_HK (0x15 - IPL_HMIN)
346 #define IPL_RL (0x15 - IPL_HMIN)
347 #define IPL_RQ (0x15 - IPL_HMIN)
348 #define IPL_TQ (0x15 - IPL_HMIN)
349 #define IPL_TS (0x15 - IPL_HMIN)
350 #define IPL_RY (0x15 - IPL_HMIN)
351 #define IPL_XU (0x15 - IPL_HMIN)
352 #define IPL_LPT (0x14 - IPL_HMIN)
353 #define IPL_PTR (0x14 - IPL_HMIN)
354 #define IPL_PTP (0x14 - IPL_HMIN)
355 #define IPL_CR (0x14 - IPL_HMIN)
356
357 /* Device vectors */
358
359 #define VEC_Q 0000
360 #define VEC_PTR 0070
361 #define VEC_PTP 0074
362 #define VEC_XQ 0120
363 #define VEC_XU 0120
364 #define VEC_RQ 0154
365 #define VEC_RL 0160
366 #define VEC_LPT 0200
367 #define VEC_HK 0210
368 #define VEC_TS 0224
369 #define VEC_CR 0230
370 #define VEC_TQ 0260
371 #define VEC_RX 0264
372 #define VEC_RY 0264
373 #define VEC_DZRX 0300
374 #define VEC_DZTX 0304
375
376 /* Interrupt macros */
377
378 #define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)
379 #define NVCL(dv) ((IPL_##dv * 32) + TR_##dv)
380 #define IREQ(dv) int_req[IPL_##dv]
381 #define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
382 #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
383 #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
384
385 /* Logging */
386
387 #define LOG_CPU_I 0x1 /* intexc */
388 #define LOG_CPU_R 0x2 /* REI */
389 #define LOG_CPU_P 0x4 /* context */
390
391 /* Massbus definitions */
392
393 #define MBA_RP (TR_MBA0 - TR_MBA0) /* MBA for RP */
394 #define MBA_TU (TR_MBA1 - TR_MBA0) /* MBA for TU */
395 #define MBA_RMASK 0x1F /* max 32 reg */
396 #define MBE_NXD 1 /* nx drive */
397 #define MBE_NXR 2 /* nx reg */
398 #define MBE_GOE 3 /* err on GO */
399
400 /* Boot definitions */
401
402 #define BOOT_MB 0 /* device codes */
403 #define BOOT_HK 1 /* for VMB */
404 #define BOOT_RL 2
405 #define BOOT_UDA 17
406 #define BOOT_TK 18
407
408 /* Function prototypes for virtual memory interface */
409
410 int32 Read (uint32 va, int32 lnt, int32 acc);
411 void Write (uint32 va, int32 val, int32 lnt, int32 acc);
412
413 /* Function prototypes for physical memory interface (inlined) */
414
415 SIM_INLINE_GCC int32 ReadB (uint32 pa);
416 SIM_INLINE_GCC int32 ReadW (uint32 pa);
417 SIM_INLINE_GCC int32 ReadL (uint32 pa);
418 SIM_INLINE_GCC int32 ReadLP (uint32 pa);
419 SIM_INLINE_GCC void WriteB (uint32 pa, int32 val);
420 SIM_INLINE_GCC void WriteW (uint32 pa, int32 val);
421 SIM_INLINE_GCC void WriteL (uint32 pa, int32 val);
422 void WriteLP (uint32 pa, int32 val);
423
424 /* Function prototypes for I/O */
425
426 int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
427 int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
428 int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);
429 int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);
430
431 t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);
432 t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);
433 t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);
434 t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);
435 t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
436 t_stat auto_config (char *name, int32 num);
437
438 int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf);
439 int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf);
440 int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf);
441 int32 mba_get_bc (uint32 mbus);
442 void mba_upd_ata (uint32 mbus, uint32 val);
443 void mba_set_exc (uint32 mbus);
444 void mba_set_don (uint32 mbus);
445 void mba_set_enbdis (uint32 mbus, t_bool dis);
446 t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc);
447
448 t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);
449
450 void sbi_set_errcnf (void);
451 int32 clk_cosched (int32 wait);
452
453 #endif
Magically enhanced SIMH