VAX/vax780_mem.c

   1 /* vax780_mem.c: VAX 11/780 memory controllers
   2
   3    Copyright (c) 2004-2005, Robert M Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    This module contains the VAX 11/780 system-specific registers and devices.
  27
  28    mctl0, mctl1         MS780C/E memory controllers
  29 */
  30
  31 #include "vax_defs.h"
  32
  33 /* Memory controller register A */
  34
  35 #define MCRA_OF         0x0
  36 #define MCRA_SUMM       0x00100000                      /* err summ (MS780E) */
  37 #define MCRA_C_SIZE     0x00007E00                      /* array size - fixed */
  38 #define MCRA_V_SIZE     9
  39 #define MCRA_ILVE       0x00000100                      /* interleave wr enab */
  40 #define MCRA_TYPE       0x000000F8                      /* type */
  41 #define MCRA_C_TYPE     0x00000010                      /* 16k uninterleaved */
  42 #define MCRA_E_TYPE     0x0000006A                      /* 256k upper + lower */
  43 #define MCRA_ILV        0x00000007                      /* interleave */
  44 #define MCRA_RD         (0x00107FFF|SBI_FAULTS)
  45 #define MCRA_WR         0x00000100
  46
  47 /* Memory controller register B */
  48
  49 #define MCRB_OF         0x1
  50 #define MCRB_FP         0xF0000000                      /* file pointers */
  51 #define MCRB_V_SA       15                              /* start addr */
  52 #define MCRB_M_SA       0x1FFF
  53 #define MCRB_SA         (MCRB_M_SA << MCRB_V_SA)
  54 #define MCRB_SAE        0x00004000                      /* start addr wr enab */
  55 #define MCRB_INIT       0x00003000                      /* init state */
  56 #define MCRB_REF        0x00000400                      /* refresh */
  57 #define MCRB_ECC        0x000003FF                      /* ECC for diags */
  58 #define MCRB_RD         0xFFFFF7FF
  59 #define MCRB_WR         0x000043FF
  60
  61 /* Memory controller register C,D */
  62
  63 #define MCRC_OF         0x2
  64 #define MCRD_OF         0x3
  65 #define MCRC_DCRD       0x40000000                      /* disable CRD */
  66 #define MCRC_HER        0x20000000                      /* high error rate */
  67 #define MCRC_ERL        0x10000000                      /* log error */
  68 #define MCRC_C_ER       0x0FFFFFFF                      /* MS780C error */
  69 #define MCRC_E_PE1      0x00080000                      /* MS780E par ctl 1 */
  70 #define MCRC_E_PE0      0x00040000                      /* MS780E par ctl 0 */
  71 #define MCRC_E_CRD      0x00000200                      /* MS780E CRD */
  72 #define MCRC_E_PEW      0x00000100                      /* MS780E par err wr */
  73 #define MCRC_E_USEQ     0x00000080                      /* MS780E seq err */
  74 #define MCRC_C_RD       0x7FFFFFFF
  75 #define MCRC_E_RD       0x700C0380
  76 #define MCRC_WR         0x40000000
  77 #define MCRC_C_W1C      0x30000000
  78 #define MCRC_E_W1C      0x300C0380
  79
  80 #define MCRROM_OF       0x400
  81
  82 uint32 mcr_a[MCTL_NUM];
  83 uint32 mcr_b[MCTL_NUM];
  84 uint32 mcr_c[MCTL_NUM];
  85 uint32 mcr_d[MCTL_NUM];
  86 uint32 rom_lw[MCTL_NUM][ROMSIZE >> 2];
  87
  88 extern UNIT cpu_unit;
  89
  90 t_stat mctl_reset (DEVICE *dptr);
  91 t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
  92 t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
  93
  94 /* MCTLx data structures
  95
  96    mctlx_dev    MCTLx device descriptor
  97    mctlx_unit   MCTLx unit
  98    mctlx_reg    MCTLx register list
  99 */
 100
 101 DIB mctl0_dib[] = { TR_MCTL0, 0, &mctl_rdreg, &mctl_wrreg, 0 };
 102
 103 UNIT mctl0_unit = { UDATA (NULL, 0, 0) };
 104
 105 REG mctl0_reg[] = {
 106     { HRDATA (CRA, mcr_a[0], 32) },
 107     { HRDATA (CRB, mcr_b[0], 32) },
 108     { HRDATA (CRC, mcr_c[0], 32) },
 109     { HRDATA (CRD, mcr_d[0], 32) },
 110     { BRDATA (ROM, rom_lw[0], 16, 32, ROMSIZE >> 2) },
 111     { NULL }
 112     };
 113
 114 MTAB mctl0_mod[] = {
 115     { MTAB_XTD|MTAB_VDV, TR_MCTL0, "NEXUS", NULL,
 116       NULL, &show_nexus },
 117     { 0 }
 118     };
 119
 120 DIB mctl1_dib[] = { TR_MCTL1, 0, &mctl_rdreg, &mctl_wrreg, 0 };
 121
 122 UNIT mctl1_unit = { UDATA (NULL, 0, 0) };
 123
 124 MTAB mctl1_mod[] = {
 125     { MTAB_XTD|MTAB_VDV, TR_MCTL1, "NEXUS", NULL,
 126       NULL, &show_nexus },
 127     { 0 }  };
 128
 129 REG mctl1_reg[] = {
 130     { HRDATA (CRA, mcr_a[1], 32) },
 131     { HRDATA (CRB, mcr_b[1], 32) },
 132     { HRDATA (CRC, mcr_c[1], 32) },
 133     { HRDATA (CRD, mcr_d[1], 32) },
 134     { BRDATA (ROM, rom_lw[1], 16, 32, ROMSIZE >> 2) },
 135     { NULL }
 136     };
 137
 138 DEVICE mctl_dev[] = {
 139     {
 140     "MCTL0", &mctl0_unit, mctl0_reg, mctl0_mod,
 141     1, 16, 16, 1, 16, 8,
 142     NULL, NULL, &mctl_reset,
 143     NULL, NULL, NULL,
 144     &mctl0_dib, DEV_NEXUS
 145     },
 146     {
 147     "MCTL1", &mctl1_unit, mctl1_reg, mctl1_mod,
 148     1, 16, 16, 1, 16, 8,
 149     NULL, NULL, &mctl_reset,
 150     NULL, NULL, NULL,
 151     &mctl1_dib, DEV_NEXUS
 152     }
 153     };
 154
 155 /* Memory controller register read */
 156
 157 t_stat mctl_rdreg (int32 *val, int32 pa, int32 lnt)
 158 {
 159 int32 mctl, ofs;
 160 t_bool extmem = MEMSIZE > MAXMEMSIZE;
 161
 162 if ((pa & 3) || (lnt != L_LONG)) {                      /* unaligned or not lw? */
 163     printf (">>MCTL: invalid adapter read mask, pa = %X, lnt = %d\r\n", pa, lnt);
 164     sbi_set_errcnf ();                                  /* err confirmation */
 165     return SCPE_OK;
 166     }
 167 mctl = NEXUS_GETNEX (pa) - TR_MCTL0;                    /* get mctl num */
 168 ofs = NEXUS_GETOFS (pa);                                /* get offset */
 169 if (ofs >= MCRROM_OF) {                                 /* ROM? */
 170     *val = rom_lw[mctl][ofs - MCRROM_OF];               /* get lw */
 171     return SCPE_OK;
 172     }
 173 switch (ofs) {
 174
 175     case MCRA_OF:                                       /* CR A */
 176         *val = mcr_a[mctl] & MCRA_RD;
 177         break;
 178
 179     case MCRB_OF:                                       /* CR B */
 180         *val = (mcr_b[mctl] & MCRB_RD) | MCRB_INIT;
 181         break;
 182
 183     case MCRC_OF:                                       /* CR C */
 184         *val = mcr_c[mctl] & (extmem? MCRC_E_RD: MCRC_C_RD);
 185         break;
 186
 187     case MCRD_OF:                                       /* CR D */
 188         if (!extmem) return SCPE_NXM;                   /* MS780E only */
 189         *val = mcr_d[mctl] & MCRC_E_RD;
 190         break;
 191
 192     default:
 193         return SCPE_NXM;
 194         }
 195
 196 return SCPE_OK;
 197 }
 198
 199 /* Memory controller register write */
 200
 201 t_stat mctl_wrreg (int32 val, int32 pa, int32 lnt)
 202 {
 203 int32 mctl, ofs, mask;
 204 t_bool extmem = MEMSIZE > MAXMEMSIZE;
 205
 206 if ((pa & 3) || (lnt != L_LONG)) {                      /* unaligned or not lw? */
 207     printf (">>MCTL: invalid adapter write mask, pa = %X, lnt = %d\r\n", pa, lnt);
 208     sbi_set_errcnf ();                                  /* err confirmation */
 209     return SCPE_OK;
 210     }
 211 mctl = NEXUS_GETNEX (pa) - TR_MCTL0;                    /* get mctl num */
 212 ofs = NEXUS_GETOFS (pa);                                /* get offset */
 213 switch (ofs) {
 214
 215     case MCRA_OF:                                       /* CR A */
 216         mask = MCRA_WR | ((val & MCRA_ILVE)? MCRA_ILV: 0);
 217         mcr_a[mctl] = (mcr_a[mctl] & ~mask) | (val & mask);
 218         break;
 219
 220     case MCRB_OF:                                       /* CR B */
 221         mask = MCRB_WR | ((val & MCRB_SAE)? MCRB_SA: 0);
 222         mcr_b[mctl] = (mcr_b[mctl] & ~mask) | (val & mask);
 223         break;
 224
 225     case MCRC_OF:                                       /* CR C */
 226         mcr_c[mctl] = ((mcr_c[mctl] & ~MCRC_WR) | (val & MCRC_WR)) &
 227             ~(val & (extmem? MCRC_E_W1C: MCRC_C_W1C));
 228         break;
 229
 230     case MCRD_OF:                                       /* CR D */
 231         if (!extmem) return SCPE_NXM;                   /* MS780E only */
 232         mcr_d[mctl] = ((mcr_d[mctl] & ~MCRC_WR) | (val & MCRC_WR)) &
 233             ~(val & MCRC_E_W1C);
 234         break;
 235
 236     default:
 237         return SCPE_NXM;
 238         }
 239
 240 return SCPE_OK;
 241 }
 242
 243 /* Used by CPU and loader */
 244
 245 void rom_wr_B (int32 pa, int32 val)
 246 {
 247 uint32 mctl = NEXUS_GETNEX (pa) - TR_MCTL0;             /* get mctl num */
 248 uint32 ofs = NEXUS_GETOFS (pa) - MCRROM_OF;             /* get offset */
 249 int32 sc = (pa & 3) << 3;
 250
 251 rom_lw[mctl][ofs] = ((val & 0xFF) << sc) | (rom_lw[mctl][ofs] & ~(0xFF << sc));
 252 return;
 253 }
 254
 255 /* MEMCTL reset */
 256
 257 t_stat mctl_reset (DEVICE *dptr)
 258 {
 259 int32 i, amb;
 260 t_bool extmem = MEMSIZE > MAXMEMSIZE;
 261
 262 amb = (int32) (MEMSIZE / 2) >> 20;                      /* array size MB */
 263 for (i = 0; i < MCTL_NUM; i++) {                        /* init for MS780C */
 264     if (extmem) {                                       /* extended memory? */
 265         mcr_a[i] = ((amb - 1) << MCRA_V_SIZE) | MCRA_E_TYPE;
 266         mcr_b[i] = MCRB_INIT | ((i * amb) << (MCRB_V_SA + 4));
 267         }
 268     else {
 269         mcr_a[i] = MCRA_C_SIZE | MCRA_C_TYPE;
 270         mcr_b[i] = MCRB_INIT | (i << 21);
 271         }
 272     mcr_c[i] = 0;
 273     mcr_d[i] = 0;
 274     }
 275 return SCPE_OK;
 276 }