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First Commit of my working state
[simh.git] / VAX / vax_io.c
1 /* vax_io.c: VAX 3900 Qbus IO simulator
2
3 Copyright (c) 1998-2008, Robert M Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 qba Qbus adapter
27
28 28-May-08 RMS Inlined physical memory routines
29 25-Jan-08 RMS Fixed declarations (from Mark Pizzolato)
30 03-Dec-05 RMS Added SHOW QBA VIRT and ex/dep via map
31 05-Oct-05 RMS Fixed bug in autoconfiguration (missing XU)
32 25-Jul-05 RMS Revised autoconfiguration algorithm and interface
33 30-Sep-04 RMS Revised Qbus interface
34 Moved mem_err, crd_err interrupts here from vax_cpu.c
35 09-Sep-04 RMS Integrated powerup into RESET (with -p)
36 05-Sep-04 RMS Added CRD interrupt handling
37 28-May-04 RMS Revised I/O dispatching (from John Dundas)
38 21-Mar-04 RMS Added RXV21 support
39 21-Dec-03 RMS Fixed bug in autoconfigure vector assignment; added controls
40 21-Nov-03 RMS Added check for interrupt slot conflict (found by Dave Hittner)
41 29-Oct-03 RMS Fixed WriteX declaration (found by Mark Pizzolato)
42 19-Apr-03 RMS Added optimized byte and word DMA routines
43 12-Mar-03 RMS Added logical name support
44 22-Dec-02 RMS Added console halt support
45 12-Oct-02 RMS Added autoconfigure support
46 Added SHOW IO space routine
47 29-Sep-02 RMS Added dynamic table support
48 07-Sep-02 RMS Added TMSCP and variable vector support
49 */
50
51 #include "vax_defs.h"
52
53 /* CQBIC system configuration register */
54
55 #define CQSCR_POK 0x00008000 /* power ok RO1 */
56 #define CQSCR_BHL 0x00004000 /* BHALT enb */
57 #define CQSCR_AUX 0x00000400 /* aux mode RONI */
58 #define CQSCR_DBO 0x0000000C /* offset NI */
59 #define CQSCR_RW (CQSCR_BHL | CQSCR_DBO)
60 #define CQSCR_MASK (CQSCR_RW | CQSCR_POK | CQSCR_AUX)
61
62 /* CQBIC DMA system error register - W1C */
63
64 #define CQDSER_BHL 0x00008000 /* BHALT NI */
65 #define CQDSER_DCN 0x00004000 /* DC ~OK NI */
66 #define CQDSER_MNX 0x00000080 /* master NXM */
67 #define CQDSER_MPE 0x00000020 /* master par NI */
68 #define CQDSER_SME 0x00000010 /* slv mem err NI */
69 #define CQDSER_LST 0x00000008 /* lost err */
70 #define CQDSER_TMO 0x00000004 /* no grant NI */
71 #define CQDSER_SNX 0x00000001 /* slave NXM */
72 #define CQDSER_ERR (CQDSER_MNX | CQDSER_MPE | CQDSER_TMO | CQDSER_SNX)
73 #define CQDSER_MASK 0x0000C0BD
74
75 /* CQBIC master error address register */
76
77 #define CQMEAR_MASK 0x00001FFF /* Qbus page */
78
79 /* CQBIC slave error address register */
80
81 #define CQSEAR_MASK 0x000FFFFF /* mem page */
82
83 /* CQBIC map base register */
84
85 #define CQMBR_MASK 0x1FFF8000 /* 32KB aligned */
86
87 /* CQBIC IPC register */
88
89 #define CQIPC_QME 0x00008000 /* Qbus read NXM W1C */
90 #define CQIPC_INV 0x00004000 /* CAM inval NIWO */
91 #define CQIPC_AHLT 0x00000100 /* aux halt NI */
92 #define CQIPC_DBIE 0x00000040 /* dbell int enb NI */
93 #define CQIPC_LME 0x00000020 /* local mem enb */
94 #define CQIPC_DB 0x00000001 /* doorbell req NI */
95 #define CQIPC_W1C CQIPC_QME
96 #define CQIPC_RW (CQIPC_AHLT | CQIPC_DBIE | CQIPC_LME | CQIPC_DB)
97 #define CQIPC_MASK (CQIPC_RW | CQIPC_QME )
98
99 /* CQBIC map entry */
100
101 #define CQMAP_VLD 0x80000000 /* valid */
102 #define CQMAP_PAG 0x000FFFFF /* mem page */
103
104 int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */
105 int32 cq_scr = 0; /* SCR */
106 int32 cq_dser = 0; /* DSER */
107 int32 cq_mear = 0; /* MEAR */
108 int32 cq_sear = 0; /* SEAR */
109 int32 cq_mbr = 0; /* MBR */
110 int32 cq_ipc = 0; /* IPC */
111 int32 autcon_enb = 1; /* autoconfig enable */
112
113 extern uint32 *M;
114 extern UNIT cpu_unit;
115 extern int32 PSL, SISR, trpirq, mem_err, crd_err, hlt_pin;
116 extern int32 p1;
117 extern int32 ssc_bto;
118 extern jmp_buf save_env;
119 extern int32 sim_switches;
120 extern DEVICE *sim_devices[];
121 extern FILE *sim_log;
122
123 t_stat dbl_rd (int32 *data, int32 addr, int32 access);
124 t_stat dbl_wr (int32 data, int32 addr, int32 access);
125 int32 eval_int (void);
126 void cq_merr (int32 pa);
127 void cq_serr (int32 pa);
128 t_stat qba_reset (DEVICE *dptr);
129 t_stat qba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
130 t_stat qba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
131 t_bool qba_map_addr (uint32 qa, uint32 *ma);
132 t_bool qba_map_addr_c (uint32 qa, uint32 *ma);
133 t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc);
134 t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc);
135 t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
136 t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc);
137
138 /* Qbus adapter data structures
139
140 qba_dev QBA device descriptor
141 qba_unit QBA units
142 qba_reg QBA register list
143 */
144
145 DIB qba_dib = { IOBA_DBL, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
146
147 UNIT qba_unit = { UDATA (NULL, 0, 0) };
148
149 REG qba_reg[] = {
150 { HRDATA (SCR, cq_scr, 16) },
151 { HRDATA (DSER, cq_dser, 8) },
152 { HRDATA (MEAR, cq_mear, 13) },
153 { HRDATA (SEAR, cq_sear, 20) },
154 { HRDATA (MBR, cq_mbr, 29) },
155 { HRDATA (IPC, cq_ipc, 16) },
156 { HRDATA (IPL17, int_req[3], 32), REG_RO },
157 { HRDATA (IPL16, int_req[2], 32), REG_RO },
158 { HRDATA (IPL15, int_req[1], 32), REG_RO },
159 { HRDATA (IPL14, int_req[0], 32), REG_RO },
160 { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
161 { NULL }
162 };
163
164 MTAB qba_mod[] = {
165 { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
166 NULL, &show_iospace },
167 { MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
168 &set_autocon, &show_autocon },
169 { MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
170 &set_autocon, NULL },
171 { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
172 NULL, &qba_show_virt },
173 { 0 }
174 };
175
176 DEVICE qba_dev = {
177 "QBA", &qba_unit, qba_reg, qba_mod,
178 1, 16, CQMAWIDTH, 2, 16, 16,
179 &qba_ex, &qba_dep, &qba_reset,
180 NULL, NULL, NULL,
181 &qba_dib, DEV_QBUS
182 };
183
184 /* IO page dispatches */
185
186 static t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md);
187 static t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md);
188 static DIB *iodibp[IOPAGESIZE >> 1];
189
190 /* Interrupt request to interrupt action map */
191
192 int32 (*int_ack[IPL_HLVL][32])(); /* int ack routines */
193
194 /* Interrupt request to vector map */
195
196 int32 int_vec[IPL_HLVL][32]; /* int req to vector */
197
198 /* The KA65x handles errors in I/O space as follows
199
200 - read: set DSER<7>, latch addr in MEAR, machine check
201 - write: set DSER<7>, latch addr in MEAR, MEMERR interrupt
202 */
203
204 int32 ReadQb (uint32 pa)
205 {
206 int32 idx, val;
207
208 idx = (pa & IOPAGEMASK) >> 1;
209 if (iodispR[idx]) {
210 iodispR[idx] (&val, pa, READ);
211 return val;
212 }
213 cq_merr (pa);
214 MACH_CHECK (MCHK_READ);
215 return 0;
216 }
217
218 void WriteQb (uint32 pa, int32 val, int32 mode)
219 {
220 int32 idx;
221
222 idx = (pa & IOPAGEMASK) >> 1;
223 if (iodispW[idx]) {
224 iodispW[idx] (val, pa, mode);
225 return;
226 }
227 cq_merr (pa);
228 mem_err = 1;
229 return;
230 }
231
232 /* ReadIO - read I/O space
233
234 Inputs:
235 pa = physical address
236 lnt = length (BWLQ)
237 Output:
238 longword of data
239 */
240
241 int32 ReadIO (uint32 pa, int32 lnt)
242 {
243 int32 iod;
244
245 iod = ReadQb (pa); /* wd from Qbus */
246 if (lnt < L_LONG) iod = iod << ((pa & 2)? 16: 0); /* bw? position */
247 else iod = (ReadQb (pa + 2) << 16) | iod; /* lw, get 2nd wd */
248 SET_IRQL;
249 return iod;
250 }
251
252 /* WriteIO - write I/O space
253
254 Inputs:
255 pa = physical address
256 val = data to write, right justified in 32b longword
257 lnt = length (BWLQ)
258 Outputs:
259 none
260 */
261
262 void WriteIO (uint32 pa, int32 val, int32 lnt)
263 {
264 if (lnt == L_BYTE) WriteQb (pa, val, WRITEB);
265 else if (lnt == L_WORD) WriteQb (pa, val, WRITE);
266 else {
267 WriteQb (pa, val & 0xFFFF, WRITE);
268 WriteQb (pa + 2, (val >> 16) & 0xFFFF, WRITE);
269 }
270 SET_IRQL;
271 return;
272 }
273
274 /* Find highest priority outstanding interrupt */
275
276 int32 eval_int (void)
277 {
278 int32 ipl = PSL_GETIPL (PSL);
279 int32 i, t;
280
281 static const int32 sw_int_mask[IPL_SMAX] = {
282 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */
283 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */
284 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */
285 0xE000, 0xC000, 0x8000 /* C - E */
286 };
287
288 if (hlt_pin) return IPL_HLTPIN; /* hlt pin int */
289 if ((ipl < IPL_MEMERR) && mem_err) return IPL_MEMERR; /* mem err int */
290 if ((ipl < IPL_CRDERR) && crd_err) return IPL_CRDERR; /* crd err int */
291 for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */
292 if (i <= ipl) return 0; /* at ipl? no int */
293 if (int_req[i - IPL_HMIN]) return i; /* req != 0? int */
294 }
295 if (ipl >= IPL_SMAX) return 0; /* ipl >= sw max? */
296 if ((t = SISR & sw_int_mask[ipl]) == 0) return 0; /* eligible req */
297 for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */
298 if ((t >> i) & 1) return i; /* req != 0? int */
299 }
300 return 0;
301 }
302
303 /* Return vector for highest priority hardware interrupt at IPL lvl */
304
305 int32 get_vector (int32 lvl)
306 {
307 int32 i;
308 int32 l = lvl - IPL_HMIN;
309
310 if (lvl == IPL_MEMERR) { /* mem error? */
311 mem_err = 0;
312 return SCB_MEMERR;
313 }
314 if (lvl == IPL_CRDERR) { /* CRD error? */
315 crd_err = 0;
316 return SCB_CRDERR;
317 }
318 if (lvl > IPL_HMAX) { /* error req lvl? */
319 ABORT (STOP_UIPL); /* unknown intr */
320 }
321 for (i = 0; int_req[l] && (i < 32); i++) {
322 if ((int_req[l] >> i) & 1) {
323 int_req[l] = int_req[l] & ~(1u << i);
324 if (int_ack[l][i]) return int_ack[l][i]();
325 return int_vec[l][i];
326 }
327 }
328 return 0;
329 }
330
331 /* CQBIC registers
332
333 SCR system configuration register
334 DSER DMA system error register (W1C)
335 MEAR master error address register (RO)
336 SEAR slave error address register (RO)
337 MBR map base register
338 IPC inter-processor communication register
339 */
340
341 int32 cqbic_rd (int32 pa)
342 {
343 int32 rg = (pa - CQBICBASE) >> 2;
344
345 switch (rg) {
346
347 case 0: /* SCR */
348 return (cq_scr | CQSCR_POK) & CQSCR_MASK;
349
350 case 1: /* DSER */
351 return cq_dser & CQDSER_MASK;
352
353 case 2: /* MEAR */
354 return cq_mear & CQMEAR_MASK;
355
356 case 3: /* SEAR */
357 return cq_sear & CQSEAR_MASK;
358
359 case 4: /* MBR */
360 return cq_mbr & CQMBR_MASK;
361 }
362
363 return 0;
364 }
365
366 void cqbic_wr (int32 pa, int32 val, int32 lnt)
367 {
368 int32 nval, rg = (pa - CQBICBASE) >> 2;
369
370 if (lnt < L_LONG) {
371 int32 sc = (pa & 3) << 3;
372 int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF;
373 int32 t = cqbic_rd (pa);
374 nval = ((val & mask) << sc) | (t & ~(mask << sc));
375 val = val << sc;
376 }
377 else nval = val;
378 switch (rg) {
379
380 case 0: /* SCR */
381 cq_scr = ((cq_scr & ~CQSCR_RW) | (nval & CQSCR_RW)) & CQSCR_MASK;
382 break;
383
384 case 1: /* DSER */
385 cq_dser = (cq_dser & ~val) & CQDSER_MASK;
386 if (val & CQDSER_SME) cq_ipc = cq_ipc & ~CQIPC_QME;
387 break;
388
389 case 2: case 3:
390 cq_merr (pa); /* MEAR, SEAR */
391 MACH_CHECK (MCHK_WRITE);
392 break;
393
394 case 4: /* MBR */
395 cq_mbr = nval & CQMBR_MASK;
396 break;
397 }
398 return;
399 }
400
401 /* IPC can be read as local register or as Qbus I/O
402 Because of the W1C */
403
404 int32 cqipc_rd (int32 pa)
405 {
406 return cq_ipc & CQIPC_MASK; /* IPC */
407 }
408
409 void cqipc_wr (int32 pa, int32 val, int32 lnt)
410 {
411 int32 nval = val;
412
413 if (lnt < L_LONG) {
414 int32 sc = (pa & 3) << 3;
415 nval = val << sc;
416 }
417
418 cq_ipc = cq_ipc & ~(nval & CQIPC_W1C); /* W1C */
419 if ((pa & 3) == 0) /* low byte only */
420 cq_ipc = ((cq_ipc & ~CQIPC_RW) | (val & CQIPC_RW)) & CQIPC_MASK;
421 return;
422 }
423
424 /* I/O page routines */
425
426 t_stat dbl_rd (int32 *data, int32 addr, int32 access)
427 {
428 *data = cq_ipc & CQIPC_MASK;
429 return SCPE_OK;
430 }
431
432 t_stat dbl_wr (int32 data, int32 addr, int32 access)
433 {
434 cqipc_wr (addr, data, (access == WRITEB)? L_BYTE: L_WORD);
435 return SCPE_OK;
436 }
437
438 /* CQBIC map read and write (reflects to main memory)
439
440 Read error: set DSER<0>, latch slave address, machine check
441 Write error: set DSER<0>, latch slave address, memory error interrupt
442 */
443
444 int32 cqmap_rd (int32 pa)
445 {
446 int32 ma = (pa & CQMAPAMASK) + cq_mbr; /* mem addr */
447
448 if (ADDR_IS_MEM (ma)) return M[ma >> 2];
449 cq_serr (ma); /* set err */
450 MACH_CHECK (MCHK_READ); /* mcheck */
451 return 0;
452 }
453
454 void cqmap_wr (int32 pa, int32 val, int32 lnt)
455 {
456 int32 ma = (pa & CQMAPAMASK) + cq_mbr; /* mem addr */
457
458 if (ADDR_IS_MEM (ma)) {
459 if (lnt < L_LONG) {
460 int32 sc = (pa & 3) << 3;
461 int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF;
462 int32 t = M[ma >> 2];
463 val = ((val & mask) << sc) | (t & ~(mask << sc));
464 }
465 M[ma >> 2] = val;
466 }
467 else {
468 cq_serr (ma); /* error */
469 mem_err = 1;
470 }
471 return;
472 }
473
474 /* CQBIC Qbus memory read and write (reflects to main memory)
475
476 May give master or slave error, depending on where the failure occurs
477 */
478
479 int32 cqmem_rd (int32 pa)
480 {
481 int32 qa = pa & CQMAMASK; /* Qbus addr */
482 uint32 ma;
483
484 if (qba_map_addr (qa, &ma)) return M[ma >> 2]; /* map addr */
485 MACH_CHECK (MCHK_READ); /* err? mcheck */
486 return 0;
487 }
488
489 void cqmem_wr (int32 pa, int32 val, int32 lnt)
490 {
491 int32 qa = pa & CQMAMASK; /* Qbus addr */
492 uint32 ma;
493
494 if (qba_map_addr (qa, &ma)) { /* map addr */
495 if (lnt < L_LONG) {
496 int32 sc = (pa & 3) << 3;
497 int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF;
498 int32 t = M[ma >> 2];
499 val = ((val & mask) << sc) | (t & ~(mask << sc));
500 }
501 M[ma >> 2] = val;
502 }
503 else mem_err = 1;
504 return;
505 }
506
507 /* Map an address via the translation map */
508
509 t_bool qba_map_addr (uint32 qa, uint32 *ma)
510 {
511 int32 qblk = (qa >> VA_V_VPN); /* Qbus blk */
512 int32 qmma = ((qblk << 2) & CQMAPAMASK) + cq_mbr; /* map entry */
513
514 if (ADDR_IS_MEM (qmma)) { /* legit? */
515 int32 qmap = M[qmma >> 2]; /* get map */
516 if (qmap & CQMAP_VLD) { /* valid? */
517 *ma = ((qmap & CQMAP_PAG) << VA_V_VPN) + VA_GETOFF (qa);
518 if (ADDR_IS_MEM (*ma)) return TRUE; /* legit addr */
519 cq_serr (*ma); /* slave nxm */
520 return FALSE;
521 }
522 cq_merr (qa); /* master nxm */
523 return FALSE;
524 }
525 cq_serr (0); /* inv mem */
526 return FALSE;
527 }
528
529 /* Map an address via the translation map - console version (no status changes) */
530
531 t_bool qba_map_addr_c (uint32 qa, uint32 *ma)
532 {
533 int32 qblk = (qa >> VA_V_VPN); /* Qbus blk */
534 int32 qmma = ((qblk << 2) & CQMAPAMASK) + cq_mbr; /* map entry */
535
536 if (ADDR_IS_MEM (qmma)) { /* legit? */
537 int32 qmap = M[qmma >> 2]; /* get map */
538 if (qmap & CQMAP_VLD) { /* valid? */
539 *ma = ((qmap & CQMAP_PAG) << VA_V_VPN) + VA_GETOFF (qa);
540 return TRUE; /* legit addr */
541 }
542 }
543 return FALSE;
544 }
545
546 /* Set master error */
547
548 void cq_merr (int32 pa)
549 {
550 if (cq_dser & CQDSER_ERR) cq_dser = cq_dser | CQDSER_LST;
551 cq_dser = cq_dser | CQDSER_MNX; /* master nxm */
552 cq_mear = (pa >> VA_V_VPN) & CQMEAR_MASK; /* page addr */
553 return;
554 }
555
556 /* Set slave error */
557
558 void cq_serr (int32 pa)
559 {
560 if (cq_dser & CQDSER_ERR) cq_dser = cq_dser | CQDSER_LST;
561 cq_dser = cq_dser | CQDSER_SNX; /* slave nxm */
562 cq_sear = (pa >> VA_V_VPN) & CQSEAR_MASK;
563 return;
564 }
565
566 /* Reset I/O bus */
567
568 void ioreset_wr (int32 data)
569 {
570 reset_all (5); /* from qba on... */
571 return;
572 }
573
574 /* Powerup CQBIC */
575
576 t_stat qba_powerup (void)
577 {
578 cq_mbr = 0;
579 cq_scr = CQSCR_POK;
580 return SCPE_OK;
581 }
582
583 /* Reset CQBIC */
584
585 t_stat qba_reset (DEVICE *dptr)
586 {
587 int32 i;
588
589 if (sim_switches & SWMASK ('P')) qba_powerup ();
590 cq_scr = (cq_scr & CQSCR_BHL) | CQSCR_POK;
591 cq_dser = cq_mear = cq_sear = cq_ipc = 0;
592 for (i = 0; i < IPL_HLVL; i++) int_req[i] = 0;
593 return SCPE_OK;
594 }
595
596 /* Qbus I/O buffer routines, aligned access
597
598 Map_ReadB - fetch byte buffer from memory
599 Map_ReadW - fetch word buffer from memory
600 Map_WriteB - store byte buffer into memory
601 Map_WriteW - store word buffer into memory
602 */
603
604 int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf)
605 {
606 int32 i;
607 uint32 ma, dat;
608
609 if ((ba | bc) & 03) { /* check alignment */
610 for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */
611 if ((ma & VA_M_OFF) == 0) { /* need map? */
612 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
613 return (bc - i);
614 }
615 *buf = ReadB (ma);
616 ma = ma + 1;
617 }
618 }
619 else {
620 for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
621 if ((ma & VA_M_OFF) == 0) { /* need map? */
622 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
623 return (bc - i);
624 }
625 dat = ReadL (ma); /* get lw */
626 *buf++ = dat & BMASK; /* low 8b */
627 *buf++ = (dat >> 8) & BMASK; /* next 8b */
628 *buf++ = (dat >> 16) & BMASK; /* next 8b */
629 *buf = (dat >> 24) & BMASK;
630 ma = ma + 4;
631 }
632 }
633 return 0;
634 }
635
636 int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf)
637 {
638 int32 i;
639 uint32 ma,dat;
640
641 ba = ba & ~01;
642 bc = bc & ~01;
643 if ((ba | bc) & 03) { /* check alignment */
644 for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */
645 if ((ma & VA_M_OFF) == 0) { /* need map? */
646 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
647 return (bc - i);
648 }
649 *buf = ReadW (ma);
650 ma = ma + 2;
651 }
652 }
653 else {
654 for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
655 if ((ma & VA_M_OFF) == 0) { /* need map? */
656 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
657 return (bc - i);
658 }
659 dat = ReadL (ma); /* get lw */
660 *buf++ = dat & WMASK; /* low 16b */
661 *buf = (dat >> 16) & WMASK; /* high 16b */
662 ma = ma + 4;
663 }
664 }
665 return 0;
666 }
667
668 int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf)
669 {
670 int32 i;
671 uint32 ma, dat;
672
673 if ((ba | bc) & 03) { /* check alignment */
674 for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */
675 if ((ma & VA_M_OFF) == 0) { /* need map? */
676 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
677 return (bc - i);
678 }
679 WriteB (ma, *buf);
680 ma = ma + 1;
681 }
682 }
683 else {
684 for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
685 if ((ma & VA_M_OFF) == 0) { /* need map? */
686 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
687 return (bc - i);
688 }
689 dat = (uint32) *buf++; /* get low 8b */
690 dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */
691 dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */
692 dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */
693 WriteL (ma, dat); /* store lw */
694 ma = ma + 4;
695 }
696 }
697 return 0;
698 }
699
700 int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf)
701 {
702 int32 i;
703 uint32 ma, dat;
704
705 ba = ba & ~01;
706 bc = bc & ~01;
707 if ((ba | bc) & 03) { /* check alignment */
708 for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */
709 if ((ma & VA_M_OFF) == 0) { /* need map? */
710 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
711 return (bc - i);
712 }
713 WriteW (ma, *buf);
714 ma = ma + 2;
715 }
716 }
717 else {
718 for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */
719 if ((ma & VA_M_OFF) == 0) { /* need map? */
720 if (!qba_map_addr (ba + i, &ma)) /* inv or NXM? */
721 return (bc - i);
722 }
723 dat = (uint32) *buf++; /* get low 16b */
724 dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */
725 WriteL (ma, dat); /* store lw */
726 ma = ma + 4;
727 }
728 }
729 return 0;
730 }
731
732 /* Memory examine via map (word only) */
733
734 t_stat qba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
735 {
736 uint32 qa = (uint32) exta, pa;
737
738 if ((vptr == NULL) || (qa >= CQMSIZE)) return SCPE_ARG;
739 if (qba_map_addr_c (qa, &pa) && ADDR_IS_MEM (pa)) {
740 *vptr = (uint32) ReadW (pa);
741 return SCPE_OK;
742 }
743 return SCPE_NXM;
744 }
745
746 /* Memory deposit via map (word only) */
747
748 t_stat qba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
749 {
750 uint32 qa = (uint32) exta, pa;
751
752 if (qa >= CQMSIZE) return SCPE_ARG;
753 if (qba_map_addr_c (qa, &pa) && ADDR_IS_MEM (pa)) {
754 WriteW (pa, (int32) val);
755 return SCPE_OK;
756 }
757 return SCPE_NXM;
758 }
759
760 /* Enable/disable autoconfiguration */
761
762 t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc)
763 {
764 if (cptr != NULL) return SCPE_ARG;
765 autcon_enb = val;
766 return auto_config (NULL, 0);
767 }
768
769 /* Show autoconfiguration status */
770
771 t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc)
772 {
773 fprintf (st, "autoconfiguration ");
774 fprintf (st, autcon_enb? "enabled": "disabled");
775 return SCPE_OK;
776 }
777
778 /* Change device address */
779
780 t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc)
781 {
782 DEVICE *dptr;
783 DIB *dibp;
784 uint32 newba;
785 t_stat r;
786
787 if (cptr == NULL) return SCPE_ARG;
788 if ((val == 0) || (uptr == NULL)) return SCPE_IERR;
789 dptr = find_dev_from_unit (uptr);
790 if (dptr == NULL) return SCPE_IERR;
791 dibp = (DIB *) dptr->ctxt;
792 if (dibp == NULL) return SCPE_IERR;
793 newba = (uint32) get_uint (cptr, 16, IOPAGEBASE+IOPAGEMASK, &r); /* get new */
794 if (r != SCPE_OK) return r;
795 if ((newba <= IOPAGEBASE) || /* must be > 0 */
796 (newba % ((uint32) val))) return SCPE_ARG; /* check modulus */
797 dibp->ba = newba; /* store */
798 dptr->flags = dptr->flags & ~DEV_FLTA; /* not floating */
799 autcon_enb = 0; /* autoconfig off */
800 return SCPE_OK;
801 }
802
803 /* Show device address */
804
805 t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc)
806 {
807 DEVICE *dptr;
808 DIB *dibp;
809
810 if (uptr == NULL) return SCPE_IERR;
811 dptr = find_dev_from_unit (uptr);
812 if (dptr == NULL) return SCPE_IERR;
813 dibp = (DIB *) dptr->ctxt;
814 if ((dibp == NULL) || (dibp->ba <= IOPAGEBASE)) return SCPE_IERR;
815 fprintf (st, "address=%08X", dibp->ba);
816 if (dibp->lnt > 1)
817 fprintf (st, "-%08X", dibp->ba + dibp->lnt - 1);
818 if (dptr->flags & DEV_FLTA) fprintf (st, "*");
819 return SCPE_OK;
820 }
821
822 /* Set address floating */
823
824 t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc)
825 {
826 DEVICE *dptr;
827
828 if (cptr == NULL) return SCPE_ARG;
829 if ((val == 0) || (uptr == NULL)) return SCPE_IERR;
830 dptr = find_dev_from_unit (uptr);
831 if (dptr == NULL) return SCPE_IERR;
832 dptr->flags = dptr->flags | DEV_FLTA; /* floating */
833 return auto_config (NULL, 0); /* autoconfigure */
834 }
835
836 /* Change device vector */
837
838 t_stat set_vec (UNIT *uptr, int32 arg, char *cptr, void *desc)
839 {
840 DEVICE *dptr;
841 DIB *dibp;
842 uint32 newvec;
843 t_stat r;
844
845 if (cptr == NULL) return SCPE_ARG;
846 if (uptr == NULL) return SCPE_IERR;
847 dptr = find_dev_from_unit (uptr);
848 if (dptr == NULL) return SCPE_IERR;
849 dibp = (DIB *) dptr->ctxt;
850 if (dibp == NULL) return SCPE_IERR;
851 newvec = (uint32) get_uint (cptr, 16, VEC_Q + 01000, &r);
852 if ((r != SCPE_OK) || (newvec <= VEC_Q) ||
853 ((newvec + (dibp->vnum * 4)) >= (VEC_Q + 01000)) ||
854 (newvec & ((dibp->vnum > 1)? 07: 03))) return SCPE_ARG;
855 dibp->vec = newvec;
856 dptr->flags = dptr->flags & ~DEV_FLTA; /* not floating */
857 autcon_enb = 0; /* autoconfig off */
858 return SCPE_OK;
859 }
860
861 /* Show device vector */
862
863 t_stat show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc)
864 {
865 DEVICE *dptr;
866 DIB *dibp;
867 uint32 vec, numvec;
868
869 if (uptr == NULL) return SCPE_IERR;
870 dptr = find_dev_from_unit (uptr);
871 if (dptr == NULL) return SCPE_IERR;
872 dibp = (DIB *) dptr->ctxt;
873 if (dibp == NULL) return SCPE_IERR;
874 vec = dibp->vec;
875 if (arg) numvec = arg;
876 else numvec = dibp->vnum;
877 if (vec == 0) fprintf (st, "no vector");
878 else {
879 fprintf (st, "vector=%X", vec);
880 if (numvec > 1) fprintf (st, "-%X", vec + (4 * (numvec - 1)));
881 }
882 return SCPE_OK;
883 }
884
885 /* Build dispatch tables */
886
887 t_stat build_dsp_tab (DEVICE *dptr, DIB *dibp)
888 {
889 uint32 i, idx;
890
891 if ((dptr == NULL) || (dibp == NULL)) return SCPE_IERR; /* validate args */
892 for (i = 0; i < dibp->lnt; i = i + 2) { /* create entries */
893 idx = ((dibp->ba + i) & IOPAGEMASK) >> 1; /* index into disp */
894 if ((iodispR[idx] && dibp->rd && /* conflict? */
895 (iodispR[idx] != dibp->rd)) ||
896 (iodispW[idx] && dibp->wr &&
897 (iodispW[idx] != dibp->wr))) {
898 printf ("Device %s address conflict at %08o\n",
899 sim_dname (dptr), dibp->ba);
900 if (sim_log) fprintf (sim_log,
901 "Device %s address conflict at %08o\n",
902 sim_dname (dptr), dibp->ba);
903 return SCPE_STOP;
904 }
905 if (dibp->rd) iodispR[idx] = dibp->rd; /* set rd dispatch */
906 if (dibp->wr) iodispW[idx] = dibp->wr; /* set wr dispatch */
907 iodibp[idx] = dibp; /* remember DIB */
908 }
909 return SCPE_OK;
910 }
911
912
913 /* Build interrupt tables */
914
915 t_stat build_int_vec (DEVICE *dptr, DIB *dibp)
916 {
917 int32 i, idx, vec, ilvl, ibit;
918
919 if ((dptr == NULL) || (dibp == NULL)) return SCPE_IERR; /* validate args */
920 if (dibp->vnum > VEC_DEVMAX) return SCPE_IERR;
921 for (i = 0; i < dibp->vnum; i++) { /* loop thru vec */
922 idx = dibp->vloc + i; /* vector index */
923 vec = dibp->vec? (dibp->vec + (i * 4)): 0; /* vector addr */
924 ilvl = idx / 32;
925 ibit = idx % 32;
926 if ((int_ack[ilvl][ibit] && dibp->ack[i] && /* conflict? */
927 (int_ack[ilvl][ibit] != dibp->ack[i])) ||
928 (int_vec[ilvl][ibit] && vec &&
929 (int_vec[ilvl][ibit] != vec))) {
930 printf ("Device %s interrupt slot conflict at %d\n",
931 sim_dname (dptr), idx);
932 if (sim_log) fprintf (sim_log,
933 "Device %s interrupt slot conflict at %d\n",
934 sim_dname (dptr), idx);
935 return SCPE_STOP;
936 }
937 if (dibp->ack[i]) int_ack[ilvl][ibit] = dibp->ack[i];
938 else if (vec) int_vec[ilvl][ibit] = vec;
939 }
940 return SCPE_OK;
941 }
942
943 /* Build dib_tab from device list */
944
945 t_stat build_dib_tab (void)
946 {
947 int32 i, j;
948 DEVICE *dptr;
949 DIB *dibp;
950 t_stat r;
951
952 for (i = 0; i < IPL_HLVL; i++) { /* clear int tables */
953 for (j = 0; j < 32; j++) {
954 int_vec[i][j] = 0;
955 int_ack[i][j] = NULL;
956 }
957 }
958 for (i = 0; i < (IOPAGESIZE >> 1); i++) { /* clear dispatch tab */
959 iodispR[i] = NULL;
960 iodispW[i] = NULL;
961 iodibp[i] = NULL;
962 }
963 for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
964 dibp = (DIB *) dptr->ctxt; /* get DIB */
965 if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
966 if (r = build_int_vec (dptr, dibp)) /* add to intr tab */
967 return r;
968 if (r = build_dsp_tab (dptr, dibp)) /* add to dispatch tab */
969 return r;
970 } /* end if enabled */
971 } /* end for */
972 return SCPE_OK;
973 }
974
975 /* Show IO space */
976
977 t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc)
978 {
979 uint32 i, j;
980 DEVICE *dptr;
981 DIB *dibp;
982
983 if (build_dib_tab ()) return SCPE_OK; /* build IO page */
984 for (i = 0, dibp = NULL; i < (IOPAGESIZE >> 1); i++) { /* loop thru entries */
985 if (iodibp[i] && (iodibp[i] != dibp)) { /* new block? */
986 dibp = iodibp[i]; /* DIB for block */
987 for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
988 if (((DIB*) sim_devices[j]->ctxt) == dibp) {
989 dptr = sim_devices[j]; /* locate device */
990 break;
991 } /* end if */
992 } /* end for j */
993 fprintf (st, "%08X - %08X%c\t%s\n", dibp->ba,
994 dibp->ba + dibp->lnt - 1,
995 (dptr && (dptr->flags & DEV_FLTA))? '*': ' ',
996 dptr? sim_dname (dptr): "CPU");
997 } /* end if */
998 } /* end for i */
999 return SCPE_OK;
1000 }
1001
1002 /* Show QBA virtual address */
1003
1004 t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc)
1005 {
1006 t_stat r;
1007 char *cptr = (char *) desc;
1008 uint32 qa, pa;
1009
1010 if (cptr) {
1011 qa = (uint32) get_uint (cptr, 16, CQMSIZE - 1, &r);
1012 if (r == SCPE_OK) {
1013 if (qba_map_addr_c (qa, &pa))
1014 fprintf (of, "Qbus %-X = physical %-X\n", qa, pa);
1015 else fprintf (of, "Qbus %-X: invalid mapping\n", qa);
1016 return SCPE_OK;
1017 }
1018 }
1019 fprintf (of, "Invalid argument\n");
1020 return SCPE_OK;
1021 }
1022
1023 /* Autoconfiguration
1024
1025 The table reflects the MicroVAX 3900 microcode, with one addition - the
1026 number of controllers field handles devices where multiple instances
1027 are simulated through a single DEVICE structure (e.g., DZ, VH).
1028
1029 A minus number of vectors indicates a field that should be calculated
1030 but not placed in the DIB (RQ, TQ dynamic vectors) */
1031
1032 #define AUTO_MAXC 4
1033 #define AUTO_CSRBASE 0010
1034 #define AUTO_VECBASE 0300
1035
1036 typedef struct {
1037 char *dnam[AUTO_MAXC];
1038 int32 numc;
1039 int32 numv;
1040 uint32 amod;
1041 uint32 vmod;
1042 uint32 fixa[AUTO_MAXC];
1043 uint32 fixv[AUTO_MAXC];
1044 } AUTO_CON;
1045
1046 AUTO_CON auto_tab[] = {
1047 { { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */
1048 { { NULL }, 1, 2, 8, 8 }, /* DJ11 */
1049 { { NULL }, 1, 2, 16, 8 }, /* DH11 */
1050 { { NULL }, 1, 2, 8, 8 }, /* DQ11 */
1051 { { NULL }, 1, 2, 8, 8 }, /* DU11 */
1052 { { NULL }, 1, 2, 8, 8 }, /* DUP11 */
1053 { { NULL }, 10, 2, 8, 8 }, /* LK11A */
1054 { { NULL }, 1, 2, 8, 8 }, /* DMC11 */
1055 { { "DZ" }, DZ_MUXES, 2, 8, 8 }, /* DZ11 */
1056 { { NULL }, 1, 2, 8, 8 }, /* KMC11 */
1057 { { NULL }, 1, 2, 8, 8 }, /* LPP11 */
1058 { { NULL }, 1, 2, 8, 8 }, /* VMV21 */
1059 { { NULL }, 1, 2, 16, 8 }, /* VMV31 */
1060 { { NULL }, 1, 2, 8, 8 }, /* DWR70 */
1061 { { "RL", "RLB" }, 1, 1, 8, 4, {IOBA_RL}, {VEC_RL} }, /* RL11 */
1062 { { "TS", "TSB", "TSC", "TSD" }, 1, 1, 0, 4, /* TS11 */
1063 {IOBA_TS, IOBA_TS + 4, IOBA_TS + 8, IOBA_TS + 12},
1064 {VEC_TS} },
1065 { { NULL }, 1, 2, 16, 8 }, /* LPA11K */
1066 { { NULL }, 1, 2, 8, 8 }, /* KW11C */
1067 { { NULL }, 1, 1, 8, 8 }, /* reserved */
1068 { { "RX", "RY" }, 1, 1, 8, 4, {IOBA_RX} , {VEC_RX} }, /* RX11/RX211 */
1069 { { NULL }, 1, 1, 8, 4 }, /* DR11W */
1070 { { NULL }, 1, 1, 8, 4, { 0, 0 }, { 0 } }, /* DR11B - fx CSRs,vec */
1071 { { NULL }, 1, 2, 8, 8 }, /* DMP11 */
1072 { { NULL }, 1, 2, 8, 8 }, /* DPV11 */
1073 { { NULL }, 1, 2, 8, 8 }, /* ISB11 */
1074 { { NULL }, 1, 2, 16, 8 }, /* DMV11 */
1075 { { "XU", "XUB" }, 1, 1, 8, 4, {IOBA_XU}, {VEC_XU} }, /* DEUNA */
1076 { { "XQ", "XQB" }, 1, 1, 0, 4, /* DEQNA */
1077 {IOBA_XQ,IOBA_XQB}, {VEC_XQ} },
1078 { { "RQ", "RQB", "RQC", "RQD" }, 1, -1, 4, 4, /* RQDX3 */
1079 {IOBA_RQ}, {VEC_RQ} },
1080 { { NULL }, 1, 8, 32, 4 }, /* DMF32 */
1081 { { NULL }, 1, 2, 16, 8 }, /* KMS11 */
1082 { { NULL }, 1, 1, 16, 4 }, /* VS100 */
1083 { { "TQ", "TQB" }, 1, -1, 4, 4, {IOBA_TQ}, {VEC_TQ} }, /* TQK50 */
1084 { { NULL }, 1, 2, 16, 8 }, /* KMV11 */
1085 { { "VH" }, VH_MUXES, 2, 16, 8 }, /* DHU11/DHQ11 */
1086 { { NULL }, 1, 6, 32, 4 }, /* DMZ32 */
1087 { { NULL }, 1, 6, 32, 4 }, /* CP132 */
1088 { { NULL }, 1, 2, 64, 8, { 0 } }, /* QVSS - fx CSR */
1089 { { NULL }, 1, 1, 8, 4 }, /* VS31 */
1090 { { NULL }, 1, 1, 0, 4, { 0 } }, /* LNV11 - fx CSR */
1091 { { NULL }, 1, 1, 16, 4 }, /* LNV21/QPSS */
1092 { { NULL }, 1, 1, 8, 4, { 0 } }, /* QTA - fx CSR */
1093 { { NULL }, 1, 1, 8, 4 }, /* DSV11 */
1094 { { NULL }, 1, 2, 8, 8 }, /* CSAM */
1095 { { NULL }, 1, 2, 8, 8 }, /* ADV11C */
1096 { { NULL }, 1, 0, 8, 0 }, /* AAV11C */
1097 { { NULL }, 1, 2, 8, 8, { 0 }, { 0 } }, /* AXV11C - fx CSR,vec */
1098 { { NULL }, 1, 2, 4, 8, { 0 } }, /* KWV11C - fx CSR */
1099 { { NULL }, 1, 2, 8, 8, { 0 } }, /* ADV11D - fx CSR */
1100 { { NULL }, 1, 2, 8, 8, { 0 } }, /* AAV11D - fx CSR */
1101 { { "QDSS" }, 1, 3, 0, 16, {IOBA_QDSS} }, /* QDSS - fx CSR */
1102 { { NULL }, -1 } /* end table */
1103 };
1104
1105 t_stat auto_config (char *name, int32 nctrl)
1106 {
1107 uint32 csr = IOPAGEBASE + AUTO_CSRBASE;
1108 uint32 vec = VEC_Q + AUTO_VECBASE;
1109 AUTO_CON *autp;
1110 DEVICE *dptr;
1111 DIB *dibp;
1112 uint32 j, k, vmask, amask;
1113
1114 if (autcon_enb == 0) return SCPE_OK; /* enabled? */
1115 if (name) { /* updating? */
1116 if (nctrl < 0) return SCPE_ARG;
1117 for (autp = auto_tab; autp->numc >= 0; autp++) {
1118 for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
1119 if (strcmp (name, autp->dnam[j]) == 0)
1120 autp->numc = nctrl;
1121 }
1122 }
1123 }
1124 for (autp = auto_tab; autp->numc >= 0; autp++) { /* loop thru table */
1125 if (autp->amod) { /* floating csr? */
1126 amask = autp->amod - 1;
1127 csr = (csr + amask) & ~amask; /* align csr */
1128 }
1129 for (j = k = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
1130 dptr = find_dev (autp->dnam[j]); /* find ctrl */
1131 if ((dptr == NULL) || (dptr->flags & DEV_DIS) ||
1132 !(dptr->flags & DEV_FLTA)) continue; /* enabled, floating? */
1133 dibp = (DIB *) dptr->ctxt; /* get DIB */
1134 if (dibp == NULL) return SCPE_IERR; /* not there??? */
1135 if (autp->amod) { /* dyn csr needed? */
1136 if (autp->fixa[k]) /* fixed csr avail? */
1137 dibp->ba = autp->fixa[k]; /* use it */
1138 else { /* no fixed left */
1139 dibp->ba = csr; /* set CSR */
1140 csr += (autp->numc * autp->amod); /* next CSR */
1141 } /* end else */
1142 } /* end if dyn csr */
1143 if (autp->numv && autp->vmod) { /* dyn vec needed? */
1144 uint32 numv = abs (autp->numv); /* get num vec */
1145 if (autp->fixv[k]) { /* fixed vec avail? */
1146 if (autp->numv > 0)
1147 dibp->vec = autp->fixv[k]; /* use it */
1148 }
1149 else { /* no fixed left */
1150 vmask = autp->vmod - 1;
1151 vec = (vec + vmask) & ~vmask; /* align vector */
1152 if (autp->numv > 0)
1153 dibp->vec = vec; /* set vector */
1154 vec += (autp->numc * numv * 4);
1155 } /* end else */
1156 } /* end if dyn vec */
1157 k++; /* next instance */
1158 } /* end for j */
1159 if (autp->amod) csr = csr + 2; /* flt CSR? gap */
1160 } /* end for i */
1161 return SCPE_OK;
1162 }
Magically enhanced SIMH