VAX/vaxmod_defs.h

   1 /* vaxmod_defs.h: VAX model-specific definitions file
   2
   3    Copyright (c) 1998-2007, Robert M Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    29-Apr-07    RMS     Separated checks for PxBR and SBR
  27    17-May-06    RMS     Added CR11/CD11 support
  28    10-May-06    RMS     Added NOP'd reserved operand checking macros
  29    05-Oct-05    RMS     Added XU definitions for autoconfigure
  30    15-Jun-05    RMS     Added QDSS support
  31    12-Sep-04    RMS     Removed map_address prototype
  32    16-Jun-04    RMS     Added DHQ11 support
  33    21-Mar-04    RMS     Added RXV21 support
  34    25-Jan-04    RMS     Removed local debug logging support
  35                 RMS,MP  Added "KA655X" support
  36    29-Dec-03    RMS     Added Q18 definition for PDP11 compatibility
  37    22-Dec-02    RMS     Added BDR halt enable definition
  38    11-Nov-02    RMS     Added log bits for XQ
  39    10-Oct-02    RMS     Added DEQNA/DELQA, multiple RQ, autoconfigure support
  40    29-Sep-02    RMS     Revamped bus support macros
  41    06-Sep-02    RMS     Added TMSCP support
  42    14-Jul-02    RMS     Added additional console halt codes
  43    28-Apr-02    RMS     Fixed DZV vector base and number of lines
  44
  45    This file covers the KA65x ("Mayfair") series of CVAX-based Qbus systems.
  46    The simulator defines an extended physical memory variant of the KA655,
  47    called the KA655X.  It has a maximum memory size of 512MB instead of 64MB.
  48
  49    System memory map
  50
  51         0000 0000 - 03FF FFFF           main memory (KA655)
  52         0400 0000 - 0FFF FFFF           reserved (KA655), main memory (KA655X)
  53         1000 0000 - 13FF FFFF           cache diagnostic space (KA655), main memory (KA655X)
  54         1400 0000 - 1FFF FFFF           reserved (KA655), main memory (KA655X)
  55
  56         2000 0000 - 2000 1FFF           Qbus I/O page
  57         2000 2000 - 2003 FFFF           reserved
  58         2004 0000 - 2005 FFFF           ROM space, halt protected
  59         2006 0000 - 2007 FFFF           ROM space, halt unprotected
  60         2008 0000 - 201F FFFF           Local register space
  61         2020 0000 - 2FFF FFFF           reserved
  62         3000 0000 - 303F FFFF           Qbus memory space
  63         3400 0000 - 3FFF FFFF           reserved
  64 */
  65
  66 #ifdef FULL_VAX                                         /* subset VAX */
  67 #undef FULL_VAX
  68 #endif
  69
  70 #ifndef _VAXMOD_DEFS_H_
  71 #define _VAXMOD_DEFS_H_ 1
  72
  73 /* Microcode constructs */
  74
  75 #define CVAX_SID        (10 << 24)                      /* system ID */
  76 #define CVAX_UREV       6                               /* ucode revision */
  77 #define CON_HLTPIN      0x0200                          /* external CPU halt */
  78 #define CON_PWRUP       0x0300                          /* powerup code */
  79 #define CON_HLTINS      0x0600                          /* HALT instruction */
  80 #define CON_BADPSL      0x4000                          /* invalid PSL flag */
  81 #define CON_MAPON       0x8000                          /* mapping on flag */
  82 #define MCHK_TBM_P0     0x05                            /* PPTE in P0 */
  83 #define MCHK_TBM_P1     0x06                            /* PPTE in P1 */
  84 #define MCHK_M0_P0      0x07                            /* PPTE in P0 */
  85 #define MCHK_M0_P1      0x08                            /* PPTE in P1 */
  86 #define MCHK_INTIPL     0x09                            /* invalid ireq */
  87 #define MCHK_READ       0x80                            /* read check */
  88 #define MCHK_WRITE      0x82                            /* write check */
  89
  90 /* Machine specific IPRs */
  91
  92 #define MT_CADR         37
  93 #define MT_MSER         39
  94 #define MT_CONPC        42
  95 #define MT_CONPSL       43
  96 #define MT_IORESET      55
  97
  98 /* Memory system error register */
  99
 100 #define MSER_HM         0x80                            /* hit/miss */
 101 #define MSER_CPE        0x40                            /* CDAL par err */
 102 #define MSER_CPM        0x20                            /* CDAL mchk */
 103
 104 /* Cache disable register */
 105
 106 #define CADR_RW         0xF3
 107 #define CADR_MBO        0x0C
 108
 109 /* Memory */
 110
 111 #define MAXMEMWIDTH     26                              /* max mem, std KA655 */
 112 #define MAXMEMSIZE      (1 << MAXMEMWIDTH)              /* max mem size */
 113 #define MAXMEMWIDTH_X   29                              /* max mem, KA655X */
 114 #define MAXMEMSIZE_X    (1 << MAXMEMWIDTH_X)
 115 #define INITMEMSIZE     (1 << 24)                       /* initial memory size */
 116 #define MEMSIZE         (cpu_unit.capac)
 117 #define ADDR_IS_MEM(x)  (((uint32) (x)) < MEMSIZE)
 118
 119 /* Cache diagnostic space */
 120
 121 #define CDAAWIDTH       16                              /* cache dat addr width */
 122 #define CDASIZE         (1u << CDAAWIDTH)               /* cache dat length */
 123 #define CDAMASK         (CDASIZE - 1)                   /* cache dat mask */
 124 #define CTGAWIDTH       10                              /* cache tag addr width */
 125 #define CTGSIZE         (1u << CTGAWIDTH)               /* cache tag length */
 126 #define CTGMASK         (CTGSIZE - 1)                   /* cache tag mask */
 127 #define CDGSIZE         (CDASIZE * CTGSIZE)             /* diag addr length */
 128 #define CDGBASE         0x10000000                      /* diag addr base */
 129 #define CDG_GETROW(x)   (((x) & CDAMASK) >> 2)
 130 #define CDG_GETTAG(x)   (((x) >> CDAAWIDTH) & CTGMASK)
 131 #define CTG_V           (1u << (CTGAWIDTH + 0))         /* tag valid */
 132 #define CTG_WP          (1u << (CTGAWIDTH + 1))         /* wrong parity */
 133 #define ADDR_IS_CDG(x)  ((((uint32) (x)) >= CDGBASE) && \
 134                         (((uint32) (x)) < (CDGBASE + CDGSIZE)))
 135
 136 /* Qbus I/O registers */
 137
 138 #define IOPAGEAWIDTH    13                              /* IO addr width */
 139 #define IOPAGESIZE      (1u << IOPAGEAWIDTH)            /* IO page length */
 140 #define IOPAGEMASK      (IOPAGESIZE - 1)                /* IO addr mask */
 141 #define IOPAGEBASE      0x20000000                      /* IO page base */
 142 #define ADDR_IS_IO(x)   ((((uint32) (x)) >= IOPAGEBASE) && \
 143                         (((uint32) (x)) < (IOPAGEBASE + IOPAGESIZE)))
 144
 145 /* Read only memory - appears twice */
 146
 147 #define ROMAWIDTH       17                              /* ROM addr width */
 148 #define ROMSIZE         (1u << ROMAWIDTH)               /* ROM length */
 149 #define ROMAMASK        (ROMSIZE - 1)                   /* ROM addr mask */
 150 #define ROMBASE         0x20040000                      /* ROM base */
 151 #define ADDR_IS_ROM(x)  ((((uint32) (x)) >= ROMBASE) && \
 152                         (((uint32) (x)) < (ROMBASE + ROMSIZE + ROMSIZE)))
 153
 154 /* Local register space */
 155
 156 #define REGAWIDTH       19                              /* REG addr width */
 157 #define REGSIZE         (1u << REGAWIDTH)               /* REG length */
 158 #define REGBASE         0x20080000                      /* REG addr base */
 159
 160 /* KA655 board registers */
 161
 162 #define KAAWIDTH        3                               /* KA reg width */
 163 #define KASIZE          (1u << KAAWIDTH)                /* KA reg length */
 164 #define KABASE          (REGBASE + 0x4000)              /* KA650 addr base */
 165
 166 /* CQBIC registers */
 167
 168 #define CQBICSIZE       (5 << 2)                        /* 5 registers */
 169 #define CQBICBASE       (REGBASE)                       /* CQBIC addr base */
 170 #define CQMAPASIZE      15                              /* map addr width */
 171 #define CQMAPSIZE       (1u << CQMAPASIZE)              /* map length */
 172 #define CQMAPAMASK      (CQMAPSIZE - 1)                 /* map addr mask */
 173 #define CQMAPBASE       (REGBASE + 0x8000)              /* map addr base */
 174 #define CQIPCSIZE       2                               /* 2 bytes only */
 175 #define CQIPCBASE       (REGBASE + 0x1F40)              /* ipc reg addr */
 176
 177 /* CMCTL registers */
 178
 179 /* #define CMCTLSIZE    (18 << 2)                       /* 18 registers */
 180 #define CMCTLSIZE       (19 << 2)                       /* KA655X extra reg */
 181 #define CMCTLBASE       (REGBASE + 0x100)               /* CMCTL addr base */
 182
 183 /* SSC registers */
 184
 185 #define SSCSIZE         0x150                           /* SSC size */
 186 #define SSCBASE         0x20140000                      /* SSC base */
 187
 188 /* Non-volatile RAM - 1KB long */
 189
 190 #define NVRAWIDTH       10                              /* NVR addr width */
 191 #define NVRSIZE         (1u << NVRAWIDTH)               /* NVR length */
 192 #define NVRAMASK        (NVRSIZE - 1)                   /* NVR addr mask */
 193 #define NVRBASE         0x20140400                      /* NVR base */
 194 #define ADDR_IS_NVR(x)  ((((uint32) (x)) >= NVRBASE) && \
 195                         (((uint32) (x)) < (NVRBASE + NVRSIZE)))
 196
 197 /* CQBIC Qbus memory space (seen from CVAX) */
 198
 199 #define CQMAWIDTH       22                              /* Qmem addr width */
 200 #define CQMSIZE         (1u << CQMAWIDTH)               /* Qmem length */
 201 #define CQMAMASK        (CQMSIZE - 1)                   /* Qmem addr mask */
 202 #define CQMBASE         0x30000000                      /* Qmem base */
 203
 204 /* Machine specific reserved operand tests (all NOPs) */
 205
 206 #define ML_PA_TEST(r)
 207 #define ML_LR_TEST(r)
 208 #define ML_SBR_TEST(r)
 209 #define ML_PXBR_TEST(r)
 210 #define LP_AST_TEST(r)
 211 #define LP_MBZ84_TEST(r)
 212 #define LP_MBZ92_TEST(r)
 213
 214 /* Qbus I/O modes */
 215
 216 #define READ            0                               /* PDP-11 compatibility */
 217 #define WRITE           (L_WORD)
 218 #define WRITEB          (L_BYTE)
 219
 220 /* Common CSI flags */
 221
 222 #define CSR_V_GO        0                               /* go */
 223 #define CSR_V_IE        6                               /* interrupt enable */
 224 #define CSR_V_DONE      7                               /* done */
 225 #define CSR_V_BUSY      11                              /* busy */
 226 #define CSR_V_ERR       15                              /* error */
 227 #define CSR_GO          (1u << CSR_V_GO)
 228 #define CSR_IE          (1u << CSR_V_IE)
 229 #define CSR_DONE        (1u << CSR_V_DONE)
 230 #define CSR_BUSY        (1u << CSR_V_BUSY)
 231 #define CSR_ERR         (1u << CSR_V_ERR)
 232
 233 /* Timers */
 234
 235 #define TMR_CLK         0                               /* 100Hz clock */
 236
 237 /* I/O system definitions */
 238
 239 #define DZ_MUXES        4                               /* max # of DZV muxes */
 240 #define DZ_LINES        4                               /* lines per DZV mux */
 241 #define VH_MUXES        4                               /* max # of DHQ muxes */
 242 #define MT_MAXFR        (1 << 16)                       /* magtape max rec */
 243 #define AUTO_LNT        34                              /* autoconfig ranks */
 244
 245 #define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
 246 #define DEV_V_QBUS      (DEV_V_UF + 1)                  /* Qbus */
 247 #define DEV_V_Q18       (DEV_V_UF + 2)                  /* Qbus, mem <= 256KB */
 248 #define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
 249 #define DEV_UBUS        (1u << DEV_V_UBUS)
 250 #define DEV_QBUS        (1u << DEV_V_QBUS)
 251 #define DEV_Q18         (1u << DEV_V_Q18)
 252 #define DEV_FLTA        (1u << DEV_V_FLTA)
 253
 254 #define UNIBUS          FALSE                           /* 22b only */
 255
 256 #define DEV_RDX         16                              /* default device radix */
 257
 258 /* Device information block */
 259
 260 #define VEC_DEVMAX      4                               /* max device vec */
 261
 262 typedef struct {
 263     uint32              ba;                             /* base addr */
 264     uint32              lnt;                            /* length */
 265     t_stat              (*rd)(int32 *dat, int32 ad, int32 md);
 266     t_stat              (*wr)(int32 dat, int32 ad, int32 md);
 267     int32               vnum;                           /* vectors: number */
 268     int32               vloc;                           /* locator */
 269     int32               vec;                            /* value */
 270     int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
 271     } DIB;
 272
 273 /* I/O page layout - RQB,RQC,RQD float based on number of DZ's */
 274
 275 #define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
 276 #define IOLN_DZ         010
 277 #define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
 278 #define IOLN_RQB        004
 279 #define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
 280 #define IOLN_RQC        004
 281 #define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
 282 #define IOLN_RQD        004
 283 #define IOBA_VH         (IOPAGEBASE + 000440)           /* DHQ11 */
 284 #define IOLN_VH         020
 285 #define IOBA_RQ         (IOPAGEBASE + 012150)           /* RQDX3 */
 286 #define IOLN_RQ         004
 287 #define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
 288 #define IOLN_TS         004
 289 #define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
 290 #define IOLN_RL         012
 291 #define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
 292 #define IOLN_XQ         020
 293 #define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
 294 #define IOLN_XQB        020
 295 #define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
 296 #define IOLN_TQ         004
 297 #define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
 298 #define IOLN_XU         010
 299 #define IOBA_RP         (IOPAGEBASE + 016700)           /* RP/RM */
 300 #define IOLN_RP         054
 301 #define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
 302 #define IOLN_CR         010
 303 #define IOBA_RX         (IOPAGEBASE + 017170)           /* RXV11 */
 304 #define IOLN_RX         004
 305 #define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
 306 #define IOLN_RY         004
 307 #define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
 308 #define IOLN_QDSS       002
 309 #define IOBA_DBL        (IOPAGEBASE + 017500)           /* doorbell */
 310 #define IOLN_DBL        002
 311 #define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
 312 #define IOLN_LPT        004
 313 #define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
 314 #define IOLN_PTR        004
 315 #define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
 316 #define IOLN_PTP        004
 317
 318 /* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14
 319    Within each IPL, priority is right to left
 320 */
 321
 322 /* IPL 17 */
 323
 324 /* IPL 16 */
 325
 326 #define INT_V_CLK       0                               /* clock */
 327
 328 /* IPL 15 */
 329
 330 #define INT_V_RQ        0                               /* RQDX3 */
 331 #define INT_V_RL        1                               /* RLV12/RL02 */
 332 #define INT_V_DZRX      2                               /* DZ11 */
 333 #define INT_V_DZTX      3
 334 #define INT_V_RP        4                               /* RP,RM drives */
 335 #define INT_V_TS        5                               /* TS11/TSV05 */
 336 #define INT_V_TQ        6                               /* TMSCP */
 337 #define INT_V_XQ        7                               /* DEQNA/DELQA */
 338 #define INT_V_RY        8                               /* RXV21 */
 339
 340 /* IPL 14 */
 341
 342 #define INT_V_TTI       0                               /* console */
 343 #define INT_V_TTO       1
 344 #define INT_V_PTR       2                               /* PC11 */
 345 #define INT_V_PTP       3
 346 #define INT_V_LPT       4                               /* LP11 */
 347 #define INT_V_CSI       5                               /* SSC cons UART */
 348 #define INT_V_CSO       6
 349 #define INT_V_TMR0      7                               /* SSC timers */
 350 #define INT_V_TMR1      8
 351 #define INT_V_VHRX      9                               /* DHQ11 */
 352 #define INT_V_VHTX      10
 353 #define INT_V_QDSS      11                              /* QDSS */
 354 #define INT_V_CR        12
 355
 356 #define INT_CLK         (1u << INT_V_CLK)
 357 #define INT_RQ          (1u << INT_V_RQ)
 358 #define INT_RL          (1u << INT_V_RL)
 359 #define INT_DZRX        (1u << INT_V_DZRX)
 360 #define INT_DZTX        (1u << INT_V_DZTX)
 361 #define INT_RP          (1u << INT_V_RP)
 362 #define INT_TS          (1u << INT_V_TS)
 363 #define INT_TQ          (1u << INT_V_TQ)
 364 #define INT_XQ          (1u << INT_V_XQ)
 365 #define INT_RY          (1u << INT_V_RY)
 366 #define INT_TTI         (1u << INT_V_TTI)
 367 #define INT_TTO         (1u << INT_V_TTO)
 368 #define INT_PTR         (1u << INT_V_PTR)
 369 #define INT_PTP         (1u << INT_V_PTP)
 370 #define INT_LPT         (1u << INT_V_LPT)
 371 #define INT_CSI         (1u << INT_V_CSI)
 372 #define INT_CSO         (1u << INT_V_CSO)
 373 #define INT_TMR0        (1u << INT_V_TMR0)
 374 #define INT_TMR1        (1u << INT_V_TMR1)
 375 #define INT_VHRX        (1u << INT_V_VHRX)
 376 #define INT_VHTX        (1u << INT_V_VHTX)
 377 #define INT_QDSS        (1u << INT_V_QDSS)
 378 #define INT_CR          (1u << INT_V_CR)
 379
 380 #define IPL_CLK         (0x16 - IPL_HMIN)                       /* relative IPL */
 381 #define IPL_RQ          (0x15 - IPL_HMIN)
 382 #define IPL_RL          (0x15 - IPL_HMIN)
 383 #define IPL_DZRX        (0x15 - IPL_HMIN)
 384 #define IPL_DZTX        (0x15 - IPL_HMIN)
 385 #define IPL_RP          (0x15 - IPL_HMIN)
 386 #define IPL_TS          (0x15 - IPL_HMIN)
 387 #define IPL_TQ          (0x15 - IPL_HMIN)
 388 #define IPL_XQ          (0x15 - IPL_HMIN)
 389 #define IPL_RY          (0x15 - IPL_HMIN)
 390 #define IPL_TTI         (0x14 - IPL_HMIN)
 391 #define IPL_TTO         (0x14 - IPL_HMIN)
 392 #define IPL_PTR         (0x14 - IPL_HMIN)
 393 #define IPL_PTP         (0x14 - IPL_HMIN)
 394 #define IPL_LPT         (0x14 - IPL_HMIN)
 395 #define IPL_CSI         (0x14 - IPL_HMIN)
 396 #define IPL_CSO         (0x14 - IPL_HMIN)
 397 #define IPL_TMR0        (0x14 - IPL_HMIN)
 398 #define IPL_TMR1        (0x14 - IPL_HMIN)
 399 #define IPL_VHRX        (0x14 - IPL_HMIN)
 400 #define IPL_VHTX        (0x14 - IPL_HMIN)
 401 #define IPL_QDSS        (0x14 - IPL_HMIN)
 402 #define IPL_CR          (0x14 - IPL_HMIN)
 403
 404 #define IPL_HMAX        0x17                            /* highest hwre level */
 405 #define IPL_HMIN        0x14                            /* lowest hwre level */
 406 #define IPL_HLVL        (IPL_HMAX - IPL_HMIN + 1)       /* # hardware levels */
 407 #define IPL_SMAX        0xF                             /* highest swre level */
 408
 409 /* Device vectors */
 410
 411 #define VEC_Q           0x200                           /* Qbus vector offset */
 412 #define VEC_PTR         (VEC_Q + 0070)
 413 #define VEC_PTP         (VEC_Q + 0074)
 414 #define VEC_XQ          (VEC_Q + 0120)
 415 #define VEC_XU          (VEC_Q + 0120)
 416 #define VEC_RQ          (VEC_Q + 0154)
 417 #define VEC_RL          (VEC_Q + 0160)
 418 #define VEC_LPT         (VEC_Q + 0200)
 419 #define VEC_TS          (VEC_Q + 0224)
 420 #define VEC_CR          (VEC_Q + 0230)
 421 #define VEC_RP          (VEC_Q + 0254)
 422 #define VEC_TQ          (VEC_Q + 0260)
 423 #define VEC_RX          (VEC_Q + 0264)
 424 #define VEC_RY          (VEC_Q + 0264)
 425 #define VEC_DZRX        (VEC_Q + 0300)
 426 #define VEC_DZTX        (VEC_Q + 0304)
 427 #define VEC_VHRX        (VEC_Q + 0310)
 428 #define VEC_VHTX        (VEC_Q + 0314)
 429
 430 /* Interrupt macros */
 431
 432 #define IVCL(dv)        ((IPL_##dv * 32) + INT_V_##dv)
 433 #define IREQ(dv)        int_req[IPL_##dv]
 434 #define SET_INT(dv)     int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
 435 #define CLR_INT(dv)     int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
 436 #define IORETURN(f,v)   ((f)? (v): SCPE_OK)             /* cond error return */
 437
 438 /* Logging */
 439
 440 #define LOG_CPU_I       0x1                             /* intexc */
 441 #define LOG_CPU_R       0x2                             /* REI */
 442 #define LOG_CPU_P       0x4                             /* context */
 443
 444 /* Function prototypes for virtual memory interface */
 445
 446 int32 Read (uint32 va, int32 lnt, int32 acc);
 447 void Write (uint32 va, int32 val, int32 lnt, int32 acc);
 448
 449 /* Function prototypes for physical memory interface (inlined) */
 450
 451 SIM_INLINE_GCC int32 ReadB (uint32 pa);
 452 SIM_INLINE_GCC int32 ReadW (uint32 pa);
 453 SIM_INLINE_GCC int32 ReadL (uint32 pa);
 454 SIM_INLINE_GCC int32 ReadLP (uint32 pa);
 455 SIM_INLINE_GCC void WriteB (uint32 pa, int32 val);
 456 SIM_INLINE_GCC void WriteW (uint32 pa, int32 val);
 457 SIM_INLINE_GCC void WriteL (uint32 pa, int32 val);
 458 void WriteLP (uint32 pa, int32 val);
 459
 460 /* Function prototypes for I/O */
 461
 462 int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
 463 int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
 464 int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);
 465 int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);
 466
 467 t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);
 468 t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);
 469 t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);
 470 t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);
 471 t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
 472 t_stat auto_config (char *name, int32 num);
 473
 474 int32 clk_cosched (int32 wait);
 475
 476 #endif