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196ba1fc PH |
1 | /* pdp8_clk.c: PDP-8 real-time clock simulator\r |
2 | \r | |
3 | Copyright (c) 1993-2007, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | clk real time clock\r | |
27 | \r | |
28 | 18-Jun-07 RMS Added UNIT_IDLE flag\r | |
29 | 01-Mar-03 RMS Aded SET/SHOW CLK FREQ support\r | |
30 | 04-Oct-02 RMS Added DIB, device number support\r | |
31 | 30-Dec-01 RMS Removed for generalized timers\r | |
32 | 05-Sep-01 RMS Added terminal multiplexor support\r | |
33 | 17-Jul-01 RMS Moved function prototype\r | |
34 | 05-Mar-01 RMS Added clock calibration support\r | |
35 | \r | |
36 | Note: includes the IOT's for both the PDP-8/E and PDP-8/A clocks\r | |
37 | */\r | |
38 | \r | |
39 | #include "pdp8_defs.h"\r | |
40 | \r | |
41 | extern int32 int_req, int_enable, dev_done, stop_inst;\r | |
42 | \r | |
43 | int32 clk_tps = 60; /* ticks/second */\r | |
44 | int32 tmxr_poll = 16000; /* term mux poll */\r | |
45 | \r | |
46 | int32 clk (int32 IR, int32 AC);\r | |
47 | t_stat clk_svc (UNIT *uptr);\r | |
48 | t_stat clk_reset (DEVICE *dptr);\r | |
49 | t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
50 | t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
51 | \r | |
52 | /* CLK data structures\r | |
53 | \r | |
54 | clk_dev CLK device descriptor\r | |
55 | clk_unit CLK unit descriptor\r | |
56 | clk_reg CLK register list\r | |
57 | */\r | |
58 | \r | |
59 | DIB clk_dib = { DEV_CLK, 1, { &clk } };\r | |
60 | \r | |
61 | UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 16000 };\r | |
62 | \r | |
63 | REG clk_reg[] = {\r | |
64 | { FLDATA (DONE, dev_done, INT_V_CLK) },\r | |
65 | { FLDATA (ENABLE, int_enable, INT_V_CLK) },\r | |
66 | { FLDATA (INT, int_req, INT_V_CLK) },\r | |
67 | { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },\r | |
68 | { DRDATA (TPS, clk_tps, 8), PV_LEFT + REG_HRO },\r | |
69 | { NULL }\r | |
70 | };\r | |
71 | \r | |
72 | MTAB clk_mod[] = {\r | |
73 | { MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",\r | |
74 | &clk_set_freq, NULL, NULL },\r | |
75 | { MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",\r | |
76 | &clk_set_freq, NULL, NULL },\r | |
77 | { MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,\r | |
78 | NULL, &clk_show_freq, NULL },\r | |
79 | { MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev },\r | |
80 | { 0 }\r | |
81 | };\r | |
82 | \r | |
83 | DEVICE clk_dev = {\r | |
84 | "CLK", &clk_unit, clk_reg, clk_mod,\r | |
85 | 1, 0, 0, 0, 0, 0,\r | |
86 | NULL, NULL, &clk_reset,\r | |
87 | NULL, NULL, NULL,\r | |
88 | &clk_dib, 0\r | |
89 | };\r | |
90 | \r | |
91 | /* IOT routine\r | |
92 | \r | |
93 | IOT's 6131-6133 are the PDP-8/E clock\r | |
94 | IOT's 6135-6137 are the PDP-8/A clock\r | |
95 | */\r | |
96 | \r | |
97 | int32 clk (int32 IR, int32 AC)\r | |
98 | {\r | |
99 | switch (IR & 07) { /* decode IR<9:11> */\r | |
100 | \r | |
101 | case 1: /* CLEI */\r | |
102 | int_enable = int_enable | INT_CLK; /* enable clk ints */\r | |
103 | int_req = INT_UPDATE; /* update interrupts */\r | |
104 | return AC;\r | |
105 | \r | |
106 | case 2: /* CLDI */\r | |
107 | int_enable = int_enable & ~INT_CLK; /* disable clk ints */\r | |
108 | int_req = int_req & ~INT_CLK; /* update interrupts */\r | |
109 | return AC;\r | |
110 | \r | |
111 | case 3: /* CLSC */\r | |
112 | if (dev_done & INT_CLK) { /* flag set? */\r | |
113 | dev_done = dev_done & ~INT_CLK; /* clear flag */\r | |
114 | int_req = int_req & ~INT_CLK; /* clear int req */\r | |
115 | return IOT_SKP + AC;\r | |
116 | }\r | |
117 | return AC;\r | |
118 | \r | |
119 | case 5: /* CLLE */\r | |
120 | if (AC & 1) int_enable = int_enable | INT_CLK; /* test AC<11> */\r | |
121 | else int_enable = int_enable & ~INT_CLK;\r | |
122 | int_req = INT_UPDATE; /* update interrupts */\r | |
123 | return AC;\r | |
124 | \r | |
125 | case 6: /* CLCL */\r | |
126 | dev_done = dev_done & ~INT_CLK; /* clear flag */\r | |
127 | int_req = int_req & ~INT_CLK; /* clear int req */\r | |
128 | return AC;\r | |
129 | \r | |
130 | case 7: /* CLSK */\r | |
131 | return (dev_done & INT_CLK)? IOT_SKP + AC: AC;\r | |
132 | \r | |
133 | default:\r | |
134 | return (stop_inst << IOT_V_REASON) + AC;\r | |
135 | } /* end switch */\r | |
136 | }\r | |
137 | \r | |
138 | /* Unit service */\r | |
139 | \r | |
140 | t_stat clk_svc (UNIT *uptr)\r | |
141 | {\r | |
142 | int32 t;\r | |
143 | \r | |
144 | dev_done = dev_done | INT_CLK; /* set done */\r | |
145 | int_req = INT_UPDATE; /* update interrupts */\r | |
146 | t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */\r | |
147 | sim_activate (&clk_unit, t); /* reactivate unit */\r | |
148 | tmxr_poll = t; /* set mux poll */\r | |
149 | return SCPE_OK;\r | |
150 | }\r | |
151 | \r | |
152 | /* Reset routine */\r | |
153 | \r | |
154 | t_stat clk_reset (DEVICE *dptr)\r | |
155 | {\r | |
156 | int32 t;\r | |
157 | \r | |
158 | dev_done = dev_done & ~INT_CLK; /* clear done, int */\r | |
159 | int_req = int_req & ~INT_CLK;\r | |
160 | int_enable = int_enable & ~INT_CLK; /* clear enable */\r | |
161 | t = sim_rtcn_init (clk_unit.wait, TMR_CLK);\r | |
162 | sim_activate_abs (&clk_unit, t); /* activate unit */\r | |
163 | tmxr_poll = t;\r | |
164 | return SCPE_OK;\r | |
165 | }\r | |
166 | \r | |
167 | /* Set frequency */\r | |
168 | \r | |
169 | t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)\r | |
170 | {\r | |
171 | if (cptr) return SCPE_ARG;\r | |
172 | if ((val != 50) && (val != 60)) return SCPE_IERR;\r | |
173 | clk_tps = val;\r | |
174 | return SCPE_OK;\r | |
175 | }\r | |
176 | \r | |
177 | /* Show frequency */\r | |
178 | \r | |
179 | t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)\r | |
180 | {\r | |
181 | fprintf (st, (clk_tps == 50)? "50Hz": "60Hz");\r | |
182 | return SCPE_OK;\r | |
183 | }\r |