PDP8/pdp8_clk.c

   1 /* pdp8_clk.c: PDP-8 real-time clock simulator
   2
   3    Copyright (c) 1993-2007, Robert M Supnik
   4
   5    Permission is hereby granted, free of charge, to any person obtaining a
   6    copy of this software and associated documentation files (the "Software"),
   7    to deal in the Software without restriction, including without limitation
   8    the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9    and/or sell copies of the Software, and to permit persons to whom the
  10    Software is furnished to do so, subject to the following conditions:
  11
  12    The above copyright notice and this permission notice shall be included in
  13    all copies or substantial portions of the Software.
  14
  15    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18    ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19    IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21
  22    Except as contained in this notice, the name of Robert M Supnik shall not be
  23    used in advertising or otherwise to promote the sale, use or other dealings
  24    in this Software without prior written authorization from Robert M Supnik.
  25
  26    clk          real time clock
  27
  28    18-Jun-07    RMS     Added UNIT_IDLE flag
  29    01-Mar-03    RMS     Aded SET/SHOW CLK FREQ support
  30    04-Oct-02    RMS     Added DIB, device number support
  31    30-Dec-01    RMS     Removed for generalized timers
  32    05-Sep-01    RMS     Added terminal multiplexor support
  33    17-Jul-01    RMS     Moved function prototype
  34    05-Mar-01    RMS     Added clock calibration support
  35
  36    Note: includes the IOT's for both the PDP-8/E and PDP-8/A clocks
  37 */
  38
  39 #include "pdp8_defs.h"
  40
  41 extern int32 int_req, int_enable, dev_done, stop_inst;
  42
  43 int32 clk_tps = 60;                                     /* ticks/second */
  44 int32 tmxr_poll = 16000;                                /* term mux poll */
  45
  46 int32 clk (int32 IR, int32 AC);
  47 t_stat clk_svc (UNIT *uptr);
  48 t_stat clk_reset (DEVICE *dptr);
  49 t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);
  50 t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);
  51
  52 /* CLK data structures
  53
  54    clk_dev      CLK device descriptor
  55    clk_unit     CLK unit descriptor
  56    clk_reg      CLK register list
  57 */
  58
  59 DIB clk_dib = { DEV_CLK, 1, { &clk } };
  60
  61 UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 16000 };
  62
  63 REG clk_reg[] = {
  64     { FLDATA (DONE, dev_done, INT_V_CLK) },
  65     { FLDATA (ENABLE, int_enable, INT_V_CLK) },
  66     { FLDATA (INT, int_req, INT_V_CLK) },
  67     { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
  68     { DRDATA (TPS, clk_tps, 8), PV_LEFT + REG_HRO },
  69     { NULL }
  70     };
  71
  72 MTAB clk_mod[] = {
  73     { MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
  74       &clk_set_freq, NULL, NULL },
  75     { MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",
  76       &clk_set_freq, NULL, NULL },
  77     { MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,
  78       NULL, &clk_show_freq, NULL },
  79     { MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev },
  80     { 0 }
  81     };
  82
  83 DEVICE clk_dev = {
  84     "CLK", &clk_unit, clk_reg, clk_mod,
  85     1, 0, 0, 0, 0, 0,
  86     NULL, NULL, &clk_reset,
  87     NULL, NULL, NULL,
  88     &clk_dib, 0
  89     };
  90
  91 /* IOT routine
  92
  93    IOT's 6131-6133 are the PDP-8/E clock
  94    IOT's 6135-6137 are the PDP-8/A clock
  95 */
  96
  97 int32 clk (int32 IR, int32 AC)
  98 {
  99 switch (IR & 07) {                                      /* decode IR<9:11> */
 100
 101     case 1:                                             /* CLEI */
 102         int_enable = int_enable | INT_CLK;              /* enable clk ints */
 103         int_req = INT_UPDATE;                           /* update interrupts */
 104         return AC;
 105
 106     case 2:                                             /* CLDI */
 107         int_enable = int_enable & ~INT_CLK;             /* disable clk ints */
 108         int_req = int_req & ~INT_CLK;                   /* update interrupts */
 109         return AC;
 110
 111     case 3:                                             /* CLSC */
 112         if (dev_done & INT_CLK) {                       /* flag set? */
 113             dev_done = dev_done & ~INT_CLK;             /* clear flag */
 114             int_req = int_req & ~INT_CLK;               /* clear int req */
 115             return IOT_SKP + AC;
 116             }
 117         return AC;
 118
 119     case 5:                                             /* CLLE */
 120         if (AC & 1) int_enable = int_enable | INT_CLK;  /* test AC<11> */
 121         else int_enable = int_enable & ~INT_CLK;
 122         int_req = INT_UPDATE;                           /* update interrupts */
 123         return AC;
 124
 125     case 6:                                             /* CLCL */
 126         dev_done = dev_done & ~INT_CLK;                 /* clear flag */
 127         int_req = int_req & ~INT_CLK;                   /* clear int req */
 128         return AC;
 129
 130     case 7:                                             /* CLSK */
 131         return (dev_done & INT_CLK)? IOT_SKP + AC: AC;
 132
 133     default:
 134         return (stop_inst << IOT_V_REASON) + AC;
 135         }                                               /* end switch */
 136 }
 137
 138 /* Unit service */
 139
 140 t_stat clk_svc (UNIT *uptr)
 141 {
 142 int32 t;
 143
 144 dev_done = dev_done | INT_CLK;                          /* set done */
 145 int_req = INT_UPDATE;                                   /* update interrupts */
 146 t = sim_rtcn_calb (clk_tps, TMR_CLK);                   /* calibrate clock */
 147 sim_activate (&clk_unit, t);                            /* reactivate unit */
 148 tmxr_poll = t;                                          /* set mux poll */
 149 return SCPE_OK;
 150 }
 151
 152 /* Reset routine */
 153
 154 t_stat clk_reset (DEVICE *dptr)
 155 {
 156 int32 t;
 157
 158 dev_done = dev_done & ~INT_CLK;                         /* clear done, int */
 159 int_req = int_req & ~INT_CLK;
 160 int_enable = int_enable & ~INT_CLK;                     /* clear enable */
 161 t = sim_rtcn_init (clk_unit.wait, TMR_CLK);
 162 sim_activate_abs (&clk_unit, t);                        /* activate unit */
 163 tmxr_poll = t;
 164 return SCPE_OK;
 165 }
 166
 167 /* Set frequency */
 168
 169 t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)
 170 {
 171 if (cptr) return SCPE_ARG;
 172 if ((val != 50) && (val != 60)) return SCPE_IERR;
 173 clk_tps = val;
 174 return SCPE_OK;
 175 }
 176
 177 /* Show frequency */
 178
 179 t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)
 180 {
 181 fprintf (st, (clk_tps == 50)? "50Hz": "60Hz");
 182 return SCPE_OK;
 183 }